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Be - Computer Engineering - Semester 3 - 2023 - October - Digital Electronics and Logic Design Deld Pattern 2019

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0% found this document useful (0 votes)
61 views2 pages

Be - Computer Engineering - Semester 3 - 2023 - October - Digital Electronics and Logic Design Deld Pattern 2019

Uploaded by

tanmaynanaware20
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Total No. of Questions : 6] SEAT No.

8
23
P-5397 [Total No. of Pages : 2

ic-
tat
[6186]-523

7s
S.E. (Computer Engineering) (Insem.)

9:0
02 91
0:4
DIGITAL ELECTRONICS AND LOGIC DESIGN

0
31
(2019 Pattern) (Semester - III) (210245)
3/1 13
0

om
Time : 1 Hour] [Max. Marks : 30
0/2
.23 GP

Instructions to the candidates :


1) Attempt Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6.
E
81

rsic-238
.c
2) Neat diagrams must be drawn wherever necessary.
C

3) Assume suitable data, if necessary.


16

tat
8.2

es
Q1) a) Simplify the following function F(A, B, C, D) = å m(0, 2, 4, 5, 6, 7, 8,

:07
.24

10, 13, 15).


:49p [5]
02P 91
49

0a
b) Simplify the following function [5]
0
31
3/1 n13

F(A, B, C, D) = π m(0, 2, 3, 8, 9, 12, 13, 15)


P0

OR
0/2
8 1 io
.23 tG

Q2) a) Simplify the following function F(A, B, C, D) = å m(0 2 4 5 6 8, 10 15)


CE
s

+d(7 13 14) [5]

38
ue

c-2
b) Simplify the following function [5]
i
16

tat
F(w, x, y, z) = å m(4, 5, 7, 12, 14, 15) +d(3, 8, 10)
Q
8.2

7s
.24

9:0
PU

91
49

Q3) a) Draw and explain 4-bit BCD adder using IC 7483. Explain any two BCD
0:4
30

addition operations. [5]


31
SP

01

b) Design a 4 bit Gray to Binary code converter? State the application of


02

Gray code. [5]


0/2
GP
3/1

OR
CE
81

Q4) a) Design a 4 bit BCD to Excess-3 code converter circuit using logic gates.[5]
.23

b) What is Multiplexer? Design 8:1 multiplexer with a dual 4:1 - multiplexer.


16

[5]
8.2

P.T.O.
.24
49
Q5) a) What do you mean by half adder and full adder? How will you implement

8
23
full adder using half adder? Draw the circuit diagram. [5]

ic-
b) Convert the following expressions into their standard SOP form [5]

tat
7s
i) Y = AB + AC + BC

9:0
ii) Y = A + BC + ABC

02 91
0:4
OR

0
31
Q6) a) 3/1 13
Minimize the function using K-map and implement Using NAND gates,
0

om
F(A, B, C, D) = å m(4, 5, 6, 7, 8, 12) +d(1, 2, 3, 9, 11, 14).
0/2
[5]
.23 GP

b) Write a short note on 2 bit comparator? [5]


E
81

rsic-238
.c
C


16

tat
8.2

es
:07
.24

:49p
02P 91
49

0a
0
31
3/1 n13
P0
0/2
8 1 io
.23 tG
CE
s

38
ue

c-2
i
16

tat
Q
8.2

7s
.24

9:0
PU

91
49

0:4
30
31
SP

01
02
0/2
GP
3/1
CE
81
.23
16
8.2
.24

[6186]-523 2
49

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