Lecture 15:

Differential Pairs (Part 2)

Gu-Yeon Wei
Division of Engineering and Applied Sciences
Harvard University
[email protected]

Wei 1
 Overview

• Reading
– S&S: Chapter 6.6
• Supplemental Reading
– S&S: Chapter 6.9
– Razavi, Design of Analog CMOS Integrated Circuits: Chapter 4
• Background
– Our treatment of MOS differential pairs has assumed ideal
elements. However, real devices suffer a variety of mismatches.
This lecture will investigate how mismatches in the load resistor
and transistors affect performance of the differential pair. We will
then conclude our discussion of differential pair amplifiers with an
active-load differential pair that only uses MOS devices.

Wei ES154 - Lecture 15 2

 Another Way to Analyze MOS Differential Pairs

• Let’s investigate another

technique for analyzing the RD RD RD RD
MOS differential pair
Vout1 X Y Vout2 Vout1 X Y Vout2
• For the differential pair circuit
on the left (driven by two
independent signals), compute V Vin2 Vin1
in1
the output using superposition
I I
– Start with Vin1, set Vin2=0
and first solve for X w.r.t.
Vin1
– Reduces to a degenerated
common-source amp
– neglecting channel-length RD
modulation and body- RD RD
effect, RS = 1/gm2 Vout1 X
Vout1 X Y Vout2
– so…
M1
VX − g m1 RD − RD M2 Vin1
= = Vin1 RS
Vin1 1 + g m1 RS 1 1
+ RS
g m1 g m 2

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 • Now, solve for Y w.r.t. Vin1
• Replace circuit within box with a Thevenin equivalent RD RD
– M1 is a source follower with VT=Vin1
Vout1 X Y Vout2
– RT=1/gm1
• The circuit reduces to a common-gate amplifier where… M1 M2

VY RD Vin1
=
Vin1 1 1
+
g m1 g m 2
• So, overall (assuming gm1 = gm2)

− 2 RD
VX − VY = Vin1 = − g m RDVin1
due to Vin1
1 g m1 + 1 g m 2 RD

by symmetry Y Vout2

V X − VY due to Vin 2
= g m RDVin 2 RT

VT
V − VY
Ad = X = − g m RD
Vin1 − Vin 2

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 Offsets in MOS Differential Pair

• There are 3 main sources of offset that affect the performance of

MOS differential pair circuits
– Mismatch in load resistors
– Mismatch in W/L of differential pair devices
– Mismatch in Vt of differential pair devices
• Let’s investigate each individually

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 Resistor Mismatch

• For the differential pair circuit shown, consider the case

where RD1 RD2
– Load resistors are mismatched by ∆RD
∆R VO
RD1, 2 = RD ± D
2
– All other devices parameters are perfectly matched
• With both inputs grounded, I1 = I2= I/2, but VO is not zero I1 I2
due to differences in the voltages across the load resistors
I I
VO = ∆RD
2
– It is common to find the input-referred offset which is
calculated as
VOS = VO Ad
– since Ad = gmRD
I VGS − Vt ∆RD
gm = VOS =
VGS − Vt 2 RD

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 W/L Mismatch

• Now consider what happens when device sizes W/L are mismatched for the two
differential pair MOS devices M1 and M2
W  W 1 W 
  = ± ∆ 
 L 1, 2 L 2  L 

• This mismatch causes mismatch in the currents that flow through M1 and M2

I I ∆(W L )
I1, 2 = ±
2 2 2(W L )
– This mismatch results in VO

∆(W L )
VO = I RD
2(W L )

– So in the input referred offset is…

VGS − Vt ∆(W L )
VOS = VO Ad VOS =
2 (W L )
Wei ES154 - Lecture 15 7
 Vt Mismatch

• Lastly, consider mismatches in the threshold voltage

∆Vt
Vt1, 2 = Vt ±
2
• Again, currents I1 and I2 will differ according to the following saturation current
equation
2 2
1 W  ∆V  1 W 2 ∆Vt 
I1 = µ n Cox VGS − Vt − t  = µ n Cox (VGS − Vt ) 1 − 
2 L  2  2 L  2(VGS − V )
t 

– For small ∆Vt << 2(VGS-Vt)

1 W  ∆Vt  I ∆I I  ∆Vt 
I1, 2 ≅ µ nCox (VGS − Vt )2 1 m  = m ∆I =  
2 L  VGS − Vt  2 2 2  VGS − Vt 

– Again, using VOS=VO/Ad (Ad = gmRD and VO =2∆IRD) we get…

2(∆I )(RD ) 2 IRD  ∆Vt  VGS − Vt

VOS = =   = ∆Vt
Ad 2  VGS − Vt  IRD

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 Mismatch Summary

• The 3 sources of mismatch can be combined into one equation:

VGS − Vt  ∆RD ∆(W L ) 

VOS = ∆Vt +  + 
2  DR (W L ) 

– arising from Vt, RD, and W/L mismatches

• Notice that offsets due to ∆RD and ∆W/L are functions of the
overdrive voltage

Wei ES154 - Lecture 15 9

 Differential Pair with MOS Loads

Vb

Vout Vout

Vin Vin

I I

• Consider the above two MOS loads in place of resistors

• Left:
– a diode connected pMOS has an effective resistance of 1/gmP
g mN
Ad = − g mN (1 g mP || roN || roP ) ≅ −
g mP
• Right:
– pMOS devices in saturation have effective resistance of roP
Ad = − g mN (roN || roP )

Wei ES154 - Lecture 15 10

 Active-Loaded CMOS Differential Amplifier

• A commonly used amplifier topology in CMOS technologies

• Output is taken single-endedly for a differential input
– with a vid/2 at the gate of M1, i1 flows M3 M4

i1 = g m (vid 2) i1
vo
– i1 is also mirrored through the M3-M4 current mirror i1
i2
– a –vid/2 at the gate of M2 causes i2 to also flow through M2
i2 = g m (vid 2) M1 M2
vid
• Given that ID=I/2 (nominally)
I
gm = I
VGS − Vt

• The voltage at the output then is given by…

vo = (i1 + i2 )(ro 2 || ro 4 ) = 2i1 (ro 2 || ro 4 )
ro
Ad = g m (ro 2 || ro 4 ) ≅ g m
2

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 Next Time

• Reading:
– S&S: Chapter 6.6
• Supplemental Reading:
– S&S: Chapter 6.4
– Razavi: Chapter 5

• Overview
– We have seen that transistor transconductance and the effective
load resistance set the gain of differential amplifiers. We will next
investigate a technique called cascoding that can increase the
output resistance of MOS devices in saturation. Utilizing this
technique, we can build higher quality current sources and
amplifiers (w/ MOS loads) with higher gain. We will also see the
trade offs this technique imposes.

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