TLV 2432 A
TLV 2432 A
D Output Swing Includes Both Supply Rails D Very Low Supply Current . . . 125 µA Per
D Extended Common-Mode Input Voltage Channel Max
Range . . . 0 V to 4.5 V (Min) with 5-V Single D 600-Ω Output Drive
Supply D Macromodel Included
D No Phase Inversion D Available in Q-Temp Automotive
D Low Noise . . . 18 nV/√Hz Typ at f = 1 kHz HighRel Automotive Applications
D Low Input Offset Voltage Configuration Control / Print Support
950 µV Max at TA = 25°C (TLV243xA) Qualification to Automotive Standards
D Low Input Bias Current . . . 1 pA Typ
HIGH-LEVEL OUTPUT VOLTAGE
description vs
HIGH-LEVEL OUTPUT CURRENT
The TLV243x and TLV243xA are low-voltage 5
operational amplifier from Texas Instruments. The
VDD = 5 V
common-mode input voltage range for each
ÁÁ
TA = 25°C
dynamic range in single- or split-supply applica-
ÁÁ
tions. This family is fully characterized at 3-V and TA =–40°C
VOH
ÁÁ
5-V supplies and is optimized for low-voltage
V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TLV2432
FK PACKAGE
(TOP VIEW)
VDD+
1OUT
TLV2434
TLV2432
NC
NC
NC
D OR PW PACKAGE
U PACKAGE
(TOP VIEW)
(TOP VIEW)
3 2 1 20 19
NC 4 18 NC
NC 1 10 NC 1OUT 1 14 4OUT
1IN – 5 17 2OUT
1OUT 2 9 VDD + 1IN – 2 13 4IN –
NC 6 16 NC
1IN – 3 8 2OUT 1IN+ 3 12 4IN+
1IN + 7 15 2IN –
1IN + 4 7 2IN – VDD+ 4 11 VDD–/GND
NC 8 14 NC
9 10 11 12 13 VDD – /GND 5 6 2IN + 2IN+ 5 10 3IN+
2IN – 6 9 3IN –
VDD– /GND
2IN+
NC
NC
NC
2OUT 7 8 3OUT
NC – No internal connection
VB3
Q26
Q20
R5 C2
Q7 Q9 VDD–/GND
C1
OUT
Q11 Q16 R6 C3
VB3
VB2
Q2 Q5 Q14
Q21
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD
Input voltage, VI (any input, see Note 1): C and I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD
Input current, II (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Total current into VDD + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Total current out of VDD – . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix (dual) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
I suffix (quad) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD – .
2. Differential voltages are at IN+ with respect to IN –. Excessive current flows if input is brought below VDD – – 0.3 V.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
AV = – 1, 0 1%
To 0.1% 64
6.4
Step = 0.5 V to 2.5 V,,
ts Settling time 25°C µs
RL = 2 kه,
CL = 100 pF‡ To 0.01%
0 01% 14 1
14.1
AV = – 1, 0 1%
To 0.1% 64
6.4
Step = 0.5 V to 2.5 V,,
ts Settling time 25°C µs
RL = 2 kه,
CL = 100 pF‡ To 0.01%
0 01% 14 1
14.1
AV = – 1, To 0.1%
0 1% 64
6.4
Step = 1.5 V to 3.5 V,,
ts Settling time 25°C µs
RL = 2 kه,
CL = 100 pF‡ To 0.01%
0 01% 13 1
13.1
AV = – 1, 0 1%
To 0.1% 64
6.4
Step = 1.5 V to 3.5 V,,
ts Settling time 25°C µs
RL = 2 kه,
CL = 100 pF‡ To 0.01%
0 01% 13 1
13.1
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Distribution 2,3
,
VIO Input offset voltage
vs Common-mode input voltage 4,5
αVIO Temperature coefficient Distribution 6,7
IIB/IIO Input bias and input offset currents vs Free-air temperature 8
VOH High-level output voltage vs High-level output current 9,11
VOL Low-level output voltage vs Low-level output current 10,12
VO(PP) Maximum peak-to-peak output voltage vs Frequency 13
vs Supplyy voltage
g 14
IOS Short circuit output current
Short-circuit
vs Free-air temperature 15
VID Differential input voltage vs Output voltage 16,17
Differential gain vs Load resistance 18
AVD Large-signal differential voltage amplification vs Frequency 19,20
AVD Differential voltage amplification vs Free-air temperature 21,22
zo Output impedance vs Frequency 23,24
vs Frequency
q y 25
CMRR Common mode rejection ratio
Common-mode
vs Free-air temperature 26
vs Frequency
q y 27,28
,
kSVR Supply voltage rejection ratio
Supply-voltage
vs Free-air temperature 29
IDD Supply current vs Supply voltage 30
vs Load capacitance 31
SR Slew rate
vs Free-air temperature 32
VO Inverting large-signal pulse response 33,34
VO Voltage-follower large-signal pulse response 35,36
VO Inverting small-signal pulse response 37,38
VO Voltage-follower small-signal pulse response 39,40
Vn Equivalent input noise voltage vs Frequency 41, 42
Noise voltage (referred to input) Over a 10-second period 43
THD + N Total harmonic distortion plus noise vs Frequency 44,45
vs Free-air temperature 46
Gain bandwidth product
Gain-bandwidth
vs Supply voltage 47
vs Frequency
q y 19,20
,
φm Phase margin
vs Load capacitance 48
Gain margin vs Load capacitance 49
B1 Unity-gain bandwidth vs Load capacitance 50
TYPICAL CHARACTERISTICS
Percentage of Amplifiers – %
25 25
20 20
15 15
10 10
5 5
0 0
–1600 –800 0 800 1600 –1600 –800 0 800 1600
VIO – Input Offset Voltage – µV VIO – Input Offset Voltage – µV
Figure 2 Figure 3
1 1
0.5 0.5
0 0
–0.5
ÁÁÁ ÁÁ
–0.5
ÁÁÁ ÁÁ
–1
VVIO
–1
VVIO
ÁÁÁ –1.5
ÁÁ –1.5
–2 –2
–0.5 0 0.5 1 1.5 2 2.5 3 –0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VIC – Common-Mode Input Voltage – V VIC – Common-Mode Input Voltage – V
Figure 4 Figure 5
TYPICAL CHARACTERISTICS
Percentage of Amplifiers – %
15 15
10 10
5 5
0 0
–4 –3 –2 –1 0 1 2 3 4 –4 –3 –2 –1 0 1 2 3 4
αVIO – Temperature Coefficient – µV / °C αVIO – Temperature Coefficient – µV / °C
Figure 6 Figure 7
35 3
VDD± = ± 2.5 V VDD = 3 V
VIC = 0 V
30
OH – High-Level Output Voltage – V
VO = 0 2.5
RS = 50 Ω
25 TA = –40°C
IIB 2
TA = 25°C
20 TA = 125°C
1.5
15
IIO 1
10
ÁÁ
TA = 0°C
VOH
ÁÁ
0.5
IB and IIO
ÁÁ
ÁÁ
0 0
IIIB
25 45 65 85 105 125 0 3 6 9 12 15
TA – Free-Air Temperature – °C IOH – High-Level Output Current – mA
Figure 8 Figure 9
TYPICAL CHARACTERISTICS
0.8 3
TA = 125°C
0.6 TA = 85°C
TA = 25°C 2
ÁÁ
TA = 25°C
0.4
ÁÁ ÁÁ
TA = –40°C TA =–40°C
VOL
ÁÁ ÁÁ VOH
1
V
0.2
V
0 0
0 1 2 3 4 5 0 4 8 12 16 20
IOL – Low-Level Output Current – mA IOH – High-Level Output Current – Am
Figure 10 Figure 11
1.2 5
RL = 2 kΩ
VDD = 5 V VDD = 5 V TA = 25°C
VOL – Low-Level Output Voltage – V
1
4
TA = 125°C
0.8
TA = 85°C
3
0.6 VDD = 3 V
ÁÁÁ
0.4
TA = 25°C
ÁÁÁ ÁÁ
TA = –40°C
VOL
ÁÁÁ ÁÁ
0.2
VO(PP)
0
0 1 2 3 4
IOL – Low-Level Output Current – mA
5 ÁÁ 0
102 103 104 105 106
f – Frequency – Hz
Figure 12 Figure 13
TYPICAL CHARACTERISTICS
15 VIC = 2.5 V
5
5
0 0
–5
–5
–10 –10
IOS
VID = 100 mV
IIOS
–15 –15
–20
–20
2 3 4 5 6 7 8 9 10
–75 –50 –25 0 25 50 75 100 125
VDD – Supply Voltage – V TA – Free-Air Temperature – °C
Figure 14 Figure 15
VIC = 1.5 V
V ID – Differential Input Voltage – µ V
RL = 2 kΩ
TA = 25°C TA = 25°C
500 500
250 250
0 0
–250 –250
–500 –500
–750 –750
–1000 –1000
0 0.5 1 1.5 2 2.5 3 0 1 2 3 4 5
VO – Output Voltage – V VO – Output Voltage – V
Figure 16 Figure 17
TYPICAL CHARACTERISTICS
DIFFERENTIAL GAIN
vs
LOAD RESISTANCE
103
VO(PP) = 2 V
TA = 25°C VDD = 5 V
Differential Gain – V/ mV
VDD = 3 V
102
101
1
1 101 102 103
RL – Load Resistance – kΩ
Figure 18
TA = 25°C
Voltage Amplification – dB
m – Phase Margin
40 90°
20 45°
ÁÁ
φom
0 0°
ÁÁ
AVD
–20 –45°
–40 –90°
104 105 106 107
f – Frequency – Hz
Figure 19
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
80 180°
VDD = 3 V
RL = 2 kΩ
60 CL = 100 pF 135°
AVD – Large-Signal Differential TA = 25°C
Voltage Amplification – dB
m – Phase Margin
40 90°
20 45°
ÁÁ
φom
0 0°
ÁÁ
AVD
ÁÁ –20 –45°
–40 –90°
104 105 106 107
f – Frequency – Hz
Figure 20
VIC = 2.5 V
RL = 1 MΩ VO = 0.5 V to 2.5 V
1000
100
RL = 1 MΩ
100
10
10 RL = 2 kΩ
1
1
VDD = 5 V
VIC = 2.5 V RL = 2 kΩ
VO = 1 V to 4 V
0.1 0.1
– 75 – 50 – 25 0 25 50 75 100 125 – 75 – 50 – 25 0 25 50 75 100 125
TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C
Figure 21 Figure 22
TYPICAL CHARACTERISTICS
Ω
z o – Output Impedance – 0
z o – Output Impedance – 0
AV = 100
100 100 AV = 100
AV = 10
AV = 10
10 10
zo
zo
AV = 1
AV = 1
1 1
102 103 104 105 102 103 104 105
f – Frequency – Hz f – Frequency – Hz
Figure 23 Figure 24
TA = 25°C
CMRR – Common-Mode Rejection Ratio – dB
VDD = 5 V
VIC = 2.5 V VDD = 5 V
80 98
VDD = 3 V
VIC = 1.5 V
60 96
VDD = 3 V
40 94
20 92
0 90
102 103 104 105 106 – 75 – 50 – 25 0 25 50 75 100 125
f – Frequency – Hz TA – Free-Air Temperature – °C
Figure 25 Figure 26
TYPICAL CHARACTERISTICS
TA = 25°C
TA = 25°C
100 100
80 80
60 60
40 40
ÁÁ ÁÁ
ÁÁ ÁÁ
20 20
KSVR
KSVR
ÁÁ 0
101 102 103 104 105 106
ÁÁ 0
101 102 103 104 105 106
f – Frequency – Hz f – Frequency – Hz
Figure 27 Figure 28
VO = VDD/2
No Load
250 TA = 25°C
98
DD – Supply Current – µ A
TA = – 40°C
200
96
TA = 85°C
150
ÁÁ
94
ÁÁ
100
IIDD
92
ÁÁ
kSVR
VDD = 2.7 V to 8 V 50
VO = VDD/2
90 0
– 75 – 50 – 25 0 25 50 75 100 125 0 2 4 6 8 10
TA – Free-Air Temperature – °C VDD – Supply Voltage – V
Figure 29 Figure 30
TYPICAL CHARACTERISTICS
SR – Slew Rate – V/ µ s
0.4
SR – Slew Rate – V/
0.25
0.3
0.2
0.2
0.1 0.15
0
0.1
101 102 103 104 105 – 75 – 50 – 25 0 25 50 75 100 125
CL – Load Capacitance – pF
TA – Free-Air Temperature – °C
Figure 31 Figure 32
TA = 25°C
VO – Output Voltage – V
TA = 25°C
2
3
1.5
2
1
VO
VO
0.5 1
0 0
0 10 20 30 40 50 0 10 20 30 40 50
t – Time – µs t – Time – µs
Figure 33 Figure 34
TYPICAL CHARACTERISTICS
TA = 25°C
VO – Output Voltage – V
2
3
1.5
2
1
VO
VO
1
0.5
0 0
0 10 20 30 40 50 0 5 10 15 20 25 30 35 40 45 50
t – Time – µs t – Time – µs
Figure 35 Figure 36
TA = 25°C
VO – Output Voltage – V
1.54 2.54
1.52 2.52
1.5 2.5
VO
VO
1.48
V
2.48
1.46 2.46
1.44 2.44
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
t – Time – µs t – Time – µs
Figure 37 Figure 38
TYPICAL CHARACTERISTICS
TA = 25°C
VO – Output Voltage – V
1.54 2.54
1.52 2.52
1.5 2.5
VO
VO
1.48 2.48
1.46 2.46
1.44 2.44
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
t – Time – µs t – Time – µs
Figure 39 Figure 40
nv//HzHz
RS = 20 Ω RS = 20 Ω
100 TA = 25°C TA = 25°C
V n – Equivalent Input Noise Voltage – nV/
100
80 80
60 60
40 40
20 20
VN
VN
0 0
101 102 103 104 101 102 103 104
f – Frequency – Hz f – Frequency – Hz
Figure 41 Figure 42
TYPICAL CHARACTERISTICS
1500
1000
Noise Voltage – nV
500
–500
–1000
VDD = 5 V
–1500 f = 0.1 Hz to 10 Hz
TA = 25°C
–2000
0 1 2 3 4 5 6 7 8 9 10
t – Time – s
Figure 43
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE
vs vs
FREQUENCY FREQUENCY
THD + N – Total Harmonic Distortion Plus Noise – %
10 10
VDD = 5 V VDD = 3 V
RL = 2 kΩ Tied to 2.5 V TA = 25°C RL = 2 kΩ Tied to 1.5 V TA = 25°C
RL = 2 kΩ Tied to 0 V RL = 2 kΩ Tied to 0 V
AV = 10 AV = 10
AV = 1 AV = 1
1 1
0.1 0.1
AV = 10 AV = 10
AV = 1 AV = 1
0.01 0.01
101 102 103 104 105 101 102 103 104 105
f – Frequency – Hz f – Frequency – Hz
Figure 44 Figure 45
TYPICAL CHARACTERISTICS
TA = 25°C
500
650
400
300 600
200
550
100
0 500
–50 –25 0 25 50 75 100 125 0 1 2 3 4 5 6 7 8
TA – Free-Air Temperature – °C VDD – Supply Voltage – V
Figure 46 Figure 47
Gain Margin – dB
45°
Rnull = 200 Ω Rnull = 100 Ω
10
30°
φom
Rnull = 0
5 Rnull = 0
15°
TA = 25°C
Rnull = 100 Ω RL = 2 kΩ
0° 0
101 102 103 104 105 101 102 103 104 105
CL – Load Capacitance – pF CL – Load Capacitance – pF
Figure 48 Figure 49
TYPICAL CHARACTERISTICS
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
600
TA = 25°C
RL = 2 kΩ
500
300
ÁÁ
200
ÁÁ 100
0
101 102 103 104 105
CL – Load Capacitance – pF
Figure 50
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice . The Boyle macromodel (see Note 5) and subcircuit in Figure 51 are generated using
the TLV243x typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D Maximum positive output voltage swing D Unity-gain frequency
D Maximum negative output voltage swing D Common-mode rejection ratio
D Slew rate D Phase margin
D Quiescent power dissipation D DC output resistance
D Input bias current D AC output resistance
D Open-loop voltage amplification D Short-circuit output current limit
NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
99
DLN
3 EGND +
VCC +
9 92
FB
+ – 90 91
RSS ISS
RO2 + DLP + –
VB
RP HLIM VLP VLN
+ –
2 10 – – +
IN – VC R2
J1 J2 – C2
DP 6 7
IN + 53 +
1 11 VLIM
12 DC GCM GA
–
C1 8
RD1 RD2
60 RO1
+ DE
VAD 5
– 54
VCC –
4 – +
VE OUT
.SUBCKT TLV2432 1 2 3 4 5 RD1 60 11 21.22E3
C1 11 12 3.560E–12 RD2 60 12 21.22E3
C2 6 7 15.00E–12 R01 8 5 120
DC 5 53 DX R02 7 99 120
DE 54 5 DX RP 3 4 26.04E3
DLP 90 91 DX RSS 10 99 24.24E6
DLN 92 90 DX VAD 60 4 –.6
DP 4 3 DX VB 9 0 DC 0
EGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5 VC 3 53 DC .65
FB 7 99 POLY (5) VB VC VE VLP VE 54 4 DC .65
+ VLN 0 21.04E6 –30E6 30E6 30E6 –30E6 VLIM 7 8 DC 0
GA 6 0 11 12 47.12E–6 VLP 91 0 DC 1.4
GCM 0 6 10 99 4.9E–9 VLN 0 92 DC 9.4
ISS 3 10 DC 8.250E–6 .MODEL DX D (IS=800.0E–18)
HLIM 90 0 VLIM 1K .MODEL JX PJF (IS=500.0E–15 BETA=281E–6
J1 11 2 10 JX + VTO= –.065)
J2 12 1 10 JX .ENDS
R2 6 9 100.0E3
www.ti.com 24-May-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TLV2432AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2432AI Samples
TLV2432AIPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2432AI Samples
TLV2432AQD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 V2432A Samples
TLV2432AQDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 V2432A Samples
TLV2432AQDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 V2432A Samples
TLV2432CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 2432C Samples
TLV2432IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2432I Samples
TLV2432QD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 V2432Q Samples
TLV2434AIDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2434AI Samples
TLV2434AIPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2434AI Samples
TLV2434CDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 2434C Samples
TLV2434CPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 2434C Samples
TLV2434IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2434I Samples
TLV2434IPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2434I Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 24-May-2024
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 31-May-2024
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 31-May-2024
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 31-May-2024
TUBE
T - Tube
height L - Tube length
W - Tube
width
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
4214825/C 02/2019
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0008A SCALE 2.800
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
C
6.6 SEATING PLANE
TYP
6.2
A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1
3.1 2X
2.9
NOTE 3 1.95
4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.75 0.15
0 -8 0.05
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8
SYMM
6X (0.65)
5
4
(5.8)
4221848/A 02/2015
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8
SYMM
6X (0.65)
5
4
(5.8)
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024, Texas Instruments Incorporated