EPE2206 Computer Systems and

Microprocessors

 DMA
 UART
 Memory Hierarchy
 Hard Drives/Magnetic Discs

Dr Kwee Hiong Lee

[email protected]
I/O Devices
UART
 I/O device: UART
 (Universal Asynchronous Receiver and Transmitter)
Also called serial port or ACIA (Asynchronous
Comms Interface Adapter).
 This allows connection to byte-oriented external
devices such as a keyboard or modem.
 The bits are sent serially - one after the other. This is
cheap, but slow. UARTs are relatively simple in
hardware terms.
 The CPU transfers data to the UART one byte at a
time, and the UART handles the transmission.
 UART (2)

Shown below is a timing diagram for the transmission

of the character 1110111.
 UART (3)
 Features of the timing diagram:
• The 'idle' state (when nothing is being transmitted)
is 1. If it is 0 on an incoming link, this indicates that
the other side is not powered on, or faulty.
• Bits are transmitted with the LSB first, MSB last.
• The start bit allows the receiver to synchronise to the
incoming bit stream.
• The parity bit is used as a simple error check. It is
chosen so that the total number of 1's is either
even or odd. The example shows even parity. If the
receiving end detects the wrong parity, there
may have been a transmission error (or the sending
UART sends data with the wrong parity).
 UART (4)
 There can be one or two stop bits (two stop bits was
normal with older, much slower links - one stop bit is
common now). They return the line to the idle state.
 If no stop bit is detected, this indicates that the
sending UART transmits at a different speed from the
receiver’s speed. The receiving UART can then try
alternative speeds until a stop bit is found (this trick is
often performed by fax machines).
 Alternatively, the sending UART could be faulty.
 When transmission is finished, there can be an
arbitrary transmission gap. The whole sequence then
repeats itself.
 UART (5)
 Internal organisation of the UART:
 UART (6)
 The mode register is used to set
• character length in bits
• parity enable and parity definition
• number of stop bits
• clock frequencies for send and receive
• interrupt enable
 The status register indicates
• transmit (Tx) buffer empty or full.
• receive (Rx) buffer empty or full.
• parity error has occurred.
• framing error has occurred: no stop bit found.
• overrun error has occurred: previous byte
overwritten (possible software error).
 UART (7)
 Transmission:
• the CPU waits until the transmit buffer becomes empty
• the CPU loads a byte into the transmit buffer
• the control logic adds the start/stop bits and the
parity bit
• the control logic transfers the contents of the transmit
buffer to the transmit register
• the contents of the transmit register are shifted out to
the line in synchronisation with the transmit clock.
 UART (8)
 Reception:
• the control logic detects the leading edge of the
start bit
• the timing logic finds the middle of the start bit,
and checks if it is still there (otherwise assume it
was noise)
• the data bits, parity bit and stop bit(s) are sampled
(in the middle) and shifted into the receive register
• checks are made for the presence of transmission errors
and status flags are set appropriately
• the incoming byte is transferred to the receive
buffer and the status flag is set
• the CPU transfers the byte from the receive buffer
Hard Drives / Magnetic Discs
 Magnetic Discs
 The disc is coated with magnetic material.
Picture:
 Magnetic Discs (2)
 Each sector contains:
- a preamble, to detect the start of the sector
- the track and sector number
- data bits
- error check bits
 Magnetic Discs (3)

Tracks are read from the outside to the inside.

 Magnetic Discs (4)
 The parameters of a disk are sometimes known as its
geometry:
• number of “platters” - metal discs;
• number of surfaces, usually two per platter
• number of different positions for the head assembly,
i.e number of tracks - called cylinders when there is
more than one platter;
• number of sectors per track;
• sector size, usually in bytes.
Total disk capacity = sector size ×
number of sectors per track ×
number of tracks per cylinder ×
number of cylinders
 CD-ROM, DVD
 These have the following characteristics:
• the disc is coated in metal, with areas that reflect light
differently.
• Normal surface is called “land”
• Surface affected by strong laser beam is called “pit”
• land-followed-by-pit represents 0,
pit-followed-by-land represents 1.
These are read by a weak laser beam.
• they are read from the inside to the outside
CD-ROM, DVD (2)
Memory Hierarchy
 Memory Hierarchy

 Users want very fast, very large, and very cheap memory.
These requirements are contradictory, so this is not possible.
The solution is to have various types of memory, differing in
speed, size and cost:
• Register memory.
The smallest, fastest, and most expensive.
• Cache memory.
This is used to hold copies of the most frequently used data.
• Main memory.
The principal storage area for programs and data.
• Secondary memory.
Holds programs and data not currently used.
Usually magnetic discs. Largest, slowest, and cheapest.
 Each can transfer data to/from above and below. Cost and
speed decrease going down the list.
 Cache Memory
 This is intended to bridge the gap between:
• The high speed, but small capacity of registers.
• The high capacity, but slow speed of main memory.
 A cache exploits the principle of locality:
programs have many loops, so they tend to execute
the same small set of instructions repeatedly.
 Principle:
 Cache Memory (2)
 The cache is faster than main memory, but smaller.
It is slower than registers, but larger.
What Access time Capacity
Registers 1 ns 1 Kb
Cache 10 ns 8 Mb
Main memory 100 ns 8 Gb
Hard drive 10000000 ns 4 Tb

 Modern CPUs have two caches:

• One on the same chip as the CPU (L1 cache)
• A secondary one on the motherboard (L2 cache).
 Cache Memory (3)
 Basic idea when reading from memory:
• the CPU fetches an instruction from memory
• the cache checks whether it holds a copy
• if so, it sends it to the CPU
• if not, it fetches it from main memory, sends it to the CPU,
and also keeps its own copy.
 When the CPU writes to memory, the cache copies
the data, and then does the write operation.
 100 fetches on the same instruction will result in
1 slow and 99 fast read operations. The speed-up
factor is almost 10.
 When the cache becomes full, "old" entries can be
overwritten. They are usually randomly chosen.
 DMA
Direct Memory Access
 Direct Memory Access (DMA)
 Suppose the CPU wants to send a large amount of
data to an I/O device. It would have to execute a loop
such as the following:
Repeat
read one word from memory
write the word to the device
Until all-data-transferred

 A DMA controller is a special chip to handle large

data transfers, without the CPU being involved.
 It connects to the bus like any other I/O device.
 It often has its own data channels to memory, so it
does not need to use the bus.
 Direct Memory Access (DMA) (2)

 The controller has the following (usually several):

• a counter
• an address register
 Instead of doing the work itself, the CPU loads the
memory address and the number of bytes into the
DMA controller. The CPU then continues with other
work.
 The controller proceeds to transfer the bytes,
while adjusting the counter and the address after
each byte. At the end of the transfer, the controller
interrupts the CPU to tell it the work has been done.