Analog IC Designer S Handbook 1720706789

Analog IC Designer's Handbook
J-F. DEBROUX
September 23, 2020
Top-Down method at work in analog IC design

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Abstract
Analog IC design is one of the particular design activities where de-
signers get feedback on their choices only months after they nish their
design and where the cost of even the smallest design change is huge.
This has historically brought the need for new tools such as SPICE,
the ancestor of almost all the electric simulators, so as to give feedback
on the design choices before actually getting the prototypes. This should
also have deeply impacted the design methods, and it has, but the avail-
ability of simulators has nally allowed the old try and x method not
only to survive but also to stay very popular.
If tools such as electric simulators have gained popularity in most
electronic design elds, even out of the IC design world, methods such
as the TOP-DOWN approach are not as popular as they should be,
especially in the analog design community, even in the analog IC design
microcosm. This is probably because this method is felt as dicult to use
practically even though most designers agree that it is the right approach.
The goal of this book is to show that the TOP-DOWN approach for
analog design is not only valid but that it is one of the most powerful
available methods to create good analog design without sacricing the
time to market. This method creates faster and better designs but re-
quires a good understanding of the method itself, of course, but also of
the underlying techniques and of the basic design elements.
After a general introduction of the TOP-DOWN method goals and
principles in the rst part, the second part presents and details analog IC
design elements from components to basic building blocks with a strong
emphasis on practical aspects. Various additional design techniques are
then detailed in the third part. The reader is then ready for the main
course, a series of design examples based on the TOP-DOWN method
that are grouped in the fourth part. These examples are processed the
way they are in real life, from specication to implementation, from gen-
eral considerations down to implementation details. Analysis of existing
circuits is useful for learning but real life design is synthesis, not analysis.
Finally, the fth part introduces or reminds useful basic concepts and
presents the notation in use through the book.
The methods and techniques described in this book have been used by
the author through 35 years of analog and mixed signal ICs design expe-
rience in various application elds including RF and sensor signal condi-
tioning for various markets such as industrial, automotive and aerospace.
The author feels that the method he presents in this book can help many
analog electronic designers in their day to day work and hopes it will bring
both a deeper understanding of design and a broader view over design
activities.
Contents
Contents 3
List of Figures 9
I Analog integrated circuit development 14

1 Introduction 15
1.1 TOP-DOWN design methodology example . . . . . . . . . . . . 15
1.2 Product life . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.3 Before going further . . . . . . . . . . . . . . . . . . . . . . . . 21
2 Development 22
2.1 Specication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3 Manufacturing . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4 Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5 Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.6 IC development . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.7 Local loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3 Design 27
3.1 Design activity . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Simple objects design . . . . . . . . . . . . . . . . . . . . . . . 28
3.3 Options and criteria to make a choice . . . . . . . . . . . . . . 28
3.4 Complex object design . . . . . . . . . . . . . . . . . . . . . . . 30
3.5 Architecture and Sizing . . . . . . . . . . . . . . . . . . . . . . 31
3.6 Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.7 Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8 Design levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4 TOP-DOWN Design Flow 35

4.1 Recursive Loops . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2 Controlling recursion . . . . . . . . . . . . . . . . . . . . . . . . 37
5 Feasibility study 39
5.1 Laws of physics . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2 Technologies and tools . . . . . . . . . . . . . . . . . . . . . . . 40
5.3 Skills and resources . . . . . . . . . . . . . . . . . . . . . . . . . 40
3
CONTENTS 4
5.4 Costs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.5 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6 Design Management 44
6.1 Design kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.2 Process options and components list . . . . . . . . . . . . . . . 45
6.3 Multiple access design . . . . . . . . . . . . . . . . . . . . . . . 45
6.4 Revision control . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.5 Naming convention . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.6 Documentation structure . . . . . . . . . . . . . . . . . . . . . 47
6.7 Power supply strategy . . . . . . . . . . . . . . . . . . . . . . . 47
6.8 Return from experience . . . . . . . . . . . . . . . . . . . . . . 48
7 Specication 49
7.1 Specication contents . . . . . . . . . . . . . . . . . . . . . . . 50
7.2 Specication tools . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.3 Specication checklist . . . . . . . . . . . . . . . . . . . . . . . 53
8 Architecture 56
8.1 Architecture catalog . . . . . . . . . . . . . . . . . . . . . . . . 56
8.2 Levels 0 and 1 architecture . . . . . . . . . . . . . . . . . . . . 56
8.3 Level 2 architecture . . . . . . . . . . . . . . . . . . . . . . . . 57
8.6 Choosing an Architecture . . . . . . . . . . . . . . . . . . . . . 57
8.7 Architecture tools . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.8 Architecture validation . . . . . . . . . . . . . . . . . . . . . . . 60
9 Sizing 62
9.1 Sizing methods . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.2 Sizing example: Square root circuit33.2 . . . . . . . . . . . . . 64
9.3 Leaf cell sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.4 Sizing validation . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10 Implementation 68
10.1 Floor plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.3 Manufacturing . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11 Validation 70
11.1 Sizing validation . . . . . . . . . . . . . . . . . . . . . . . . . . 71
11.2 Layout validation . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.3 Silicon validation . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12 Sizing validation 74
12.1 Environment conditions . . . . . . . . . . . . . . . . . . . . . . 74
12.2 Process cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.3 Monte-Carlo analysis . . . . . . . . . . . . . . . . . . . . . . . . 76
13 Layout validation 78
CONTENTS 5
14 Silicon validation 79
15 Troubleshooting 81
15.1 Describe the problem . . . . . . . . . . . . . . . . . . . . . . . . 81
15.2 Identify root cause . . . . . . . . . . . . . . . . . . . . . . . . . 82
15.3 Design debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
15.4 Silicon debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
II Analog IC design 85
16 Introduction 86
16.1 Analog electronics . . . . . . . . . . . . . . . . . . . . . . . . . 86
16.2 Consequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
17 Basic analog IC design elements 88

17.1 Integrated components . . . . . . . . . . . . . . . . . . . . . . . 88
17.2 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
18 Bipolar transistors 90
18.1 Symbols and notation . . . . . . . . . . . . . . . . . . . . . . . 90
18.2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
18.3 Cross sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
18.4 Model equations . . . . . . . . . . . . . . . . . . . . . . . . . . 93
18.5 Simplied model . . . . . . . . . . . . . . . . . . . . . . . . . . 103
18.6 Small signal model . . . . . . . . . . . . . . . . . . . . . . . . . 103
18.7 Eects of bias current . . . . . . . . . . . . . . . . . . . . . . . 106
18.8 Eects of geometry . . . . . . . . . . . . . . . . . . . . . . . . . 106
18.9 Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
18.10Basic transistor congurations . . . . . . . . . . . . . . . . . . . 107
18.11Design kit validation . . . . . . . . . . . . . . . . . . . . . . . . 108
19 MOS transistors 110

19.1 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
19.2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
19.3 Cross sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
19.4 Model equations . . . . . . . . . . . . . . . . . . . . . . . . . . 112
19.5 Small signal model . . . . . . . . . . . . . . . . . . . . . . . . . 115
19.6 Weak inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
19.7 Eects of geometry . . . . . . . . . . . . . . . . . . . . . . . . . 117
19.8 Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
19.9 Basic congurations . . . . . . . . . . . . . . . . . . . . . . . . 118
19.10Extracting level 1 parameters . . . . . . . . . . . . . . . . . . . 119
20 Common characteristics of bipolar and MOS transistors 124
21 Resistors 126
21.1 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
21.2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
21.3 Cross section . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
CONTENTS 6
21.4 Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

21.5 Body and head resistances . . . . . . . . . . . . . . . . . . . . . 128
21.6 Parasitic capacitance . . . . . . . . . . . . . . . . . . . . . . . . 131
21.7 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
21.8 Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
21.9 Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . 132
21.10Misalignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
21.11Gradients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
21.12Dummies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
21.13Special resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
22 Capacitors 143
22.1 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
22.2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
22.3 Cross sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
22.4 Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
22.5 Area capacitance and peripheral capacitance . . . . . . . . . . 145
22.6 Parasitic capacitance . . . . . . . . . . . . . . . . . . . . . . . . 148
22.7 Parasitic resistance . . . . . . . . . . . . . . . . . . . . . . . . . 149
22.8 Breakdown voltage . . . . . . . . . . . . . . . . . . . . . . . . . 149
22.9 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
22.10Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
22.11Gradients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
22.12Dummies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
22.13Improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
23 Inductors 152
23.1 Spiral inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
23.2 Multilayer solenoid . . . . . . . . . . . . . . . . . . . . . . . . . 152
24 ESD devices 153

24.1 The Human Body Model . . . . . . . . . . . . . . . . . . . . . . 154
24.2 The Machine Model . . . . . . . . . . . . . . . . . . . . . . . . 155
24.3 The Charged Device Model . . . . . . . . . . . . . . . . . . . . 155
24.4 ESD protection general strategy . . . . . . . . . . . . . . . . . 155
24.5 ESD protection devices . . . . . . . . . . . . . . . . . . . . . . 156
25 Parasitic components 157

25.1 Isolation diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
25.2 Parasitic resistors . . . . . . . . . . . . . . . . . . . . . . . . . . 157
25.3 Parasitic capacitors . . . . . . . . . . . . . . . . . . . . . . . . . 159
25.4 Parasitic MOS . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
25.5 Parasitic bipolar . . . . . . . . . . . . . . . . . . . . . . . . . . 161
25.6 Parasitic thyristor . . . . . . . . . . . . . . . . . . . . . . . . . 161
26 Substrate related issues 162

26.1 Reducing generation . . . . . . . . . . . . . . . . . . . . . . . . 163
26.2 Optimizing attenuation . . . . . . . . . . . . . . . . . . . . . . 163
CONTENTS 7
26.3 Reducing sensitivity . . . . . . . . . . . . . . . . . . . . . . . . 164

26.4 Thermal coupling . . . . . . . . . . . . . . . . . . . . . . . . . . 164
27 Package considerations 165

27.1 Package equivalent schematic . . . . . . . . . . . . . . . . . . . 165
27.2 Package thermal characteristics . . . . . . . . . . . . . . . . . . 166
28 PCB considerations 167

28.1 Mechanical function . . . . . . . . . . . . . . . . . . . . . . . . 167
28.2 Thermal function . . . . . . . . . . . . . . . . . . . . . . . . . . 167
28.3 Electrical function . . . . . . . . . . . . . . . . . . . . . . . . . 168
29 Test considerations 169

29.1 Test philosophy . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
29.2 Test sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
29.3 Test architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 170
30 Reliability 171
30.1 Oxide stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
30.2 Interconnections stress . . . . . . . . . . . . . . . . . . . . . . . 171
30.3 Hot carriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
31 Basic integrated building blocks 172

31.1 Current mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
31.2 Dierential pair . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
31.3 Voltage follower . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
32 Tentative analog functions classication 178

32.1 Signal generators . . . . . . . . . . . . . . . . . . . . . . . . . . 178
32.2 Signal modiers . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
IIIDesign Examples 181

33 Square root circuit 182
33.1 Square root circuit architecture . . . . . . . . . . . . . . . . . . 182
33.2 Square root circuit sizing . . . . . . . . . . . . . . . . . . . . . 183
34 MOS Voltage follower 185
35 Constant gm cell 187

35.1 Problem to solve . . . . . . . . . . . . . . . . . . . . . . . . . . 187
35.2 Problem formalization . . . . . . . . . . . . . . . . . . . . . . . 187
35.3 Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
36 Band-gap reference voltage generator 188

36.1 Some band-gap architectures . . . . . . . . . . . . . . . . . . . 188
37 Linear Voltage regulator 190

37.1 Eciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
37.2 Operating quadrants . . . . . . . . . . . . . . . . . . . . . . . . 190
CONTENTS 8
37.3 Short circuit protection . . . . . . . . . . . . . . . . . . . . . . 191
38 Sigma-Delta Modulator 192

38.1 An intuitive approach . . . . . . . . . . . . . . . . . . . . . . . 192
38.2 Delta modulators . . . . . . . . . . . . . . . . . . . . . . . . . . 193
38.3 First order modulator . . . . . . . . . . . . . . . . . . . . . . . 194
38.4 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
38.5 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
38.6 Second order modulator . . . . . . . . . . . . . . . . . . . . . . 204
38.7 Third order modulator . . . . . . . . . . . . . . . . . . . . . . . 204
38.8 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
38.9 Small signal analysis . . . . . . . . . . . . . . . . . . . . . . . . 208
IVTechniques 229
39 Analyzing operating point DC stability 231
39.1 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
39.2 Generalizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
39.3 Example: PTAT current source . . . . . . . . . . . . . . . . . . 236
40 The dependency graph method 238
41 The gmin stepping method 240

41.1 Suggested method . . . . . . . . . . . . . . . . . . . . . . . . . 240
42 The noise peaking method 242
43 Robust design techniques 243

43.1 General principle . . . . . . . . . . . . . . . . . . . . . . . . . . 243
43.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
43.3 Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . 244
43.4 Unexpected consequences of the robust by design approach. . . 246
44 Safe design techniques 248
45 Surface optimization: R-C cell 249

45.1 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
V Basic concepts 252

46 Glossary 253
46.1 Conductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
46.2 Operating point . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
46.3 Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
46.4 Trans-conductance . . . . . . . . . . . . . . . . . . . . . . . . . 257
46.5 Trans-resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
47 Maths for electronic designers 258

47.1 Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
48 Physics for electronic designers 263
48.1 Carriers in dierent media . . . . . . . . . . . . . . . . . . . . . 263
48.2 Combination of equilibrium states . . . . . . . . . . . . . . . . 264
48.3 Kirchho laws . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
48.4 Norton-Thévenin equivalent circuits . . . . . . . . . . . . . . . 265
48.5 Ohm's law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
48.6 P-N junction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
48.7 Propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
48.8 Heat transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
48.9 Resistance between two cylinders . . . . . . . . . . . . . . . . . 267
48.10Resistance between two spheres . . . . . . . . . . . . . . . . . . 267
49 Electronics for electronic designers 269

49.1 Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
49.2 Impedance matching circuits . . . . . . . . . . . . . . . . . . . 270
49.3 Simple passive circuits . . . . . . . . . . . . . . . . . . . . . . . 270
49.4 Miller eect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
49.5 Cascode amplier . . . . . . . . . . . . . . . . . . . . . . . . . . 273
49.6 Equivalent cuto frequency of two rst order low-pass lter . . 274
50 Materials properties 275

50.1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
50.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
50.3 Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 278
51 Tools 279
51.1 Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
51.2 CAS (Computer Algebra System) . . . . . . . . . . . . . . . . . 279
51.3 Behavioral simulators . . . . . . . . . . . . . . . . . . . . . . . 279
51.4 Electrical simulators . . . . . . . . . . . . . . . . . . . . . . . . 279
52 Index 280
Index 281
List of Figures
1.1 Product Life . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1 Development Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1 Hierarchical Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
18.1 Bipolar transistors symbols . . . . . . . . . . . . . . . . . . . . . . 90
9
LIST OF FIGURES 10
18.2 Vertical NPN Cross-section . . . . . . . . . . . . . . . . . . . . . . 91

18.3 Lateral PNP Cross-section . . . . . . . . . . . . . . . . . . . . . . . 92
18.4 Substrate PNP Cross-section . . . . . . . . . . . . . . . . . . . . . 92
18.5 Vertical PNP (isolated) Cross-section . . . . . . . . . . . . . . . . . 92
18.6 IC vs. VCE (VBE) Basic . . . . . . . . . . . . . . . . . . . . . . . 94
18.7 IC/IB vs. VCE Basic . . . . . . . . . . . . . . . . . . . . . . . . . 95
18.8 IC/IB vs. IC Basic . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
18.9 IC vs. VCE (VBE) Early . . . . . . . . . . . . . . . . . . . . . . . 96
18.10IC/IB vs VCE Early . . . . . . . . . . . . . . . . . . . . . . . . . . 97
18.11IC/IB vs. IC Early . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
18.12CBE terms vs. VBE . . . . . . . . . . . . . . . . . . . . . . . . . . 100
18.13CBE terms vs. IC . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
18.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
18.15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
18.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
18.17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
18.18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
19.1 NMOS and PMOS symbols . . . . . . . . . . . . . . . . . . . . . . 110

19.2 NMOS on P Substrate . . . . . . . . . . . . . . . . . . . . . . . . . 111
19.3 PMOS on P Substrate . . . . . . . . . . . . . . . . . . . . . . . . . 111
19.4 Isolated NMOS on P Substrate . . . . . . . . . . . . . . . . . . . . 112
19.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
19.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
19.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
19.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
19.9 Extracting KP and VT . . . . . . . . . . . . . . . . . . . . . . . . 121
19.10ID vs. VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
19.11Comparing Level 1 to actual model (lin scale) . . . . . . . . . . . . 122
19.12Comparing Level 1 to actual model (log scale) . . . . . . . . . . . 122
20.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
21.1 Resistor symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

21.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
21.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
21.4 Bulk resistor Cross-section . . . . . . . . . . . . . . . . . . . . . . . 127
21.5 Poly resistor Cross-section . . . . . . . . . . . . . . . . . . . . . . . 127
21.6 Resistance vs. Length . . . . . . . . . . . . . . . . . . . . . . . . . 129
21.7 Geometrical eect . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
21.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
21.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
21.10Thermal resistance 1% . . . . . . . . . . . . . . . . . . . . . . . . . 133
21.11Thermal resistance 10% . . . . . . . . . . . . . . . . . . . . . . . . 134
21.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
21.13Rectangular resistor misalignment . . . . . . . . . . . . . . . . . . 137
21.14U shaped resistor misalignment . . . . . . . . . . . . . . . . . . . . 138
21.15Rectangular resistor angular misalignment . . . . . . . . . . . . . . 139
21.16Eect of gradient on 2 resistors . . . . . . . . . . . . . . . . . . . . 140
21.17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
LIST OF FIGURES 11
21.18Eect of gradient on 4 resistors . . . . . . . . . . . . . . . . . . . . 141

21.19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
22.1 Capacitor symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

22.2 MOS Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
22.3 POLY/N+ Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . 144
22.4 POLY-POLY Capacitor . . . . . . . . . . . . . . . . . . . . . . . . 144
22.5 MIM Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
22.6 MOM Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
22.7 FR4 capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
22.8 Fringe capacitance location . . . . . . . . . . . . . . . . . . . . . . 147
22.9 Vertical eld parasitic capacitor . . . . . . . . . . . . . . . . . . . . 149
24.1 HBM test bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

24.2 HBM test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 154
24.3 MM test bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
24.4 MM test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 155
24.5 CDM test bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
24.6 CDM test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 155
25.1 IR Drop Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . 158

25.2 IR Drop Dierential Pair . . . . . . . . . . . . . . . . . . . . . . . 158
25.3 IR Drop Mirror Strip . . . . . . . . . . . . . . . . . . . . . . . . . . 158
25.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
25.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
25.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
25.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
25.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
25.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
26.1 Substrate attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . 163
31.1 Diode connected transistors . . . . . . . . . . . . . . . . . . . . . . 173

31.2 Bipolar current mirror . . . . . . . . . . . . . . . . . . . . . . . . . 173
31.3 Bipolar Current Mirror small signal model . . . . . . . . . . . . . 174
31.4 MOS Current mirror . . . . . . . . . . . . . . . . . . . . . . . . . . 174
31.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
31.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
31.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
31.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
31.9 Dierential pair schematic . . . . . . . . . . . . . . . . . . . . . . . 177
31.10Dierential pair small signal schematic . . . . . . . . . . . . . . . . 177
31.11Voltage follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
33.1 Square Root circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
34.1 MOS Follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

34.2 Follower Small signal model . . . . . . . . . . . . . . . . . . . . . . 186
37.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
LIST OF FIGURES 12
38.1 Delta modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

38.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
38.3 Sigma-Delta modulator . . . . . . . . . . . . . . . . . . . . . . . . 193
38.4 First order Sigma-Delta modulator . . . . . . . . . . . . . . . . . . 194
38.5 Integrator subcircuit . . . . . . . . . . . . . . . . . . . . . . . . . . 197
38.6 Integrator instance with specied time constant . . . . . . . . . . . 197
38.7 Voltage comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 198
38.8 Embedded D ip-op . . . . . . . . . . . . . . . . . . . . . . . . . 198
38.9 One bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
38.10Single bit First Order Sigma-Delta modulator oscillation . . . . . . 199
38.11Single bit First Order Sigma-Delta modulator oscillation Feedback 200
38.12Single bit First Order Sigma-Delta modulator operation . . . . . . 200
38.13Single bit First Order Sigma-Delta modulator input and ltered
feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
38.14Single bit First Order Sigma-Delta modulator ltered input and
feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
38.15Integrator output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
38.16Integrator output spectrum . . . . . . . . . . . . . . . . . . . . . . 202
38.17Bit stream spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . 203
38.18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
38.19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
39.1 Two inverters loop . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

39.2 Two inverters loop Operating Point . . . . . . . . . . . . . . . . . . 232
39.3 Two inverters Open Loop . . . . . . . . . . . . . . . . . . . . . . . 233
39.4 One Inverter Transfer Characteristics . . . . . . . . . . . . . . . . . 234
39.5 Two Inverters Transfer Characteristics . . . . . . . . . . . . . . . . 234
39.6 Two Inverters Loop Operating Points . . . . . . . . . . . . . . . . 235
39.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
39.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
43.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
45.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
46.1 Generator-Load Operating Point . . . . . . . . . . . . . . . . . . . 254

46.2 Static and Dynamic Impedance . . . . . . . . . . . . . . . . . . . . 256
47.1 Two dice probability chart . . . . . . . . . . . . . . . . . . . . . . . 260

47.2 One to Three dice probability chart . . . . . . . . . . . . . . . . . 261
47.3 Four dice vs. Gaussian . . . . . . . . . . . . . . . . . . . . . . . . . 262
48.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
48.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
49.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
49.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
49.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
49.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
49.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
49.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
LIST OF FIGURES 13
49.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
49.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
49.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
49.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
49.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
49.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Part I
Analog integrated circuit

development
14
Chapter 1
Introduction
This handbook is intended to help and assist analog IC designers in their day
to day design work. This handbook describes the general TOP-DOWN design
methodology and some related techniques that can be used during most design
phases. It looks at the design activity as a whole and tries to gure out some
general principles and to give an overview on the design process.
The document is structured logically and normally denes words and con-
cepts before using them. However, basic knowledge of electronics is required
for using this handbook eciently in day to day design. The general method
developed in this handbook is not intended to change the way you work, it is
intended to help you and to speed up your experience.
If you know and practice methods that have proved to be ecient, go on

using them.
If you are interested in looking at methods that might be dierent from

yours, feel free to read some sections in this handbook.
If you think that some of your methods should be improved, you can refer
to the relevant sections in this handbook.
If you have no method for addressing some of your design challenges, try
to use the ones described in this handbook.
If you would like to contribute to this handbook, all suggestions are wel-
come. They will be analyzed in detail and taken into account.
A few more words about using this handbook: It can, of course, be read from
start to end, but this may seem a bit theoretical in a rst place, especially for
freshers. It can also be read from the table of contents entries and navigated
back and forth according to the needs.
1.1 TOP-DOWN design methodology example

Let's start with a very simple example from day to day life: Building a new
house. What can be the process to perform this task?
Basically there are two opposite methods:
15
CHAPTER 1. INTRODUCTION 16
You can start the process by putting the rst brick on the ground and
follow your inspiration.
You can dene rst the size of the house, the number of oors how the
dierent rooms will be located inside.
What the TOP-DOWN method suggests is that the second method is a better
approach. Of course, in real life, one often has to mix these two extreme
methods. However, this mix always benets from putting emphasis on dening
before doing.
Common arguments against the TOP-DOWN method are that it is less

creative or that it takes time to dene what has to be done or that people know
what they have to do and don't need to write specications before designing.
In this book we will show that:
TOP-DOWN design can be even more creative than BOTTOM-UP de-

sign.
The time it takes to write a specication is really worth it.
We can state that most experienced people practicing BOTTOM-UP design in

fact use an implicit TOP-DOWN approach. Finally, another common situation
is when people do not know what they want. The BOTTOM-UP method allows
to start and see what gets out. But is that the best path to a successful product?
1.1.1 Why dening before doing?

In our simple example, the number of oors, for instance, denes the
pressure the building will apply on the ground. For the house to last
long, the basement nature and size should be adapted to that pressure.
Starting with the number of oors undened can result in a house

that collapses after some time or even before it is achieved. This
may kill persons and cost lots of time and money. The time it
would have taken to write the specication before starting building
is really worth it.
Another approach could be to oversize the basement so that it can support

many oors and then decide to stop, for instance, after two oors. This
would result in extra delays and costs that could have been avoided by
dening the goal before starting.
Again, specifying rst is worth the money.
Yes, writing a specication before starting a new project can be seen as time
consuming. But in fact it saves time and money on the whole project.
It does take time to write a specication.
But knowing what to do saves much more time than it takes to write the
specication.
And specifying does not disable creativity nor inspiration...
The confusion is that most of the time, the designer knows more or less
what he has to do. The specication is often implicit and inaccurate.
What the TOP-DOWN method suggests is that clarifying the specica-
tion is important and that expressing implied things is important. This
is of particular importance in the common situation where several design-
ers have to work together on the same projects. Another very common
situation is that it is dicult to specify everything from the beginning.
The TOP-DOWN method does not require that every detail is dened
before starting, it recommends that things should be dened before be-
ing done. So the specication can be loose at the beginning and can be
rened along the design process. There is a big margin between dening
nothing and dening everything. This margin is a space for step by step
implementing the TOP-DOWN design method. And anyway, it does not
much take time to dene what you know!
1.1.1.1 What about the details?
For instance, what about the location of the dierent rooms in the house? Or
the dining room walls color?
These are, of course an issue to address, but clearly after the number of
oors is dened.
It would be useless to think of a single oor rooms organization if nally

a two oors house is built. In this case, some work should be done again
causing waste of time and money.
For the colors, they do not really interact with previous steps and can be
dened later in the process.
This shows that, obviously, the sequential aspect is important. Some questions
have to be addressed rst, other questions depend on the answers to the rst
ones. Some topics are important, others are details.
If all the topics have to be addressed, they do not have to be addressed all
at the same time.
1.1.2 Conclusion
This very simple example is aimed at showing two things that are very common
in projects:
Most uncontrolled delays and costs result from rework.

Rework often results from lack of specication or lack of method.
The TOP-DOWN design methodology consists globally in:
Going step by step from the project as a whole to the project details.
Dening things before doing.
Organizing the work ow and sharing the work load.

The goal of TOP-DOWN is to minimize rework. The expected result is FASTER

AND BETTER designs.
Of course, TOP-DOWN design is possible only for designers who know
about the design techniques, the laws of their art, the behavior and properties
of basic building blocks and some of the classic solutions in their eld. This is
basically why dedicated sections in this book deals with components, building
blocks and basic electronics laws.
1.2 Product life

Before considering the details of the TOP-DOWN method, a good start point
is looking at the overall product life, taking a big picture. After all, the best
approach for introducing the TOP-DOWN method is the TOP-DOWN method
itself !
To some extend, what is shown here for integrated circuits can apply to
many other products. Looking at the entire product life gives a good overview
and shows what happens before and after the design phase this book focuses
on. And knowing the context, the origin and the goal really helps the designer
in his day to day work as it gives some of the always missing data that are
required to make the best choice between the design options.
Figure 1.1: Product Life
Definition
Development
Time
Production
End of life
The product life can be gured as linear over time and it divides in four
major phases:
First, the product life begin with the Denition phase, which aims at
dening the future product characteristics.
Then, the Development phase takes place. It aims at designing the prod-
uct and setting up the manufacturing tools. The design phase in which
the designer's work mainly takes place is part of the product development
phase.
The Production phase, the true goal of the whole story, the only phase
that makes money follows Development.
End of life is not a phase at properly speaking, but whatever the reason,
production has to stop sometimes and this reality has to be managed
from beginning.
It is basically because only production makes money that denition and devel-
opment have to be made as short as possible. This reduces expenses and speeds
up return on invest.
The other good reasons for speeding up Development are competition and
limited product life time on the market. The shorter the denition and devel-
opment phases, the sooner the product gets on the market and the more likely
it can be ahead of competitors, but also the longer the product can stay on the
market before it is outdated or replaced by another product. This can make
the dierence between a successful project and a disaster.
1.2.1 Denition
As briey said in the introduction, it is always a good practice to dene the
goal before doing anything. For most products, denition consists mainly in
dening two things:
Dening the product functions.
Dening the product performances.
A product denition is usually a list of functions it must achieve together with

numbers specifying all the required performances. It is often a good practice to
dene also the undesired behaviors and their characteristics so as this gives a
better picture of the product. The denition phase goal is translating a product
idea into a formal product description. The denition phase ends when the
product requirement specication is available. A common situation is that not
all the functions and performance can be specied at the very beginning of a
project but a good practice is to open questions even though answers can be
TBD (To Be Dened) for a while. TOP-DOWN consists in specifying before
doing, but it does not say that everything must be dened during the very rst
minute...
1.2.2 Development
Development will not be detailed here. In the next chapter, we will zoom on the
development phase that includes design, our primary focus with this book. The
development phase goal is translating a product description formalized in the
requirement specication into an actual working product. The Development
really starts when the product requirement specication is available and ends
when the product is ready for volume production.
1.2.3 Production
Production is usually manufacturing and distributing the product in volume.
The three main constraints during the production phase are:
Production capacity must be able to face the market demand.

Production cost with respect to sales price must ensure revenue.
Production quality and consistency must satisfy customers.
One element of the IC market to consider is the price pressure that leads
to reduce the sales price along time. Maintaining revenue in a context of
price reduction is a hard challenge that must be addressed every day. Initial
Return On Investment calculations must take into account the price pressure
that can be as high as 5 to 15 % price reduction per year. Designing a good
product that can be manufacture in volume with good yield is important in
such a context. The good news is that it is one of the TOP-DOWN method
goals. The production phase goal is making money selling the product. The
production phase starts after a pre-production phase has demonstrated the
product manufacturability in good conditions and stops when the product is no
more economically interesting, either because the market prices have dropped
or because volumes have dropped.
1.2.4 End of life

Most products are kept in production as long as possible since it is a good
way to pay for the initial development costs. This is possible as long as the
sales price is higher than the production cost to ensure a reasonable margin.
This implies in many cases that the production volumes are large enough. For
various reasons, volumes may drop after some time:
A new product has grabbed the market
The product primary use has disappeared or narrowed
In this case, the product is often no longer interesting and production has to
stop. Depending on the market or the application, some products cannot be
stopped without notice:
Customers may need parts for the time it takes to setup another solution.
Parts can be required for maintenance.
For these reasons, production stop has to be planned, customers have to be

noticed to dene their needs. This requires some delay that are often dened
in the contracts. Of course, this completely depends on the addressed mar-
ket. Military products have very long life cycles. Customer products are often
stopped without notice and without spare parts for maintenance. Another as-
pect is that the product life time may dier from its manufacturing technology
life time. In such a situation that can occur for several reasons, the product
has to be redesigned. The reasons for such a situation can be:
The product still has a market but the volumes are not sucient to
maintain the technology alive for only that product.
The volumes for maintenance have been under-evaluated.
Whatever the reason, in situations where a product has to be redesigned, the

TOP-DOWN method is really helpful or, more precisely, can be helpful if it
has been used for the initial design...
Specication is available and can be used to restart the design process.
Design documentation is available and helps the designers.
Good designs are robust enough to be transferred to another technology

without too much eort.
1.3 Before going further

This introduction aims at dening the context around the design activity that
will be detailed all along the book. It is important to understand the reasons for
developing a method or a technique in order to use them properly and benet
from them. In this introduction, we have seen that there are many reasons for
the TOP-DOWN design method to be used, for speeding up the development
process and for creating better products. Before going further, it might be
good to list the reasons in order to make sure they have been understood and
will be remembered.
Chapter 2
Development
Again, as a start point, we will look at the development phase as a whole and
see how it is organized.
Figure 2.1: Development Loop
Specification
Design
Time
Manufacturing
Validation
OK?
Globally, the development phase looks like a complex loop with multiple
return path branches.
Everything starts with a Specication phase: Dening what is to be

developed, the future product characteristics. As already stated in the
introduction, dening before doing is really worth the eort even if it
may appears painful and time consuming.
Then the Design phase takes place. To state it simply, design is translat-
ing the specication into data and instructions for manufacturing. Practi-
cally design is recursively dividing the blocks in sub-blocks and organizing
the sub-blocks with respect to each other.
Once the design is completed, the product can be manufactured. Manu-

facturing can be summarized as using data and instructions to produce
the tooling that is required to manufacture the product.
22
CHAPTER 2. DEVELOPMENT 23
When the rst product samples are available, a validation phase must
take place. Validation is checking that the object complies with what was
expected and that manufacturing will be possible in good conditions.
If validation succeeds, the development is over and it's time for

production.
If validation fails, some rework is required, either changing the spec-

ication or the design or sometimes both and the loop is iterated
until the validation succeeds.
It is basically by reducing the number of times the loop is walked through that
the development time can be made shorter.
As already stated, it is one of the goals of the TOP-DOWN design method
to secure the development steps so as to minimize the number of iterations,
speeding up the development process and creating better products.
2.1 Specication
Specication in the development phase is somewhat equivalent to denition
in the product life. The goal is to dene what has to be done. The dier-
ence between denition and specication lies in the standpoint. Denition,
sometimes called Requirement Specication denes what is required from
the application, from the user's standpoint. Specication, sometimes called
Design Specication denes the product from the implementation, from the
designer's standpoint. Creating the Design Specication from the Requirement
specication is the very rst actual design step. Just like the requirement speci-
cation, the design specication is a list of product functions and performances.
Examples will be given later on for design specications.
2.2 Design
As this book's title states, design is out primary goal. Design will be detailed
along the next chapters, so it will not be here.
2.3 Manufacturing
Manufacturing in the development phase is one part of production in the prod-
uct life. During the development phase, manufacturing is normally limited to
prototypes or at least low volumes and may not use exactly the volume pro-
duction equipment or the same tooling even though sometimes it does. In any
case, the required tooling must be developed.
2.4 Validation
Validation consists in checking that the product complies with its denition,
but also in checking that the production equipment can manufacture it in
good conditions for both functions, performances and cost. The product must
be checked extensively, on a signicant number of parts and reliability must
be evaluated. Denition correctness with respect to customer need must be

checked as well. Some products are just ne, they comply to their specs, but
the users don't like them...
The validation phase has to validate everything, from the product deni-
tion with respect to the actual customer needs to the product functions and
performances, to the product matching with the production equipment and
with the economic aspects.
2.5 Loop
In case validation fails, the loop has to be iterated until validation succeeds.
Depending on what fails, design has to be changed accordingly. In some cases,
specication has to be changed if design cannot meet initial requirements in a
reasonable time frame and an acceptable budget.
2.6 IC development
Starting from here, we will focus more and more on one particular product:
The analog integrated circuit. IC development diers from other electronic
products development mainly for the design and manufacturing phases. More
precisely, it is because manufacturing is very specic that design has to take
into account this specicity.
IC Manufacturing requires expensive tooling such as masks and wafer

probing interface.
IC Manufacturing process is highly collective: Thousands of products are

manufactured at a time. This is good for reducing production costs but
prevents the possibility of manufacturing just some prototypes. So the
cost of prototypes is signicant even though plenty of them are manufac-
tured for that cost.
The product is a single piece of silicon containing thousands to millions

of components that cannot be changed individually for validating the
design.
These characteristics impact the design since the try and x method is not
really possible or is very expensive and time consuming. On the other hand,
IC design is not limited by available components or building blocks as these
can be designed on request. IC design is not really limited by complexity. IC
development is one of the few domains of human activity where it would be
possible to manufacture something more complex than what can be designed!
2.6.1 IC design
At the dierence of board design, IC design is not limited by available build-
ing blocks as these are created as required. From experience, this is a huge
dierence and it can be felt when a board designer or an electronic subsystem
designer is involved in specifying an ASIC. Usually board and subsystem de-
signer have real diculties in dening their needs as they are used to choose
available ICs and try to build their application with that. Usually, they can
explain what they did, which components they used, but they have hard times
explaining what the target was and what the design process was.
When it comes to specify an IC, the rst questions are really:
What functions and performances do I need for the IC for the global ap-
plication to work ne? Answering these questions in detail will dene the
Requirement Specication that describes the circuit from the application re-
quirement standpoint.
And then, from functions and performance as described in the requirement

specication, the designer can start the design process by wondering:
How can I build that? What blocks do I need? With what performances?
How should I organize these blocks to get the job done? The answers to
these questions are the basement of the future design. Altogether, they dene
the Design Specication that describes the circuit from the implementation
standpoint.
After the design is completed, a Data-sheet is issued. This document

describes the circuit from the user standpoint with the goal of helping him to
develop the application.
2.6.2 IC manufacturing
A signicant dierence between board and IC manufacturing lies in tooling
costs prototype costs and manufacturing lead time. Depending on the process,
mask costs lie in the 50k to 1M+ dollars range and increases at every node.
This is the major reason why design method have been improved to minimize
the number or iterations to reach a product that meets its specications. This
is also the reason of an exponential increase in the verication costs resulting
from tools and from manpower. As long as it can save an iteration, it is worth
verifying.
2.6.3 IC validation
As the prototypes get out of the fabrication process, they have to be validated.
This process has in fact two complementary purposes:
Checking that the circuit meets all its specications in all operating con-
ditions and on a statistically signicant number of parts from a number
of lots
Checking that each cell in the circuit operates according to the designers
target in all the operating conditions
These two aspects aim at validating the product. It is somewhat like looking
at an object from two dierent viewpoints. These two tasks should ideally be
performed by dierent persons:
Checking the circuit versus its specication should ideally be done by

persons that were not involved in the design process: The validators.
Checking cells versus expectations should ideally be done by the designers

who designed the cells.
The reason is that nding a circuit does not meet its specication is not natural
for designers. They are more prone to be tolerant with their baby. Someone
external can verify a circuit behavior without any interference. It is somewhat
similar to the reason why doctors or policemen should not be involved in cases
related to their family or friends. And even from a brain structure standpoint,
the qualities required for checking are not exactly the same that the qualities
required for creating.
But designers know exactly how their cells are supposed to work not with
respect to the specication but with respect to architecture and sizing. This
is why they should be involved in cell level validation. This is a good way
of checking simulation models accuracy and improving design skills. In such
tasks, designers may point out behaviors that are not covered by specication
and dierences with simulations that would be below the radar of validators.
2.7 Local loops

The development loop forward path can last a signicant time. Typically a
year or so. During all that time, the development loop is open, there is no
feedback. Does that mean that the development is out of control? That
would be unacceptable as too risky and too expensive. But in fact it is not the
case. Each of the big steps has its own internal control loop:
During the specication step, data are periodically exchanged between

the designer and the requester.
The design phase as a whole is a loop and even a recursive loop as we

will see later on.
Manufacturing normally includes process control at every step.
A general rule is that every step that can generate errors must be controlled.
Realistically, every step can generate errors, so every step has to be controlled!
In the next chapter, we will nally focus on design, the primary goal of this
book, as the title suggests.
To summarize The overall development loop should ideally be walked through

only once. But if something goes wrong in the process some rework is required.
If this happens, it means that the Top-Down method has not been applied
properly.
Chapter 3
Design
This handbook targets designers so it is mainly focused on design. In this

section, design is described from a very general standpoint. What is said here
can apply with modulation to any kind of design, it is not restricted to analog
IC design. Later on, we will focus on electronics and more precisely integrated
electronics into a more detailed approach.
3.1 Design activity

What is design? The word itself has a number of possible meanings:
Intention
Drawing
Plan
Arrangement of parts
In this book, by the word design, we mean some sort of a combination of all
these meanings. In addition, we can state that design activity also should also
includes the required elements for manufacturing the product eciently:
Not only must the designer organize the product components together to
meet the requirement, but also has he to think about and implement the
various technical elements that will allow manufacturing and testing the
product.
3.1.1 Designer's work

What does a designer do all the day long at work?
A designer's work consists in only two things:
Making choices.
Implementing and validating these choices.
27
CHAPTER 3. DESIGN 28
But these two simple things keep designers busy all day (and sometimes
night!) long.
What does a designer choose and why?

At this point, we have to make a dierence between designing a simple
object and designing a composite object created by combining simple objects.
3.2 Simple objects design

When designing a simple object, the designer has to choose only three param-
eters:
Material. The material the object will be made from.
Shape. The global object shape.
Size. The object physical dimensions.
The characteristics of a simple object depend only on these three parameters:
The material has intrinsic properties such as hardness, resistivity, or

solder-ability. The object obviously inherits the properties of the ma-
terial it is made from. Material is the most intrinsic characteristics of
a simple object. A stainless steel object is stainless because of the in-
trinsic property of the stainless steel. Manufacturing process can modify
material properties.
The shape also exhibits properties. A circle has the largest possible area
for a given perimeter for instance. The object also inherits the shape
properties. The shape can modify some of the object properties with
respect to the material properties but it cannot change everything. Shape
is an extrinsic property. Whatever its shape, an ordinary steel object will
not be stainless.
Given material and shape, the size impacts the object properties. A large
cup contains more liquid than a small cup. A large screw is stronger than
a small one. Size is not a property in itself if modies the intrinsic and
extrinsic properties. It is a numeric property.
To summarize, material is an intrinsic parameter, the inner one, shape is an

extrinsic parameter, the intermediate one, and size is a numeric parameter, the
outer one.
3.3 Options and criteria to make a choice

Of course, when it comes to make a choice, at least two things are required:
A list of options to choose from.
A set of criteria to compare options and make a choice.

3.3.1 List of options

It is important to have at least two items to make a choice. That may seem
obvious but there are so many implied choices where the designer chooses the
rst idea that comes to his mind that this has to be said again and again. Very
often, having to nd two options to choose from suggests the designer other,
more relevant options. After a training period, this can become a real way of
thinking and makes design an even more enjoyable activity.
3.3.2 Criteria
Choosing between options requires that a comparison is possible. Comparison
requires at least one criterion. When several criteria are considered, comparison
is usually based on a weighted average. Among usual criteria are:
Technical criteria like performance or reliability
Economic criteria like development cost or production cost.
Cultural criteria like aesthetics or environmental impact.
3.3.3 Example
Imagine we have to design an object intended to cut food (this object is know
as a knife in real life...)
Material should be hard enough to cut almost everything and ensure long
service. Steel for instance is harder than wood.
Shape should be such that it minimizes cutting eort. A V shaped

prole with an acute angle will be more ecient than a square prole.
But the shape should also be such that it does not cut the user's ngers
! So, the actual object should have two dierent sections with dierent
shapes. Finally, it appears not to be a simple object!
Size should be such that it ts in ones hand. Blade section should be
sucient for enduring the cutting eort.
What about costs?
Steel is more expensive than wood or plastic. A this point we have to

dene the acceptable compromise between cost and lifetime.
For the handle, the material can be softer, cheaper than the blade ma-
terial at the expense of a more complex assembly process. Again, it's a
compromise.
Manufacturing process impacts costs. Drop forged steel, machined steel

or cast steel have dierent costs and dierent performance.
What about cultural criteria?
With respect to these criteria, the handle material can be chosen for its
look and feel or for its environmental impact, from wood to gold...
Shape can be made attractive, in addition to be functional. But the

denition of a nice shape is really a matter of culture, of context, of
period.
3.4 Complex object design

For a complex object, resulting from a combination of simple objects, things
change a bit with respect to simple objects.
In addition to choosing and validating the choices, the designer has to

divide, to split, to distribute. The problem to be solved has to be divided
in simpler problems, the process has to be serialized.
This is where design is actually a creative activity.
The three parameters the designer has to choose change a bit:
Nature of lower level objects stands for material: Our knife is not
made from steel but from a blade and a handle.
Topology of arrangement stands for shape: Our blade and handle

have to be assembled together in the right way.
Values of lower level object stand for size. Our blade has a size, but
also a hardness for instance.
These parameters are functionally equivalent to those of a simple object:
Nature is the most intrinsic parameter. A capacitor is a capacitor

and behaves as a capacitor whatever the way it is used and whatever
it's value. This is why nature as the intrinsic property is equivalent
to material.
Topology is the extrinsic parameter. Connecting capacitors in series

changes the resulting value, not the capacitive behavior. This is why
topology as the extrinsic property is equivalent to shape.
Value is the numeric parameter. It is not a property in itself, it

denes the value of a property. This is why it is equivalent to size.
A complex object may have more than one characteristics so it may
have more than one value.
For complex systems, objects can be complex as well. In this case, nature
can be a functional denition such as amplier of DSP. Topology cannot be
described easily and often requires a schematic or a formal language description.
Value can be a set of parameters since the more complex the object, the more
properties it exhibits.
3.4.1 Options and criteria

The same principles as for simple objects apply for selecting from a list and
having criteria for selection.
3.4.2 Remark
Making a choice means selecting an item within a set. Keeping the rst idea
that comes to mind is not making a choice. At least two options should exist
for a choice to take place. Very often, when a rst choice is performed between
the initial options, new options come to mind because of the reasons that make
some options fail.
3.4.3 Example
As an example again, imagine our goal is to design an electronic circuit:
Components can be a resistor or a MOS or another electronic component.

This nature is logically equivalent to the material like steel or wood for
a simple object.
Components such as resistors can be connected for instance in series or

in parallel. This topology choice is logically equivalent to the shape like
square or circular of a simple object.
A capacitor, for instance, has a value in Farads which is logically equiv-

alent to the size of a simple object in meters or inches.
3.5 Architecture and Sizing

Choosing topology and nature of sub-blocks is called ARCHITECTURE.
Choosing values for sub-blocks characteristics is called SIZING.
3.6 Validation
Making and implementing choices is an error prone process:
To make choices, the designer uses his brain and he may make mistakes.
To implement the choices, the designer uses his hands and he may make
errors.
For these reasons, validating choices is mandatory. Many issues during product
design result from lack of validation.
3.7 Hierarchy
The simple examples above have introduced the idea of hierarchy for addressing
complexity. Complex designs can be managed only if complex objects are
divided recursively into less complex objects. This methods also allows to
share the workload between several designers to get the job done quicker.
3.7.1 Cells
In a hierarchical electronic design, the various blocks are usually called cells.
One cell diers from all the other ones: The Top-cell. As its name states it,
this cell contains all the other ones and no other cell contains the Top-cell.
Some cells contain only electronic components but no other cells. These cells
are usually called leaf-cells. This refers to a tree. It has a trunk, branches and
leaves. Some branches hold leafs and other branches. Some branches hold only
leafs.
Trunk is called Top-cell
Branches are called Cells
Leaves are called Leaf-cells
3.8 Design levels

The design level that can be dened by a number ranging from 0 to 4. Ranking
is based on depth of what the designer deals with. The deeper the parameter,
the higher the score. In this scale, nature is the heaviest parameter, topology
is second and value is the lightest parameter.
Level 0: Copy. Change nothing.
Level 1: Re-size. Change values.
Level 2: Modify. Change topology, natures and values.
Level 3: Combine. Merge topologies and change natures and values.
Level 4: Create. Imagine new topologies, choose natures and values.
This design level details the kind of design activity:
3.8.1 Copy
Many classic design problems have some standard solutions that have proved
to be ecient and reliable. Using these solutions out of the box results in the
fastest and safest design route. This is the base of the so called IP business.
The only requirement is that the copied cell meets or exceeds the target
specication.
One limitation is that sometimes a simpler solution might exist and would
result in a smaller silicon area. A compromise must be found in this case
between a shorter and safer design route that reduces NRE costs and a
smaller and simpler solution that reduces production costs.
3.8.2 Re-size
If no ready to use solution is available, resizing an existing solution is a rea-
sonably fast and safe design route. Resizing is changing sub-blocks values.
Basically, resizing changes a cell performance without changing its functional-
ity.
Requirements are that the origin cell functionality meets or exceeds the
requirements and that re-sized cell performance can meet the target spec-
ication.
The same limitation as for copy exists: A simpler solution may exist but
would require more design work. Again a compromise is often required.
3.8.3 Modify
If functionality has to be changed, modifying an existing solution is faster and
safer than more creative design routes. Modifying is changing both topology,
cells nature and characteristics.
The approach being more exible and creative than lower levels, limita-
tions in functionality and performance is less critical.
The limitation that exists in copy and re-size approaches is not as critical
here: If a simpler solution exists it can be implemented in the modi-
cation process eventually at the expense of more design work. Again a
compromise is often required.
3.8.4 Combine
If nothing is available to re-size or modify, combining existing solutions brings
a new solution while keeping some safety and limiting eort. In this approach,
combining existing or modied topologies extends the functionality and per-
formance domain further.
This approach suers only few limitations and is one of the most powerful.
It can bring outstanding performance at a reasonable design eort.
3.8.5 Create
If everything else has failed, a new solution must be created. This is a longest
and most dicult design route. It is strongly recommended to always use the
lowest possible design level. The boundary between combining and creating
is not very clear. Creating something new is generally combining existing
functions. Creation might be dened as bringing a new functionality that did
not exist before.
3.8.6 Design route

It is a good practice to begin with level 0 and then increase level until a solution
is found.
The time spent trying the lowest levels is short and anyway shorter that
starting at a too high level.
But, in addition, it is also a good way of reviewing the specication and

nding missing items at an early stage. And part of the work, like setting
up the design validation can be reused.
Chapter 4
TOP-DOWN Design Flow
The graph below describes the top-down design ow to be used when designing
complex systems. It is dicult to gure time in this ow. Locally, at each
hierarchical level, time ows vertically from to to bottom, but globally, it ows
horizontally from left to right. In addition, for complex designs, a number of
designers work in parallel so, at a given level, cells can be designed at the same
time.
Figure 4.1: Hierarchical Flow
Specification
Architecture
Sizing Specification
Implementation Architecture
Validation Sizing
OK? Implementation
Level N Validation
OK?
Level N-1
This ow is based on the intrinsically hierarchical nature of complex designs:
Here, only two hierarchical levels are shown, but of course, there are
generally much more.
35
CHAPTER 4. TOP-DOWN DESIGN FLOW 36
Arrows on the left and right sides are intended to show that there are
levels above and below.
Architecture, as already stated, consists in choosing the nature of sub-

blocks and the way they are connected together.
Sizing consists in choosing the sub-blocks characteristics.
For implementation and validation, the top level loop diers from the
lower levels loops.
Of course, since at each level, architecture and sizing involve several cells, at
the level just below one loop will exist for each cell. They could be gured as
several sheets for each level.
The top level loop is the product development loop as dened above. For
this loop:
Implementation consists in manufacturing the product.
Validation consists in measuring the parts in the lab.
For lower level loops :
Implementation consists in capturing architecture and sizing into a CAD

system.
Validation mainly consists in simulating the circuit and checking design

rules.
4.1 Recursive Loops

Loops at any hierarchical level look like the global development loop.2
The design of a level N block starts from the specication.7
The rst step is choosing or creating the architecture.8
The second step is sizing9 every block in the architecture. Level N sizing
denes specications for level N-1 blocks.
The third step is implementation. 10Every sized block has to be trans-

lated into ready for manufacturing data.
The fourth step is validation.11 The sized architecture must be checked

with respect to the specication.
Just like for the development loop, the design loop is ideally walked through
only once...
If everything is correct, design for level N is over, level N-1 design can
start.
If design validation fails, sizing must be changed rst because this design
loop is reasonably short.
If no suitable sizing can be found, the architecture must be changed. This

design loop is much longer than the sizing loop. This is the reason why
it is done in a second step. This is also why architecture choice should
be secured before sizing even though this cannot be done with the help
of simulation.
If specication cannot be met, it must be changed, but this requires

agreement from level N+1 designer. This loop is extremely long and
risky. It implies other people and can be a major risk for the project.
This is why it is done only when nothing else can be done. This is also why
the specication should not ask for more than what is required and what
is reasonably achievable. This is also why risk analysis at the beginning
should be done very carefully.
Globally the development phase is a large set of loops inside each others.
Again, it is basically by reducing the number of times loops are walked

through that the development time can be made shorter.
4.2 Controlling recursion

Everyone knows that recursion must be controlled in software not to result in
innite execution time or innite memory requirement. In real life, recursion
should also be controlled so that design time and cost are nite.
4.2.1 Recursion depth

How many levels are there and when does the process stop? There is no simple
answer to that simple question.
Number of levels depends on design complexity
The more complex the design, the larger the number of levels
The process stops when an existing object is met.
Existing object can be an already designed cell or a basic component.

Sometimes, a new component has to be created. This adds one more
level down.
If a technology has to be developed, this pushes the level down even

more...
4.2.2 Convergence
Since the number of items is nite, the time it takes to walk through the loops
can be nite: The process can potentially converge.
This is good news but it is not sucient.

Ensuring convergence and ideally fast convergence requires a method. The
idea is that as the amount of design work already done increases, the probability
of redoing it decreases.
This goal can be reached by ranking the requirements. The most strin-
gent requirements have to be addressed rst and the details have to be
addressed at the end. The key is then to identify the hardest design
issues.
This is basically what makes the dierence between a skilled designer and a
less experienced one. This is also why solving a new problem, addressing a
new domain is harder than staying in a well known domain and solving new
problems. However, trying to gure out the dicult issues is a must.
One practical approach is to consider the issues one after each other and
wondering how each could be addressed. For some issues, possible solutions
quickly come to mind. These will be addressed later on. For some issues, no
obvious solution appears. These have to be moved up in the list.
That can seem strange but the immediate solutions have to be addressed at
the end while the issues without solution have to be addressed rst. Among
these top issues, one can appear more dicult than the others. It should be
addressed rst. Even if this ranking is not the right one, it should not be so
dierent from the right one. Doing so helps building design experience and
makes it easier for the next times.
Chapter 5
Feasibility study
A product development should always start with a feasibility study. A product

is feasible if:
The specication does not violate the laws of physics!
The specication is achievable with available technologies and tools.
The specication is achievable with available skills and resources.
The target price is compatible with production costs.
The return in invest occurs in a reasonable time frame.
If one or more of these sentences is not true, project should be considered risky.
Risk level depends on which sentence(s) is (are) wrong.
If project violates laws of physics, it is an absolute show stopper. Project

denition must be reworked.
Other points might be addressed if the project is worth it:
If technology and/or tools are missing, either project has to be redened

or tecnology/tool have to be developed.
If resources/skills lack, they can be added.
If price is too high, production might be improved.
If return on invest is too long, production might be improved or market

might be developed.
The larger the number of negative points, the more risky the project is and the
less it is worth doing it.
5.1 Laws of physics

This is so obvious that it is important to keep it in mind! One often forgets
obvious things. However, most requirements comply with the laws of physics,
fortunately.
39
CHAPTER 5. FEASIBILITY STUDY 40
Some laws are sometimes considered as fundamental while they are not,
being only a limited collection of experimental data or extrapolated trends.
These laws can be overcome why the laws of physics can't.
As an example, in the years 1980's it was considered that light dirac-

tion would make it impossible to manufacture devices smaller than 1 µm.This
was based both on physics (diraction) and technology (scale 1 masks, UV
wavelength). Using steppers with mask scale 5 or 10 and using shorter UV
wavelength and eventually immersion lithography could overcome this limit
that was not one. And since diraction is a predictable phenomenon, it can be
integrated by pre-distording masks drawing so that nal pattern is correct.
But that did not come for free and was possible only because the market
was large enough to absorb the costs of developing these technologies and tools.
5.2 Technologies and tools

Not only must the specication be achievable in absolute, but also it must be
achievable with what is available... If a process exists to do the job but if
this process is not available to you, the product is not achievable. If special
tooling is required, either for designing or for manufacturing the product and
if either one is not available nor aordable, the product can't be done. In
particular,questions to address are:
Absolute maximum ratings. Temperature range and operating voltages

must be within the technology capabilities.
Board soldering technology. Parts must not be stressed over their capa-
bilities during board soldering.
Package on board thermal capability. The dissipated power must not

drive the junction temperature above maximum allowed value.
Design tools.
Manufacturing tools.
Sometimes, these limitations can be overcome by partnerships, subcontracting

or even fusion-acquisition operations.
5.3 Skills and resources

When the product is feasible in absolute and the process and tools are avail-
able, the required skills must be available and the available resources such as
design manpower and production capacity must be sucient to reach timescale
requirements and production rate. Questions to answer:
Are the product function and performance within the design team domain
of experience?
If outside the domain, how far?
Is the workload divided by the design team size compatible with the
target timescale?
Hiring and training can address this kind of concerns. And again, partnership,
subcontracting or fusion-acquisition can be options.
5.4 Costs
This is probably the most important issue: A product can be done if it makes
money. But this is addressed at the end since it depends on all the other
items even though, practically cost aspects must be kept in mind permanently
during the feasibility study (and during the entire product life!).Integrated
circuits costs divide mainly in two parts:
NRE costs. Expenses like design manpower and mask tooling are done
once in the product life.
Production costs. Every part costs money to produce.
There are many options to reduce costs. They have to be analyzed and con-
sidered to eventually unlock a situation.
5.4.1 NRE costs

NRE costs mainly include development manpower, masks, test tooling, test
program and lab equipment for validation.
Manpower costs must be evaluated. Apart from salaries, additional costs
such as xed costs and software licenses must be taken into account. These
can more than double the cost of manpower.
Mask costs strongly depend on process generation. Mature processes masks
are not so expensive while the latest processes have huge mask costs.
5.4.2 Production costs

Production costs divide in three parts:
Silicon
Package
Test
5.4.2.1 Silicon cost
Silicon cost is more or less proportional to IC die size. In fact, cost increases
a bit quicker than die size because of the yield impact. For a given defects
rate, the larger the chip, the more likely a defect to occur. The cost per mm2
depends on the process.
Factors impacting the cost are:
Lithography feature. The ner the devices the more sophisticated the
equipment and the environment, so the higher the cost par wafer.
Number of masks. This denes roughly the number of elementary process

steps. The higher this number, the higher the cost.
Wafer size. The larger the wafer, the more circuits manufactured at a
time, so the lower the cost. But larger wafers require larger, so more ex-
pensive processing machines, longer time spent on the steppers to expose
the entire wafer area and these eects limit the benet of larger wafers.
Process maturity. After the introduction phase of a new process, continu-

ous improvement takes place, yield improves, the initial cost of equipment
is amortized and nally cost reaches its nal oor value.
5.4.2.2 Package cost
Package cost depends on:
Package technology. Technology denes materials and process steps.

Both impact cost.
Package size. This denes the cost of materials for a given technology.
Number of pins. This denes the time spent in bonding the wires and to
some extend the cost of wire.
5.4.2.3 Test cost
Test cost depends on:
Type of tester. Number of pins, performance, analog and digital capabil-

ities impact tester hourly cost.
Test time. Obviously, the longer the test, the more expensive.
5.4.3 Total cost

There are mainly two models for calculating the product cost. Either the
NRE costs are covered separately, either they are distributed over production.
The rst approach is standard for low volumes, the second for high volumes.
Sometimes, an hybrid approach is used. Part of the NRE costs is covered
separately, part is distributed over production.
5.4.4 Product sales price

Product sales price is calculated taking into account production costs and tar-
get margin. As already stated, sales price suers from a signicant reduction
pressure in the 5 to 15 % per year depending on volumes.
5.5 Results
At the end of the feasibility study, four items must be available:
The product feasibility and associated development risks.
The product NRE and production costs including a risk factor.
The product planning with two options: The best, optimistic scenario
and a more conservative, realistic one.
An estimation on the ROI date and the capital interest over time in the
various volume production scenarios.
These data are the basis for deciding whether the project should be done or
not. As can be seen, it is a mix of technical and economical considerations.
Chapter 6
Design Management
A number of tasks have to be done prior to starting design at properly speaking.

These tasks are aimed at validating data to be used for design and setting up
the methods for addressing the design challenge and the structure for handling
the design data.
6.1 Design kit

A design kit is a set of design aid tools and associated data that are used by
the designers in their day to day design implementation and design validation.
All the design validation relies on simulations based on the design kit.
6.1.1 Design kit validation

As the design kit is a major tool for the designer, it requires validation. It is
important to know exactly the design kit status, what works properly and what
does not. It is possible to use successfully a less than perfect tool provided the
fact limitations are known.
Then it makes sense to validate extensively the Design kit even though the
designer has limited possibilities to change the tool that usually comes from
the silicon supplier which is either a separate company or a separate division
in the same company. However knowledge of strength and weaknesses of the
tool is important for using it properly and eciently.
As it requires a good knowledge of components behavior, Design kit vali-

dation is detailed later for each component type in part 2
Before design can start, the design kit status should be clear and all the
designers should be aware.
6.1.2 Design kit status

Design kit status is a document summarizing the design kit validation phase.
This document that must be made easily available to every designer must
include:
Components models (accuracy and exhaustiveness) 17.1
44
CHAPTER 6. DESIGN MANAGEMENT 45
Parasitic components (list and management strategy) 25
Size multipliers, series and parallel connections
Implied connections management
...
6.2 Process options and components list

Every designer in a team should be aware of the process options that have been
chosen and of the components that are allowed for the design. Process options
include items like:
Number or metal layers
Special devices
The number of options impacts the production cost so it usually has to be kept
to the minimum. However, if an option can simplify either the design or the
layout and results in a smaller chip, a detailed cost analysis must be carried
out to make a decision.
The options list can seem obvious for any member who has joined the team
at an early stage, but not for a member who joins later on.
A table describing options and components should be accessible to all in
a common, read only, directory and any member joining the team should be
given access to this directory. Compliance to this list is an item to be checked
during design reviews.
6.3 Multiple access design

A design method that secures the data is required when more than one de-
signer work on a circuit. Only validated cells should be placed in the circuit
library, but each designer, during his design work can perform trials that result
in cells that, temporarily, do not work properly and should not be used by
others. A good practice is that each designer should work in his own library.
A designer's own library is not supposed to contain only reliable data. Once a
cell is validated, it should be copied to the circuit library. To avoid the dan-
ger of deleting cells by accident, the circuit library should be read only for all
users but the design leader and his deputy. The design leader or his deputy
should copy cells from the designer's libraries when requested to do so. Special
attention should be paid to these copy operations. In particular, when hierar-
chical cells are copied, reference library should be changed so that the copied
version is consistently located in the circuit library. Any warning during these
copy operations should be analyzed carefully. Finally, a good practice is to run
the characterization on the copied cell in a library that only has access to the
circuit library. This ensures that the copy was correct and consistent.
6.4 Revision control

Revision control is a major issue in circuit design. The question is:
In case a cell has to be changed after is has been copied to the circuit library,
what about the previous version?
If the new version xes a serious bug that really prevented the previous
version to work properly, the old version could be dropped. In this case, the
new version simply replaces the old one.
But if the new version achieves a new balance between performances, the
old cell could have interest too. In this case, the two versions should survive.
The concern is that the library manager tool might not manage versions.
In this case, a possible solution is to sux the cell name by a version number.
It is a non ideal solution since it is not true revision control, but it brings the
capability to manage dierent versions.
6.5 Naming convention

Naming cells is important, especially when more than one person design a cir-
Dening a naming convention at an early
cuit, to avoid confusion and collision.
stage, can avoid issues and avoids renaming later on. It is a good practice to
dene this convention even before any cell is designed. One suggested method
is that cell names start with a prex that identies the top block. Then the
cell name can continue with a core that identies functionality. A number can
be added then for the purpose of identifying dierent cells with the same func-
tionality but dierent performances. The cell name might continue with two
or three letters that identify the designer. The cell name should then end with
a revision indicator.
Example: If the top cell is built from several blocks with one of these being
a modulator, cells inside the modulator can be given names like:
MOD_OTA1_XY_V10
MOD_OTA2_XY_V10
MOD_CMP1_XY_V10
MOD_BIAS1_XY_V10
MOD_BIAS2_XY_V10
MOD_BIAS2_XY_V11
A good practice is to dene a naming convention for signals too. This reduces
the risk of errors. Indications a signal name can handle can be:
The analog or digital signal type.
The voltage or current nature of a signal.
The active high or active low signal polarity.
...
6.6 Documentation structure

All the documents relating to a design should be located in a special place
that can be accessed by all the designers. The documentation structure should
comply to a standard structure. However, special needs can exist that require
additional documents.
For the standard documentation structure to support extensions, a spe-

cial le, preferably a spreadsheet le should contain a list of all documents
with links.
Basically design documentation should contain specications, design books

and data sheets.
Design traceability and design reuse require that documents are created and
updated all along the design work. A good practice is to initialize a documen-
tation structure that will be lled up with documents as they are created.
Templates for the important documents like specications and design
books can be helpful.
Documents should include revision control and successive versions should

be kept for traceability.
Writing documentation can be painful if done after the design is complete.

Doing it in real time not only is easier but also can improve the design eciency.
Writing a document requires asking the right questions. Reviewing a document
helps detecting remaining open issues or discovering inconsistencies. Some
simple rules should be kept in mind when writing documents:
The document is mainly intended to be read by someone else than the
writer.
A document should not use concepts that have not been dened previ-
ously.
A document might be read long time after being written, in a dierent

context.
Things that are obvious for the writer at the time the document is written
might not be obvious at all for the readers, including the writer, at the time
the document is read. Writing these obvious things is not so time consuming
for the writer but can save lots of time for the readers. So, a document should
contain indications on context and addressed problem. Important items such
as assumptions should be indicated clearly.
6.7 Power supply strategy

It can look strange to dene such a detailed item before design at properly
speaking. In fact, this could be considered as the very rst step of design, but
as it does not share the standard design ow structure it has been included
in the design management. The power supply strategy has to be dened at a
very early stage as it impacts the whole design and it is very dicult to change
this strategy later on. The supply strategy denes such things like the number
of dierent supplies, the way supplies will be propagated through the design
hierarchy etc...
6.8 Return from experience

Again, it can look strange to include return for experience at the beginning of
the project... This is done for two reasons:
It is time for using the return from previous experiences so as to capitalize

from them.
It is time for setting up the structure for collecting the experience, both
positive and negative, that will setup along the design.
6.8.1 Preparing the future

It can seem strange to prepare the future before looking to the past, but log-
ically you can only look at the past if you kept records from it at the time it
was not the past yet!
Among things to be included in a Return from experience document:
Everything that appears dierent from expectations whatever the reason.
Everything that was forgotten but appeared to be critical, ranked as Will

do next time
Everything that worked ne, ranked as To do.
Everything that went wrong, ranked as Never again.
It is a very common mistake to think that things will be completely dierent

next time, or that one will not make the same error twice. Experience shows
that we remember the good and forget the bad. In addition, return from
experience is not only for the people who lived it, it is also for others.
6.8.2 Using experience from the past

Obviously, all the items listed above have to be considered when a new project
starts. In particular, all the items that have been identied as to be done rst
or to be done early. The return from previous experience should be shared
widely among project members: Not all the members of a new project have
the same experience.
The time it takes is worth it: It saves much more time than it costs.
Most of this book contents is based on return from experience on a large
number of projects.
Chapter 7
Specication
As briey introduced, the specication for a given hierarchy level results from
sizing the upper level. This is the initial specication or requirement specica-
tion. Usually, such a specication is not sucient to completely dene a cell,
additional item are required. Some examples of additional items are:
Test modes, test pins.
Utility pins like bias, bypassing.
Acceptable non-ideal behavior.
Additional parameters required for choosing architecture or for sizing.
The nal specication or design specication combines requirement items and

implementation items.
For the circuit's top cell, the requirement specication is usually a cus-
tomer document and it cannot be modied easily.
On the other hand, some elements in the design specication are company
condential and cannot be given to the customer.
So, for a the top-cell design specication, managing a separate document is

usually the only solution. In this case, the design specication should contain
only the added items that result from implementation. For the other cells, the
design specication can be in the same document as the requirement specica-
tion. But it is important to keep record of which items come from requirement
and which result from implementation. A suggested solution is adding an in-
dication of origin in the design specication for each specication item.
To summarize:
The requirement specication is received from the upper level designer.
The current level designer adds items he needs to design the cell. Val-
ues for these items are asked to the upper level designer. The current
level designer also adds items from implementation. Values for these
items have to be dened by himself within the rules of the project and in
coordination with other designer for consistency purposes.
49
CHAPTER 7. SPECIFICATION 50
The current level designer writes the requirement specications for the
lower level designer.
Even in the case where the same designer manages two or more levels, it is a
good practice to write the specications.
7.1 Specication contents

A specication is a long list of items and parameters. In order to make it as
clear as possible, a specication is organized by sections. For each item in a
specication a good practice is to have an identier and a status.
7.1.1 Sections
Basically, a specication contains six sections. These sections are listed in a
particular order as they refer to each other.
1. Absolute maximum ratings. Absolute maximum ratings are often critical

to feasibility. This is why they are listed rst.
2. Operating conditions. This section contains a list of normal environment

conditions for the cell in the application. Parameters in this section are
similar to those in absolute maximum ratings.
3. Operating modes. This section describes the dierent operating modes.
4. Functions. This section lists the dierent functions in each operating

mode. This is why operating modes are listed before functions.
5. Pins. This section lists the pins that connect the cell to its environment.
Pins refer to functions. This is why they are listed after functions.
6. Electrical parameters. This section lists the cell electrical parameters.

These parameters fall in one of three types, input parameters, output pa-
rameter or transfer parameters. These parameters refer to environment,
pins, modes and functions. This is why parameters are listed at the end.
7.1.1.1 ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings dene environment parameters not to be exceeded

for the circuit to survive. Values between normal operating conditions and
absolute maximum ratings can be used for short periods without signicant
eect on reliability but functionality is not guaranteed and performances are
not specied. Using the circuit for long periods above the normal operating
conditions may permanently aect functionality or performances.
Parameters to be specied in this section are:
Temperatures, either package or junction or both.
Supply voltage.
Voltage at any pin.

ESD and latch-up data.
Usually, absolute maximum ratings are dened by application or sometimes by

particular regulations that apply for some applications. Most parameters in
this section are global for a circuit. This is the case for temperature or supply
voltage. Rarely, voltage on pins or ESD specication can be pin specic. This
is the case if some pins are connected to long wires that go outside the product
enclosure. Normally, such conditions are well identied at application level and
they can appear in the circuit specication even though they relate to lower
level cells. So, this section usually exists for a circuit but it is not necessary
to have it for an internal cell. For internal cells a reference to the top cell
specication is sucient.
7.1.1.2 OPERATING CONDITIONS
Normal operating conditions are environment parameters that allow perma-

nent operation without performance change or loss of functionality. Electrical
parameters are guaranteed only within the normal operating conditions.
Parameters to be specied in this section are:
Temperatures, either package or junction or both.
Supply voltage.
Mission prole is very useful when available so it should be made available

as often as possible.
Usually, operating conditions are dened by application. Just as for absolute

maximum ratings, operating conditions are usually global for a circuit but
some rare exceptions can exist. Again, for internal cells, referring to the top-
cell operating conditions is sucient.
7.1.1.3 FUNCTIONAL MODES
A circuit can have more than one functional mode. A simple example is the
power save mode in which the circuit is supplied normally but does not operate.
Another example is a wireless transceiver that can operate in transmit or receive
mode. When a circuit has several operating modes, the active functional blocks
depend on the functional mode so the electrical parameters depend on the
mode. There are no particular parameters to specify in this section which is
mainly a list of modes with denitions. Functional modes are dened by:
Application
Derived applications
Implementation
Obviously, most functional modes are application dened. But some modes
can be added so as to extend application range. As an example, a standby
mode in which the circuit does not operate but reduces dramatically its power
consumption can extend application to intermittent portable applications even
if the primary application does not require this feature. Implementation often
requires additional modes such as test modes or intermediate modes that are
required to switch properly from a mode to another. Functional modes are
dened for the entire circuit but they are implemented by each cell modes. For
instance in an RF transceiver, the top cell modes can be TX and Rx while for
lower level cells modes can be On and O. All the blocks that are used in Tx
have to be On in Tx, all blocks that are used in Rx have to be On in Rx. So,
this section must exist for all the cells in a circuit. The number of modes in a
cell dene the number of bits required to control the mode.
7.1.1.4 FUNCTIONS
This section lists functionality items. Usually, functions depend on functional

modes, so this section is often organized by functional mode. Again, there are
no particular parameters, this section is a list of lists. For the top-cell, functions
are most of the time entirely dened by application. For lower level cells, some
functions like bias cells are dened by implementation. So, this section must
exist for all the cells in a circuit.
7.1.1.5 PINS
This section lists the circuit pins. For the top-cell, most of the pins are dened
by application but some pins such as bypassing or test pins result from imple-
mentation. For lower level cells, some pins are application dened but most
pins result from implementation. So, this section must exist for all the cells in
a circuit.
7.1.1.6 ELECTRICAL PARAMETERS
Electrical parameters dene basically voltages and currents and their combina-
tions such as impedance or gain values. This section is organized by functions.
As functions depend on modes, this section can be organized by modes and
functions. Electrical parameters are grouped in tables. Each specication item
has a status, a reference, a description, minimum, typical and maximum values,
unit, and origin. Description has to dene pins, characteristics and conditions.
This section must exist for all the cells in a circuit.
7.1.2 Statuses
Items in the specication fall in one of ve statuses:
1. Must: This status denes that the item has to be met. In addition, if item
is dened as critical (indicated by symbol ∆), it must be 100% tested in
production.
2. Should: This status denes that the cell has some added value if item is
met.
3. May: This status denes that the item is a non-ideal behavior that the cell
is allowed to exhibit. Parameter denes limits to the non-ideal behavior.
4. Don't care: This status denes that item is not relevant, either because
condition cannot occur or because cell behavior in this case or perfor-
mance in this range is ignored.
5. Don't know: This status denes that item is to be dened.
The rst two statuses are directly related to the cell requirements. In other
words, they come from the upper level. They dene hard and soft design
constraints. The next two ones can be related to the requirement or to the
implementation. In other words they can come either from the upper level
either from the current level. They dene design degrees of freedom. The last
one is mostly related to implementation but can also be a requirement. This
status can only be transient. At some point, an item with this status must fall
in one of the other four.
For every parameter he writes in the specication, the designer should won-
der how this parameter will be checked during design validation and how this
parameter will be guaranteed in production. In order to design eciently, spec-
ication items should be ranked as they cannot be addressed simultaneously.
Designer's ranking is based on a mix of importance in the specication and dif-
culty to implement. Important items should be addressed before secondary
ones, and dicult to meet items should be addressed before easy ones. Archi-
tecture choices, sizing and even design validation should be based on the ranked
specication items. This is a good way to minimize rework.
7.2 Specication tools

As strange as it may seem, there are no specic tools for writing specications.
Specications are mainly text les that can be created with word processing
tools such as Word or Open Oce.
As specications contain many tables, a spreadsheet tool can be used but
they are less convenient for text sections.
The biggest issue with specications is that they depend on each other
through the circuit hierarchy and it is very dicult to keep them consistent
through design and specication changes.
Another issue is revision control.
7.3 Specication checklist

Writing a specication is a dicult exercise. Everything that can help is wel-
come. A formal specication review with other designers can highlight missing
items. A checklist such as the following can also help, eventually before a re-
view can take place. The following checklist is based on the proposed standard
specication structure. It is not intended to replace an existing specication
template but to indicate some items that are sometimes forgotten even though
critical for the design.
7.3.1 Environment
Ambient temperature:
Thermal resistance (depends on package and PCB environment):
ESD protection HBM: MM: CDM:
Duty cycle:
7.3.2 Operating modes

Standby:
Functional modes:
Test mode:
Mode switching time:
7.3.3 Pins
Supplies
DC values:
Transients:
Noise:
Rise/Fall time:
Protection against shorts:
Outputs
Static Load:
Dynamic load:
Acceptable noise:
Transfer
Supply rejection:
Common mode rejection:
Crosstalk:
7.3.4 Specication examples

7.3.4.1 Absolute maximum ratings
Status Reference Description Min. Typ. Max. Unit Origin
Must A1.0 Junction temperature -55 _ 150 °C Requirement

Must A2.0 ESD HBM _ _ 4 kV Requirement
7.3.4.2 Operating conditions
Status Reference Description Min. Typ. Max. Unit Origin
Must O1.0 Junction temperature -40 _ 125 °C Requirement

Must O2.0 Supply voltage 3 _ 5.5 V Requirement
7.3.4.3 Functional modes

Status Reference Description Origin
Must M1.0 Active Requirement

May M2.0 Standby
7.3.4.4 Functions
Active mode
Status Reference Description Origin
Must F1.0 Reference oscillator Requirement

Must F2.0 Power amplier Requirement
7.3.4.5 Pins
VDD Positive supply
GND Negative supply
In1, In2 Dierential RF input
Xtal1, Xtal2 External crystal pins
7.3.4.6 Electrical parameters
Cell XXXX specication

Status Reference Description Min Typ Max Unit O
Must E1.0 Supply current _ _ 2 mA Req

Must E2.0 Silicon area _ _ 0.25 mm2 Req
∆ E3.0 Pin A1 Input capacitance (note 1) _ _ 0.5 pF Req
Must E3.1 Pin A1 Input bias current _ _ 100 nA Req
Must E4.0 Pin O1 output resistance (note 2) 33 _ 75 Ω Req
May E4.1 Pin O1 output resistance 25 _ 100 Ω
√ Imple
Must E5.0 Output noise density 1 Hz-10kHz _ 5 _ nV /√Hz Req
Don't care E5.1 Output noise density above100kHz _ _ _ nV / Hz Imple
Don't know E6.0 Supply voltage rise time _ _ _ V /s Imple
Must E7.0 Pin C1 clock frequency _ _ 500 kHz Req
Should E7.1 Pin C1 clock frequency _ _ 2 M Hz Req
Note 1: With respect to ground
Note 2: At T=25 C°
Chapter 8
Architecture
Architecture work is choosing the way the cell functionality is divided into sub-
cells. It includes choosing both the sub-cell nature or function and the sub-cell
arrangements. Since a real circuit can be complex, it can require a number of
hierarchical levels. Depending on the hierarchical level the designer is dealing
with, the objects nature can change signicantly. Usually, top level objects are
complex and they get less and less complex as the hierarchical level decreases.
When it comes to deal with leaf cells, objects are electronic components.
Whatever the nature of objects, an architecture is required to dene the
kind of functions to use and the way the signals proceed between objects.
8.1 Architecture catalog

Where can the designer nd a list of available architectures?
A list of cells already developed in the team often exists.
Patents and publications can provide ideas.
Data sheets of existing products can provide valuable data.
The web is a large source of information.
As the design level 3.8 increases, it gets more and more dicult to give general
methods to address architecture work, but here are some guidelines:
8.2 Levels 0 and 1 architecture

For design levels 0 and 1, no architecture work is done at properly speaking as
design is either copied as is for level 0 or re-sized for level 1.
For level 0, work starts at design validation.
For level 1, work starts at sizing.
However validating the architecture is strongly recommended at least for level

1. This consists in checking that the chosen architecture is potentially capable
of achieving function and performances with an appropriate sizing. If not, it
is not worth trying to size the circuit.
56
CHAPTER 8. ARCHITECTURE 57
If architecture is not appropriate, design level should be increased to level

2.
8.3 Level 2 architecture

For level 2 design, work starts from an existing architecture that is considered
to be close to the target. Dierences with the target should be identied and
then:
Useless functionality should be suppressed.
Missing functionality should be added.
Dierent functionality should be modied.
Modication can be considered as a combination of suppression and addition,

but it is kept as a separate option since it is often simpler. Again, validating
the architecture is strongly recommended. If architecture is not appropriate,
design level should be increased to level 3.

For level 3 design, work starts from several architectures that are felt as good
candidates to be merged to reach the target. By assumption, none of these
candidates can do the job alone; otherwise this would be level 2 design. Only
synergy (the system does more than its components) can bring the function-
ality and the performance. The new architecture is based on synergy. It must
combine the intrinsic qualities of the parent architectures so as to increase per-
formance but it must also prevent or limit drawbacks from parents or from
combining. This work usually requires several iterations. Every new solution
must be validated. At this point, design validation is mainly checking function-

ality. Design validation often fails for early solutions, but the failure origin can
give indications for improvements. During level 3 design work, methods from
level 2 can often be successful (suppressing, adding and modifying). Again,
validating the architecture is strongly recommended. If architecture is not
appropriate, design process should be iterated.

Level 4 design usually results from failure in doing the job with level 3. For
level 4 design, work starts from specication only, but previous attempts at
lower design levels also give valuable inputs. And again, as soon as some ideas
take shape, validating the new architecture is mandatory.
8.6 Choosing an Architecture

Among the three design steps, architecture is the most demanding, the one
that requires the more skill. This is mainly because there is no well dened,
step by step method. However, here are some indications on the way to address
this design step.
8.6.1 Frequent topologies

Even though the number of topologies can be innite, experience shows that
some topologies occur more frequently. These frequent topologies are:
Independent blocks
Processing chains
Loops
8.6.1.1 Independent blocks
This is some sort of degree 0 architecture, but for top cells it is not so rare.
Circuits are sometimes just a collection of functionality that are not really
related to each other. In this case, architecture results in a list of independent
blocks. A good practice however is to wonder if some utilities or some sub-
blocks could not be shared. And usually the digital control block and the power
management block, if any, are common to all other blocks.
8.6.1.2 Processing chains
This is another very common situation. Signal processing, in a very general

sense, is usually divided in steps. In this case, architecture commonly follows
the same division and results in a processing chain built from successive blocks.
If processing involves non-linear functions, the blocks are to be assembled in
a well dened sequence. Swapping two blocks would result in a dierent pro-
cessing. If processing only involves linear operators, the sequence might be
changed without impact. However, true linear operation is a theoretical be-
havior that an actual circuit can only approximate to some extent. Then, the
processing sequence must be dened carefully. The eects of non-linearity, the
signal to noise ratio are some elements to consider when choosing the processing
sequence.
8.6.1.3 Loops
The most frequent reason for choosing a looped architecture is accuracy. Most
loops compare the output to the target and use the error signal to correct the
output. As loops exhibit this capability to correct at least part of their own
errors, they are usually accurate and robust.
8.6.2 Specication items ranking

As already stated, a good approach to the architecture work is to rank the
specication items in such an sequence that it helps choosing the architecture.
Ranking items properly is a dicult task that requires experience. Here are
some indications to rank items properly.
Of course, since at this point we are dealing with architecture, only

specication items that relate to architecture should be considered.
Items related to architecture are:
Accuracy and all related items like drift, rejections etc. . .

Robustness, reliability and portability.
Performances versus process capability.
The rst item in the list should be the most critical one. Critical aspect can
be evaluated through discussions with other designers, by searching standard
products performance or by looking at state of the art in published papers.
Architecture should be chosen in such a way that it addresses rst the most
critical specication item. It should be shaped by the rst item. The selected
topology should directly derive from the rst item.
Should the rst item be a good accuracy, it would suggest a large gain
loop.
Should the rst item be a demanding noise gure, it would suggest a

large gain, low noise rst stage.
The other items should be ranked by order of critical aspect. They should be
taken into account to rene the selected architecture.
8.6.3 The three layers model

Specication items mainly fall into 3 categories:
Input specications.
Output specications.
Transfer specications.
An approach that proved to be ecient is called the three layers model.
Input characteristics dene the input layer, the functional block that
receives the input signals.
Output characteristics dene the output layer, the functional block that
delivers the output signals.
Transfer characteristics, together with the expected transfer characteris-

tics of input and output layers dene intermediate layer.
This approach can be iterated if intermediate layer appears too complex to be

implemented in a single block.
Design usually starts with the most stringent input or output spec-
ication. It is then not so rare that design starts with the output
stage. . . If design has to start with the intermediate layer, iteration is often
required to take into account actual I/O layers characteristics.
Input layer Intermediate layer Output layer
Dened by input specications Dened by output specic

Has some transfer characteristics Has some transfer characte
Dened by transfer specications and
other layers transfer characteristics
This scheme is to be iterated.

8.6.4 The V cycle

The V cycle refers to the idea that the design process consists in recursively
splitting the circuit in smaller blocks.
Along the design phase, designers go deeper and deeper in the circuit
hierarchy and the objects complexity lowers. As this process takes place,
test-cells for validating the resulting blocks are developed. This process
down to leaf cells is the left hand, downwards going half of the V. This
design phase can be called synthesis.
Once every leaf cell is designed, the circuit is build with, simply replac-
ing behavioral descriptions with actual designs. The test-cells that have
been developed and used during the synthesis phase can be used to vali-
date the actual circuit operation. This process up to the circuit top-cell
is the right hand, upwards going half of the V. This design phase can
be called verication.
time
Top cell Top cell
Level -1 Level -1
Behavioral cells Physical cells
........ ........
Level -N Level -N
Behavioral cells Physical cells
Leaf cells
Synthesis Verication
8.7 Architecture tools

8.8 Architecture validation
As already stated, it is a good practice, whatever the design level, to validate
the architecture prior to start sizing. The time it takes to validate architecture
is negligible when compared to the characterization time and can potentially
save lots of time by reducing the number of iterations in the loop.
The way the architecture is validated completely depends on the design

level3.8.
Levels 0 and 1 architecture validation
In levels 0 and 1, validating the architecture is just checking that the cell
functional modes and functionality cover the requirement. This can seem a
bit formal, but can be done very quickly and can save lots of time if only a
detail that was not foreseen is not compliant. This detail would appear after a
signicant amount of characterization work that would have to be done again
later on.
Levels 2, 3 and 4 architecture validation

In level 2, 3 and 4 architecture is modied so it must be validated at properly

speaking. This is a dicult task that is mainly based on the designer's capa-
bility. The method looks like mental simulation, some what if play. Result is
a feeling that the architecture should do the job. This exercise requires a good
experience in this eld. It is, of course, simpler for level 2 and more dicult
for level 4. A good practice for building the required experience is to start by
level 2.Simulation can help, but running a simulation requires that the cell is
sized and this is normally not the case. A possible solution is to size the cell
roughly and to run a simulation to check if functionality is correct, whatever
the performances are. Again, experience can help choosing a reasonable sizing,
but, at this point, experience in the team can be shared with benet. Asking
a more skilled designer or even searching through literature or on the web can
give valuable information. Attention must be paid, in this case, to the fact that
the boundary between functionality and performance is not very clear. Making
several simulations with dierent sizing sets can help.
8.8.1 Architecture checklist

Chapter 9
Sizing
Sizing work takes place only if the cell is changed or completely new. Sizing
is choosing the sub-cells characteristics so as to achieve the cell target per-
formance. Sizing is signicantly dierent for a leaf cell where sub-cells are
components or for an intermediate cell where sub-cells are cells. This will be
detailed later on. First, lets consider the possible methods for sizing.
9.1 Sizing methods

9.1.1 Brute force sizing
As an example, if a cell contains only ten sub-cells, each of these sub-cells
having only two parameters, each of these parameters having only 20 possible
values. . . This example is much simpler than most real life sizing situation.
However, the total number of possibilities is about 1026 . . .
If it could take only 1 second to check one sizing (very optimistic!), it

would require 200 millions times the age of universe to analyze all the
possibilities.
Even if parameters had only two possible values, scanning all the possi-
bilities would still require more than twelve days. . . at one attempt per
second.
This example is just intended to show that using a pure brute force, computing
intensive method is generally not the solution. Educated guess can often reduce
dramatically the number or variables and can sometimes allow computer based
sizing.
9.1.2 Math based sizing

The most ecient method for sizing a cell is to express the cell characteristics
as math expressions involving the blocks characteristics. Then, drawing a de-
pendency graph shows free parameters, linked parameters, constraints, loops
or contradictions and helps choosing a solve path.
At this point, symbolic math tools can be very helpful to run the required
calculations.
62
CHAPTER 9. SIZING 63
The main concern with this method is that it may result in very compli-
cated math that cannot be solved.
In order for this method to give good results, only relevant blocks parameters
should be considered for sizing. Again, a good approach is to consider only
the specication items that have been ranked as important for the design. If
sizing with a limited set of specication items leads to a design that meets the
entire specication the problem is over. If the solution is not fully compliant,
adding items to rene sizing is usually not very dicult. The dependency graph
is getting a bit more complex but the calculation principle is not completely
dierent. And again, the specication items that are not met usually give
indications on important parameters that can then be taken into account. In
case the math approach cannot be used, a model based approach can be a
solution.
9.1.3 Model based sizing

Of course, design activity is always based on models. Model based design
usually stands for a design method that uses suitably simple models at high
hierarchy levels. If diers from ordinary design in the fact that models are
usually user dened instead of being standard models.
In this method, model accuracy i.e. eects actually taken into account is
some sort of a design variable that is continuously adjusted so as to see
what eects are important.
This method also implies replacing a structure by its important behav-

ioral characteristics in order to speed up simulations and calculations.
Design tips such as replacing a cell by its polynomial transfer characteristics

or by a look-up table are typical from model based design.
9.1.4 Hybrid methods

Very often, actual sizing results from a combination of educated guess, com-
puter based, math and model based sizing.
9.1.5 Managing tolerances

Except the constants of physics, all the parameters in a circuit are subject to
tolerances and drifts. Validating the impact of tolerances on the cell perfor-
mances is the goal of design characterization as dened in the design validation
paragraph. Improperly managed tolerances are the major source of design char-
acterization failure. When sizing a cell, tolerances should be kept in mind. This
is probably the best place to save time in design. This is also a place where
dierent architectures that seem equivalent may reveal their true dierence. A
robust architecture is much less sensitive to parameter tolerances and ensures
faster characterization and consistent production yield.
9.2 Sizing example: Square root circuit33.2

9.3 Leaf cell sizing
As already stated, a leaf cell contains only components. Sizing a leaf-cell means
choosing components parameters. This is somewhat dierent from choosing a
cell parameter:
A component behavior is not user dened as it is for a cell.
The list of parameters for a component is not user dened as it is for a

cell.
Components usually require biasing around some operating point so as to ex-

hibit the desired characteristics. In this case, sizing is a two steps process.
One step is choosing components size and operating point that give the de-
sired performance, and then choosing additional components values so that
the operating points complies with the target.
Leaf-cells require a special validation technique. First, operating point must
be simulated and compared to target. If incorrect, it must be analyzed and
changed until it is correct. Then the cell performance must be checked. Then
operating point robustness must be checked. Operating point must be unique,
DC and AC stable, process and environment stable. Then characterization can
take place.
As leaf-cells are not ideal blocks, they must be checked against a large
variety of conditions like power-up and power-down.
9.3.1 Sizable parameters

A look at the equations that rule the performances of a cell show that variable
in these equations fall into six categories:
The constants of physics.
Environment parameters.
External parameters.
Technological parameters.
Geometry parameters.
Bias parameters.
Let's now review these categories.
9.3.1.1 Constants of physics
These constants, such as q, the electron's charge, or k, Boltzmann's constant
cannot be sized at all. They are what they are. The good news from a design
standpoint is that they are not subject to change without notice!
9.3.1.2 Environment parameters
These parameters, such as the temperature and the supply voltage could be
used as design variables but if they can appear as degrees of freedom for the
designer, they are constraints for the user. These parameters should be used
only if no other solution can be found and if the upper level designer, and by
extension the customer agrees.
9.3.1.3 External parameters
These parameters usually specify external components. Their value can some-
times be discussed. These values are aected by tolerances.
9.3.1.4 Technological parameters
These parameters, such as the gate oxide thickness or the bipolar forward
current gain can be considered as exible to the designer. This is true only
within the limits of available processes. Of course, these parameters remain
exible until the process is chosen, they are xed afterward. The designer
should always keep in mind that anyhow, technological parameters are aected
by tolerances.
9.3.1.5 Geometry parameters
These parameters such as a MOS width and length are among the most used as
design variables. Tolerances on geometry are quite tight but they exist. Apart
from that, geometry parameters are free for the designer and can be changed
along the design process. But they must be xed before layout, unless the
cell provides some means of keeping it programmable, either by metal masks
or through programming. In this case, geometry can be changed during test
and even in the application. This is typically what is done sometimes during
calibration.
9.3.1.6 Bias parameters
All active electronic devices exhibit non linear characteristics and can handle
currents only in one direction. When it comes to handle analog signals that
can vary continuously around zero, a bias is used. Bias currents are very
important design variables and as such they are among the most used. They
can be changed along the design process but usually have to be xed before
layout. As for geometry, circuits can provide means of changing bias. Bias
can then be changed during test or in the application. Bias can also be self
adaptive in order to compensate for process parameters or temperature. This
kind of approach is often used in robust designs. Unless controlled by such
techniques, bias parameters are aected by tolerances.
9.3.2 Circuit's equations

The equations that describe the operation of a cell fall in three categories:
The equations of physics.

The devices equations.
The cell equations.
9.3.2.1 Equations of physics
These equations such as the Kirchho Current Law apply in any electrical
circuit.
9.3.2.2 Devices equations
These equations such as those describing the currents versus voltages in a MOS
transistor or in a bipolar transistor apply to each device in a circuit.17.1
9.3.2.3 Circuit equations
These equations such as expressing the voltage gain or the input impedance
are directly related to the circuit characteristics. Other equations in that type
derive from operating constraints that are usually conditions that must be
granted for the cell to operate properly.
9.3.3 Sizing sequence

The set of equations that completely describes the operation of the cell includes
the three types of equations.
Usually, cell characteristics can be expressed as function of small signal
parameters from devices. These equations result from cell equations and laws
of physics.
Then devices small signal parameters can be expressed as functions of siz-
able parameters, geometry and bias.
Sizing a cell is solving the set of equations so that the cell characteristics
comply with the specication. There are often more sizable parameters than
equations and nding an appropriate sequence for solving is not so obvious.
But the dependency graph method can help.
9.3.3.1 Dependency graph method
There is one dependency graph for each cell characteristics but the graphs can
share some sections in common. Each graph is built starting from the equation
that expresses the cell characteristic as a function of components or sub-blocks
characteristics. Each characteristic is gured as a box and dependencies are
gured as arrows. The graph is built step by step until it reaches primary
parameters. Primary parameters are parameters that do not depend on any-
thing. Among primary parameters are the constants of physics that are useless
for sizing, but also geometry and bias parameters that are free for sizing.
9.4 Sizing validation

Sizing, as any design activity is intrinsically error prone. As indicated above,
sizing is usually based on simplications and sometimes assumptions. Changing
the sizing of an existing design can have side eects. For these reasons, sizing
has to be validated.11.1
Chapter 10
Implementation
Any design has to go through a complex process for translating the concept
into an actual object. For a complex object, the upper level loop, as already
stated consists is the development 2phase itself. In this loop, implementation is
manufacturing the object. For the lower levels loops, implementation consists
usually in creating the data for manufacturing.
In IC design, the implementation phase consists in translating the sized
schematic which is some sort of a symbolic description including architecture
and sizing into a physical description. This phase called LAYOUT adds some
specic constraints to the design.
Along the Architecture and Sizing phases, the design is usually a set o les
in a CAD system.
10.1 Floor plan

Before starting the layout work at properly speaking, in order to simplify layout
operations, a oor plan phase is strongly recommended. Floor planning consists
in evaluating the surface of all the top level cells and trying to place them with
an appropriate form factor so that they eciently ll the rectangular chip area.
During oor planning, the following elements should be taken into account:
Number of pads
Location of pads
Number of connections between cells and from cells to pads
Size and shape of cells. Size can be estimated from devices sizes assuming
a lling factor that can be estimated from previous experience.
These oor planning tasks are rather fast and easy and can be done by iterations
until an ecient oor plan is found. Floor planning can start as soon as
schematics are nearly complete. It can be revised when all the schematics are
validated. Then it can be iterated down the hierarchy so that, at each level,
the most ecient plan is used. Finally when each leaf cell is located, layout
can start. This method is ecient since each cell pins are located directly at a
suitable place to connect properly at the upper level of hierarchy. As a result,
nal assembly is usually fast and safe at every level.
68
CHAPTER 10. IMPLEMENTATION 69
10.2 Layout
While the schematic is a symbolic representation that does not take into ac-
count the relationship between components values and sizes and that does not
consider topology, layout does. For instance, a resistor size in the layout de-
pends on its value. This, of course has an impact on the topology.
Another constraint is that the layout is a 2D structure. The third dimension
exists but the designer cannot play much with it.
During the layout phase, the design is usually a set of les in a CAD system.
The dierence with the previous phases lies in the kind of information the les
contain.
10.3 Manufacturing
In IC development, manufacturing is the implementation phase for the whole
product. For many years now, IC processing use steppers for lithography: For
each lithography operation, a dedicated reticle is stepped to cover the entire
wafer area. Complete IC process requires a set of reticles. In order to minimize
the lithography time, the reticle has to be as large as possible. So, a number
of chips have to be assembled in the reticle. These chips can be all identical
or not. Some alignment gures have to be added for the steppers to be able
to position properly with respect to previous process steps. Process Control
Monitoring structures are also added to the reticle to allow checking wafers
electrical properties measurement. For prototyping, most manufacturers allow
multiple level reticles: In one reticle, up to four lithography steps are place.
They are used one after each other, in the right sequence. This increases the
lithography time but reduces the number of reticles. It is generally a good
compromise for prototypes up to pre-production. When volume production
starts, a new set of single layer reticles has to be made.
So, the rst step of manufacturing is assembling the reticle. Then, lay-
out data have to be translated into mask description format after appropriate
transformations such as lling to ensure density in all layers is evenly dis-
tributed, sizing operations to compensate for technology. When the reticle set
is available, the wafers batch can be launched.
After about 12 weeks, wafers are complete. They can be back side grinded to
the desired thickness. Then wafers are sawed into chips that can be assembled
into packages to produce the parts.
Chapter 11
Validation
Circuit design, as a creative activity is intrinsically error prone. Designing is

making choices. Choices are based on assumptions and simplications. This is
why validating choices is mandatory and has to take place as soon as possible.
Validation is a generic word that applies for any design step where choices
are made:
Architectures validations.
Sizing validations.
It also applies for the design tools themselves:
Design kit validation.
And, of course, it applies to the product itself:
Silicon validation.
Hierarchically speaking:
Silicon validation is the top level loop validation.
Architecture and sizing validations take place at every level design loop.
Design kit validation is outside any loop.
Chronologically speaking:
Design kit validation takes place rst..
Architecture and sizing validations take place all along design.
Silicon validation takes place at the end of the rst pass in the develop-
ment loop.
Design kit validation and Architecture validation are addressed in the respec-
tive sections. In this chapter, we will introduce the loops validation phases at
properly speaking:
Sizing validation.
70
CHAPTER 11. VALIDATION 71
Layout validation.
Silicon validation.
If validation fails, a debug or troubleshooting phase is required to x the issues.

These phases will be detailed in the next four chapters.
11.1 Sizing validation

In fact, when a design is sized, everything is ready for simulating it. So, sizing
validation also validates architecture and is in fact some sort of a complete
design verication. Sizing validation is a three steps process:
Verication: Running typical simulations in order to check functionality

and performance.
Characterization: Running a full set of simulations trough voltage, tem-

perature, process and mismatch.
Debug: Identifying and xing issues if any.
11.1.1 Verication
Validating cell functionality means checking that the cell can be set to operate
in all the functional modes and that functionality and performances are correct
in all the modes. This is normally done at room temperature, nominal supply
and typical process.
Prior to design verication, the checklist below can be used to run simple
simulation that can lead to eventually modify the cell. This can save iterations
in the design loop.
Verication is done with the help of a simulator. If verication fails, the
origin of failure has to be found and corrected, and then verication has do be
done again.
11.1.2 Characterization
The specication contains a list of items that dene cell performances. Charac-
terizing is checking all the specied characteristics, in all the possible environ-
ment conditions and in any process case and checking the impact of mismatch
through Monte-Carlo simulation. Most of these performances can be checked
by simulation, with some limitations and exceptions.
Limitations mainly result from non modeled phenomenons and limited

model accuracy.
Exceptions are mainly caused by accuracy concerns, by non applicable

or non existing analysis types.
For each specication item, a test cell should be created. The test cell is a
schematic that instances the cell to test, together with stimuli and external
components. The goal is to put the cell in the conditions the specication
denes for the item to be measured. The cell can then be simulated and the
performance can be measured and compared to the specied limits. Checking

the entire specication usually requires a set of test cells with dierent setups,
dierent stimuli or dierent external components. For each test cell, several
types of analysis can be carried out depending on specication item to check.
In addition, simulation allows environment conditions such as temperature and
supply voltage, but also process case to be changed. Monte-Carlo simulations
are also required to check the inuence of mismatches.
Conclusion The result of a characterization can be positive or negative:
If the cell complies with its specication, the design can continue with
another cell. This situation shows that the design process has converged.
It means that the method has been used successfully.
If the specication is not met, iterations are required on sizing or on

architecture. If this occurs at the rst iteration, and especially if only a
slight change in sizing can cure the issue, the situation is less that ideal
but not too critical.
An unmet specication after a large number of iterations indicates that some-

thing went wrong in the design process.
11.1.3 Design Debug

If a specication is not met, a debug process must be started to nd the root
cause and nd a solution. This process is detailed in dedicated chapter: Sizing
Validation.
11.2 Layout validation

In modern tools, Layout is usually a safe design phase as tools permanently
check the consistency between the sized schematics and the layout. This is a
kind of validation. However, a global validation is required to manage a number
of possible issues:
Hierarchy issues.
Parasitic components.
11.2.1 Hierarchy issues

11.2.2 Parasitic components
11.2.3 Layout debug
If something is wrong with the layout, just as for design, a debug session is
required. It is detailed in a dedicated chapter: Layout Validation.
11.3 Silicon validation

Validation is not only a binary test to know whether the design complies with
its specication or not. If it does not comply, the reason should be identied
so as to be xed. This phase can be called troubleshooting or debugging.
Validating the silicon samples is a critical phase. Accuracy and exhaustiveness
of this work conditions the future life of the product. Validating a piece of
silicon is also a dicult task more several reasons:
One goal is to nd what's wrong and the designer hopes and wants to
show that his design is good.
Another goal is to check that everything works as expected, not only that
globally the circuit works.
Another goal is to evaluate margins but the samples are what they are
and it is not possible to vary the process parameters or the matching
data on samples.
When validation starts, not only silicon status is unknown but also the
test board status is unknown and the control software if any is also in an
unknown status.
In order for the silicon validation to be carried out eciently, a silicon validation
phase is required. It is detailed in a dedicated chapter: Silicon Validation.
Chapter 12
Sizing validation
Design characterization is probably the easiest design step even though it may
require a signicant time. This is mainly because a well dened method applies.
Characterization requires the full set of simulation using the test cells to be done
for all the possible combinations of external variables. Since external variables
are independent from each other and since they can vary continuously, the
number of combinations is innite. So, true characterization is an impossible
task. Fortunately, some assumptions that proved to be reasonably true make
this task achievable. Variables that can inuence the performances of a circuit
are mainly of two types:
Environment conditions
Process cases
12.1 Environment conditions

There are mainly two environment conditions:
Temperature
Supply voltage
Supply voltage can be a vector variable since there might be several supplies
for a cell. Then, one supply might be maximal while another one is minimal.
However, since most cells characteristics exhibit a monotonic or sometimes
quadratic behavior with environment variables, characterization can be simpli-
ed by considering only 3 possible values for the environment variables:
Minimal
Typical
Maximal
Then, the number of combinations is only 3 to the power number of variables.

For only temperature and one supply to be considered, the full set of simulation
should be done 9 times.
74
CHAPTER 12. SIZING VALIDATION 75
12.2 Process cases

The dierent components in a process are manufactured step by step along
the process. As a result, characteristics of dierent components are partly
independent from each other. As an example, if two dierent resistor types
are used, one for low values, one for high values, sheet resistance of each type
resulting from a dierent process step is independent from the other one. One
type might be at maximum while the other one might be at minimum. This
explains why all independent component types should be considered indepen-
dent during characterization. Again, considering only minimal, typical and
maximal values can be considered for process parameters. Then, the number
of combinations is 3 to the power number of variables. Usually, there are 5 to
7 key parameters in a process, so this results only in 243 to 2187 possibilities.
12.2.1 Worst case analysis

Worst case analysis is performed by combining the process cases number with
the environment cases. With the simple example considered above, combining
the environment conditions and the process cases results in a respectable 2187
to 19683 number of possible cases. And this has to be done for all specication
items. For a cell with only 10 specied items, the number of simulations to
be done is 21870 to 196830. . . Unfortunately, the worst case being potentially
dierent for each item, it is a large amount of results to be scanned to nd the
worst values.
12.2.2 Corner analysis

This is what the so called corner analysis available in most tools does. Even
though it is fully automated, the simulation time and the result les size can
be very large for a signicant cell. This is basically why corner analysis is only
suitable for small cells.
Monotonic behavior assumption

For larger cells, an assumption can be made: The sign of the partial derivatives
of a given circuit characteristics with respect to a particular variable does not
depend on the other variables.
In other words if a particular characteristics value is plotted versus a partic-
ular parameter, the curve is monotonic. The average slope can be positive or
negative. When the other variables are changed and the same characteristics
is plotted again, the curves slopes can have dierent values but the sign does
not change. This result has proved to be true most of the time and when it is
not true, the slopes are very low. This property can be used to dene another
characterization method:
Each process and environment variable is swept from minimal through

typical to maximal while all the others are set to typical, the full set of
simulation is run and the cell characteristics are recorded together with
the parameters set.
The number of characterization is only 3 times the overall number of parame-

ters.
Then, for each cell characteristics, two other simulations are done, one
with the set of all the parameters that pushes the characteristics to max-
imal, one with the set of parameters that pulls the characteristics to
minimal. These two sets of parameters are usually dierent for each cell
characteristics. This is why this is not done on the full set of simulation
but individually.
Within the validity of the assumptions this method is based on, it brings ab-
solute worst values that should occur very rarely.
If the cell meets the specication even in this absolute worst case, char-
acterization may stop. The cell is probably too robust, but making it less
robust would require additional work which is denitely not worth the
money except if silicon area can be reduced signicantly!
If the specication is not met in the absolute worst case, the question is:
How probable is this case?
Evaluating the probability of occurrence requires considering separately the

random process parameters and the deterministic environment variables.
For any process variable, maximal and minimal values for each cell charac-
teristics can be considered as +3 sigma and -3 sigma values, so sigma on each
performance value for each variable can be evaluated.
Then, overall sigma for each cell specied item can be computed as the
square root of the sum of squares of all individual sigma values.
It is then possible to nd the limits for process dependency at any number
of sigma for each cell characteristics.
Then, inuence of environment variables should be considered:
A simple method is to assume that performance variation with temperature
or supply voltage does not depend on process case. Then, simulating environ-
ment variations in a typical process case gives voltage and temperature slopes.
Combining these slopes with process worst cases gives a good estimate of the
worst values for each cell performance.
A more accurate method is simulating variations with environment variables
in the identied worst process cases. This shows how slopes depend on process
and can then be used to calculate more accurate worst values.
It must be stated that so far, only structural sensitivities have been con-
sidered. Inuence of mismatch has not been taken into account. This requires
another approach: Monte-Carlo analysis.
12.3 Monte-Carlo analysis

Monte-Carlo analysis is another approach that can be used for characterizing
a cell if data are available. Usually parameters have process and mismatch
variations. If only process variations are considered, results are close to the
corner analysis results or monotonic behavior assumption. If mismatch is taken
into account, this method brings valuable results that no other method can
bring.
12.3.1 Monte Carlo analysis principle

This method consists in running a reasonable number of simulations with sta-
tistical parameters, for process, mismatch or both. This analysis provides mean
and standard deviation for each simulated cell performance.
Inuence of environment variables must be considered in a similar way as for
the monotonic behavior assumption method, through voltage and temperature
slopes.
Chapter 13
Layout validation
Layout validation is usually divided in three steps:
DRC: Design Rules Checking. Verifying that layout complies to design

rules in terms of polygons size, distance, overlap etc...
LVS: Layout Versus Schematic. Verifying that layout implements the

desired schematic.
PEX: Parasitic Extraction. Extracting parasitic Rs and Cs added by

layout.
Layout validation can be thought as a simple task as powerful tools are available
to check the layout versus the schematic and to simulate the layout including
parasitic components. But this idea is not completely true:
Some parasitic components such as substrate coupling are not usually

managed.
Identifying an issue does not give the solution.
78
Chapter 14
Silicon validation
As already stated, silicon validation is a dicult task.
14.0.1 SILICON VALIDATION PLAN

Roughly, silicon validation is a three steps process:
Lab setup verication
Silicon verication
Silicon characterization
General considerations In the lab, only external signals can be measured

easily. Internal signal might be addressed by probing but this requires that
special small pads have been intentionally added. Dedicated test hardware
is highly recommended to make verication easier, even though it costs some
silicon area. The verication time and often the production test time it saves
is worth the money. One point to keep in mind is that measuring internal
signals can aect circuit operation by adding a signicant amount of parasitic
capacitance on the signal line.
Validation plan Basically the plan lists all the measurements to be per-
formed with associated conditions. The goal is ideally to check every spec item
from every circuit cell.
14.0.2 LAB SETUP VERIFICATION

A Lab setup consists in hardware and software that are intended to interface the
piece of silicon with the external world. The hardware is mainly a board with a
socket and a set of power supplies and measurement instruments. The software
achieves the interface with the silicon control section if any and can be used
to drive measurement instruments in order to automate the characterization.
Both the board and the software have to be validated before they can be linked
to any piece of silicon.
79
CHAPTER 14. SILICON VALIDATION 80
Board validation Validating the board includes items like:
Check that supplies and signals are connected to the right pin of the
socket
Check in particular that the level shifters on the digital signals, if

any, operate properly
Check that current consumption is zero when no circuit is present in the

socket.
Check parasitic capacitance values on the dierent pins.
Software validation
14.0.3 SILICON VERIFICATION

Silicon diers from simulated schematic:
Simulation models are only models, some eects are not modeled.
Layout verication tools do not have 100% detection.
Silicon includes non-modeled parasitic components.
Silicon suers from manufacturing issues, so yield below 100%.
Prototypes can also suer from an improper bonding. . .
The board used for verication may also be the origin of some issues. . .
Silicon verication can start only when the lab setup has been veried.
1. Setup the supplies: Voltage and current limitation 30% above the ex-
pected consumption.
2. Turn all the supplies o.
3. Insert a part in the socket.
4. Turn all the supplies on.
5. Check current consumption.
6. Start measurements.
A good practice is to write a day to day validation report summarizing the

measurements carried out, the conditions, the equipment, the results, the is-
sues.
If something goes wrong during the measurements, troubleshooting ??must
take place.
14.0.4 SILICON CHARACTERIZATION

After the silicon is validated i.e. all functions and performance are checked
in nominal conditions, a characterization phase can take place so as to check
statistically and through operating conditions. A good start point is to charac-
terize extensively 10 parts though the full supply voltage range and temperature
range. Ideally, parts from dierent process corners should be characterized.
Chapter 15
Troubleshooting
The general method for troubleshooting divides in six steps. Eventually, a

seventh step is added if relevant:
1. Describe the problem
2. Identify root cause
3. List possible solutions
4. Choose solution
5. Implement solution
6. Validate solution
7. [Prevent recurrence]
This method applies in every situation where an issue occurs. During the
development of an analog IC, this can take place mainly during the design phase
and during the validation phase. A design issue is generally a specication
item that is not met. A validation issue is generally an unexpected dierence
between simulation and measurement.
15.1 Describe the problem

This can seem obvious but dening accurately and without ambiguity a prob-
lem and specifying properly the conditions of occurrence if applicable is a dif-
cult task that requires method and training. A powerful method is to answer
the standard questions:
What? What does not work as expected?
When? When does the issue occur, in what conditions?
How? How can one see that something is wrong? How often does the
issue occur?
Very often, answering the initial list of questions brings additional questions.
81
CHAPTER 15. TROUBLESHOOTING 82
15.2 Identify root cause

This is probably the most dicult step in troubleshooting. Of course, possible
root causes depend on the addressed issue. However, there are several standard
cause classes:
Tools
Environment
Principle
Implementation
Failure
Interaction
15.2.1 Tools
The issue can be real on the circuit under evaluation or can result from the
tools that are used for the evaluation. Tools depend on the phase in progress.
They are simulators and models during the design phase, they are measure-
ment instruments during prototypes validation. Tools must be questioned and
checked to make sure that the issue is real. Using another simulator or another
simulation technique, using another measurement instrument can help.
15.2.2 Environment
During design, design kit can be updated resulting in changes in the circuit be-
havior. The change does not necessarily result from a design change. However,
normally the new design kit is supposed to be more accurate and the circuit
must be change in order to work properly in the new environment.
During prototypes evaluation, some oscillations may not result from the
circuit but from a cellphone or from another signal source in the surroundings.
A special subclass of environment items are parasitic elements. They should
be considered during design and tools should take them into account but this
is not always the case. In the lab, sockets parasitic elements can impact the
circuit behavior.
15.2.3 Principle
The issue can result from the principle that has been used for designing the
circuit. During design, this should normally occur only at early stages. It this
occurs during validation, it indicates that something really went wrong in the
development process.
15.2.4 Implementation
The issue can result from a bad implementation of a good principle.
15.2.5 Failure
Issue can result from a component failure or from a design failure.
15.2.6 Interaction
A dicult situation is when the issue does not result from a simple cause but
from an interaction between two or more causes.
15.3 Design debug

When one or more specication items are not met
15.4 Silicon debug

In case something does not work as expected in the lab, either during veri-
cation or during characterization the designer must start a troubleshooting or
debugging phase. Globally, the approach is based on the general seven steps
problem solving method:
1. Dene the problem
2. Find root cause
3. List possible solutions
4. Choose one solution
5. Implement solution
6. Validate solution
7. Prevent recurrence
Of course, when applied to silicon debugging, the general method is adapted

to the particular constraints of that eld.
15.4.1 Dene the problem

Steps are:
1. List issues.
2. For each issue, check consistency and nd boundaries.
a) Run the experiment again in order to avoid spurious phenomenons.
b) Run the same experiment with a couple other parts in order to avoid
a part artifact.
c) Run the experiment with another measurement instrument in order

to avoid an instrument artifact.
d) Vary supply voltage and temperature or other signal parameters in

order to nd a possible region of correct operation.
Each issue should be summarized in a sentence describing the undesired be-

havior and the conditions of occurrence.
15.4.2 Find root cause

One root cause has to be found for each issue. A single cause may be the root
for several issues. The method for each issue is:
1. Imagine scenarios that could lead to the issue.
2. Check scenarios
a) Force the circuit in conditions (temperature, voltage, frequency...)

where a given scenario predicts that something should change and
check prediction.
b) Use the on chip test circuitry in order to identify the faulty block.
c) Use simulations to enforce assumed cause and compare with mea-

surements (circuit signature)
When two or three signatures comply with expectations from a given scenario,
it is a good candidate. The investigations to nd root cause may show addi-
tional issues. These should be considered as well but as separate issues that
must be analyzed. Only careful analysis can dene whether dierent issues
are related to the same root cause. A complex problem should never be over-
simplied.
Once a root cause is identied, it should be validated using all the possible
tools and methods. Simulation is a powerful tool but some techniques such as
FIB (Focused Ion Beam) allow in place circuit modications by cutting wires
and creating new connections.
15.4.3 List possible solutions

Just like for design, the right solution is the best choice in a list. Depending on
the context (metal x or full re-spin), the list of possible solutions may vary.
Usually, the more expensive the solution, the more powerful it is.
15.4.4 Choose a solution and implement it

The solution must be validated extensively through simulation. A design
change leads to a new design with ideally the expected eect on the problem.
But the new design may also exhibit some undesired behavior or performance
that could be worse than the original design!
15.4.5 Validate the solution

Full silicon validation is required again to check that the original problem is
xed but also that the x did not create a new issue nor it did break something
that worked ne before.
Part II
Analog IC design
85
Chapter 16
Introduction
Before going further, let's answer the following question:
What is analog electronics?
16.1 Analog electronics

For many electronic engineers, it is the nightmare branch of electronics...
For others it is what they like, at work and often at home too...
Often, denition of analog electronics is very personal, very aective.
For the author, and for the sake of clarity:
Analog electronics is the branch of electronics in which electrical signals

representing data can have an a priori unlimited number of signicant values.
In contrast digital electronics is the branch of electronics in which electrical

signals representing data have a limited number of signicant values.
In both branches, data are represented by electrical signals
In both branches, electrical signals have an innite number of possible

values
The dierence lies in the signicant values:
All possible values are signicant for analog electronics

Only some values are signicant for digital electronics
What are the consequences of this denition of analog electronics?
16.2 Consequences
In electronic circuits, electrical signals interact with components and generate
other electrical signals. Let's simplify a bit and consider a simple circuit with
just one input and one output. The output signal characteristics depend on:
The input signal (fortunately).
86
The circuit characteristics.
The circuit characteristics divide in two groups:
The desired characteristics. The circuit is intended to perform some

modications to the signal. (otherwise it is useless!)
The spurious characteristics. The circuit has inevitably some non ideal
characteristics and it introduces undesired modications. It may also add
parasitic signals to the output signal.
It is then very dicult and sometimes impossible for an analog circuit to know
whether a change in the output signal results from a change in the input signal
or from a change in the circuit characteristics.
If an analog circuit is properly designed and implemented, the output signal
depends mainly on the input signal, the circuit itself introduces limited signal
distortions and adds minor parasitic.
The circuit must then be designed and implemented in such a way that
changes in circuit parameters have a minor impact on the output signal and
that noise and parasitic signals are kept to an acceptable level.
As a consequence, the inuence of circuit parameters on the output signal
must be analyzed carefully and circuit must be optimized until the target spec-
ication is met whatever the parameters inside their specied tolerances and
whatever the environment conditions within specications.
Chapter 17
Basic analog IC design elements
As already stated, it is necessary for designers to know about the behavior and
properties of components and basic circuits and about techniques and particu-
lar aspects of implementation. This is why, before going further these elements
are grouped together in this part for those who might not be completely fa-
miliar with. Analog IC design is a branch of analog design. The dierence
comes from the integration that has many practical consequences. In turn,
these particularities do not allow direct integration of a board schematic and
then have an impact on the design:
The production cost of an IC is linked to the circuit area, not to the num-
ber of components. The larger the circuit, the higher the cost whatever
the contents.
NRE costs for developing an IC are much higher than for developing a
PCB. Delays between a design decision and feedback are much longer
than for a breadboard.
Absolute values tolerances of components are poor, only matching can

be reasonably good.
Passive components sizes are proportional to their value.
The cost of a 100 pF capacitor in an IC is about the same as 1500 gates

in a 0.18 µm CMOS process.
Changing a component value or a connection requires weeks to months

and costs tens of thousand dollars.
All these dierences have made analog IC design a risky activity, even more
risky than analog board design. The try and x method is hardly usable.
17.1 Integrated components

Analog integrated circuits include both active devices and passive devices con-
nected together in order to achieve their functionality. Integrated components
as simple objects are dened by their material, shape and size.
Material: Mainly silicon, oxide and aluminum.
88
CHAPTER 17. BASIC ANALOG IC DESIGN ELEMENTS 89
Material is either what is available in the process or in some cases is

added especially to the process for the particular purpose of creating
the component.
Shape: Depends on component type but most components are build from
a number rectangles.
Shape is usually dened by photo-lithography, etching and some

other physical or chemical technique.
Size: Depends on component value or parameter.
Size is dened together with shape by the same techniques.
The integrated components will be analyzed in terms of their characteristics

and behavior, not in terms of technology except when a direct link exists be-
tween process and characteristics.
17.2 Devices
Integrated components belong to three families:
Active devices
Passive devices
Parasitic devices
Availability of particular devices depends on process and options.
17.2.1 Active devices

These devices are bipolar transistors, MOS transistors and various diodes.
17.2.2 Passive devices

These devices are resistors, capacitors and inductors.
17.2.3 Parasitic devices

These devices include parasitic capacitors and resistors, isolation diodes, par-
asitic MOS, parasitic bipolar transistors and parasitic thyristors.
Chapter 18
Bipolar transistors
Bipolar transistors were the rst transistors to be created in 1948 by Bardeen,

Brattain and Schockley at Bell Labs.
Bipolar transistors behavior is reasonably well described by the so called
Gummel and Poon model. This model is suitable for calculation and for
computation. The designer can use it, at least in a simplied version, for sizing
a circuit and simulators use it extensively.
18.1 Symbols and notation

Bipolar transistors exist in two polarities, NPN and PNP.
Bipolar transistors have three pins: emitter, base and collector.
Pins are identied by a letter, E for emitter, B for base and C for collector.
Currents in the three pins are identied by the pin letter as IE, IB and IC.
Voltages are identied by the two pins letters as VBE, VBC, VCE.
Figure 18.1: Bipolar transistors symbols
With the gured convention on voltages and currents:
Voltages are positive for NPNs, negative for PNPs.
Base and collector currents are positive for NPNs, negative for PNPs.
90
CHAPTER 18. BIPOLAR TRANSISTORS 91
Emitter currents are negative for NPNs, positive for PNPs.
18.1.0.1 Note:
In the symbols shown here, emitter is bottom connection for the NPN and top
connection for the PNP. This is the standard convention for drawing schematics
with the positive supply at the top and the negative supply at the bottom.
18.2 Layout
18.3 Cross sections
In integrated circuits, transistors have to be isolated from each other. Starting
from this constraint, several transistor structures can be implemented. They
will be detailed hereafter. Basically, transistors are named:
Vertical if the emitter current ows perpendicular to the die surface
Lateral if the emitter current ows parallel to the die surface.
In all the gures below, only the nal and simplied transistor structure is
shown, no details are given on process.
18.3.1 Vertical NPN

In the classic bipolar process, the most standard transistor is the vertical NPN
on a P type substrate.
Figure 18.2: Vertical NPN Cross-section
The actual transistors structure is more complex, mainly in order to reduce

the parasitic series resistance on collector and base by adding higher doping
regions between the access on top and the active region inside the transistor.
18.3.2 Lateral PNP

In the classic bipolar process, PNPs cannot be implemented as both vertical
and isolated on P substrate. Isolated PNPs are lateral.
For eciency reasons, actual transistors dier a bit from this simplied
drawing. Usually, collector P area is given a ring shape surrounding the emitter.
In order to prevent the parasitic PMOS to turn on, a good practice is to have
the emitter metal connection overlapping the N base region between emitter
and collector. In order to achieve the best possible current gain, the emitter
should be highly doped. If some other P layers are available and compatible in
size and depth, the can be added to the emitter region to improve the lateral
PNP current gain.
Figure 18.3: Lateral PNP Cross-section
18.3.3 Substrate PNP

In the classic bipolar process, vertical PNPs cannot be isolated on a P substrate,
they share the collector in common.
Figure 18.4: Substrate PNP Cross-section
18.3.4 Vertical PNP

Implementing a vertical PNP could be thought just as the dual of the vertical
NPN implementation. It is not usually the case as most of the time, NPNs are
required as well. So implementing a vertical PNP on a P substrate requires
one more isolating N well. In addition, the three active layers are obviously
not the same as for the NPN. As a result, such a process is more complex and
more expensive than the simpler classic process.
Figure 18.5: Vertical PNP (isolated) Cross-section
Just as for vertical NPNs, actual transistors are more complex with added
regions mainly intended to reduce parasitic series resistance.
18.3.5 Bipolar transistors in MOS and BiCMOS process

Without special process options, only lateral and substrate PNPs are available
in CMOS processes. With appropriate options, CMOS processes can become
true BiCMOS processes with good performance bipolar transistors.
18.3.6 Some simple considerations from the vertical

transistors cross sections
The vertical bipolar transistor base is very thin. The emitter to collector dis-
tance is very small, smaller the the drain to source distance in a MOS from the
same generation. Base thickness has been below 0.1 µm for more than 20 years.
This has been possible because base thickness is not dened by lithography but
by the dierence between two junction depths. And this is also allowed even
with a signicant breakdown voltage since only the base collector is reverse bi-
ased and the depleted region can extend in the collector allowing high voltages
even if the base is this.
Another consideration is related to current density. As the current ows
vertically, it uses all the emitter area which can be made signicant. In a MOS
transistor, the current ows horizontally in a very thin inverted layer. Achieving
a signicant area for the current to ow implies a very large transistor.
18.4 Model equations

Equations are written for NPNs. For PNPs, voltages and currents are multi-
plied by -1. Equations apply for the transistor whatever its structure
18.4.1 Basic equations

First, let's dene:
k·T
VT =
q
Where k = 1.39 · 10−23 is Boltzmann's constant, q = 1.6 · 10−19 is the
electron's charge in Coulomb and T is the absolute temperature in Kelvin. VT
is known as the thermodynamic voltage. At room temperature, V T ' 25 mV
18.4.1.1 Collector and base currents
The collector current that actually ows from collector to emitter depends on
VBE and VBC the following way:

V BE V BC
ICbasic = IS · exp − exp
NF · V T NR · V T
For the base current that actually ows from base to emitter, expression is:
" #
V BE V BC

exp N F ·V T −1 exp N R·V T −1
IB = IS · −
BF BR
As a result, emitter current is the sum of collector current and base current.
In order to satisfy the Kirchho Current Law, emitter current is negative.
IE = − (IC + IB)
It is fundamental to see that, in usual operating conditions, collector current
and base current result from base-emitter voltage. As a result, the current gain
usually noted β is an indirect eect.
These equations show ve model parameters:
IS, the saturation current
NF, the forward surface emission coecient
NR, the reverse surface emission coecient
BF, the forward current gain
BR, the reverse current gain
Note on NF and NR For vertical transistors, the NF and NR parameters

are close to 1. For lateral transistors, NF and NR are larger and cause a non
ideal behavior that make these transistors unsuitable to design band-gaps.
Example: With this basic model, and with the following parameter values:
IS = 10 −16
BF = 100
BR = 1
NF = 1
NR = 1
We can plot the following curves:
IC versus VCE for various VBE values
Figure 18.6: IC vs. VCE (VBE) Basic
This graph shows that the transistor operates like a current source when
VBC is negative enough i.e. when VCE is signicantly larger than VBE. When
VCE is smaller than VBE, the transistor enters in the so called saturation
region.
IC/IB versus VCE
Figure 18.7: IC/IB vs. VCE Basic
This graph shows that current gain of basic model is fairly constant and
equal to parameter BF outside the saturation region and drops as the transistor
goes deeper into saturation.
IC/IB versus IC
Figure 18.8: IC/IB vs. IC Basic
This graph shows that current gain of basic model is fairly constant and
equal to parameter BF over a wide collector current range.
The basis static model describes a somewhat ideal transistor but already
includes the saturation eect.
18.4.2 Early eect

This eect describes the output resistance. The collector current is primarily
dened by the base-emitter voltage but also depends on the collector-base
voltage. The equation is shaped to show an Early factor and the basic collector
current.

V BC V BE
ICEarly = ICbasic · 1 − − = ICbasic · KEarly
V AF V AR
This equation adds two model parameters:
VAF, the forward Early voltage
VAR the reverse Early voltage
Adding the following parameter values:
V AF = 20
V AR = 5
The previous curves change a bit:
IC versus VCE for various VBE values
Figure 18.9: IC vs. VCE (VBE) Early
Now our transistor shows a nite output resistance
IC/IB versus VCE

Figure 18.10: IC/IB vs VCE Early
Now, current gain depends on VCE, even outside the saturation region.
IC/IB versus IC
Figure 18.11: IC/IB vs. IC Early
Now, current gain changes slightly with collector current but this is only
due to the change in VBE.
18.4.3 High injection

This eect describes the current gain reduction at high currents. The equation
is shaped to show an injection factor and the basic collector current.
ICinjection = ICbasic. = ICbasic.Kinjection
This equation adds two model parameters:
IKF, the forward roll-o current
IKR the reverse roll-o current
Removing VAF and VAR to cancel Early eect and adding the following pa-
rameter value:
IKF = 2 · 10 −3
The previous curves change again:
1. IC versus VCE for various VBE values
2. IC/IB versus VCE
3. IC/IB versus IC
18.4.4 Combined Early and high injection eects

The actual transistor exhibits both the Early eect and the high injection
phenomenons. The factors simply multiply by each other.
IC = ICbasic · KEarly · Kinjection
Keeping parameter:
IKF = 2 · 10 −3
And restoring the parameter values:
V AF = 20
V AR = 5
The previous curves change again:
1. IC versus VCE for various VBE values
2. IC/IB versus VCE
3. IC/IB versus IC
18.4.5 Leakage currents

These eects describe the current gain reduction at low currents.
18.4.6 Access resistances

Inevitably, parasitic resistances exist on the three pins. These resistances re-
sult from connections and semiconductor material between access points and
internal region where the transistor eect takes place.
Usually, emitter resistance is low as emitter is a thin area with direct

access to the emitter connection.
Base resistance is usually signicant as for achieving a reasonable current

gain, base is made thin and connection is located quite far from active
area.
Collector resistance can be signicant as the connection is located quite

far from active area and collector is made from lightly doped, high resis-
tivity material to achieve a reasonable current gain.
The three resistances, as made from semiconductor material are subject to

temperature variations.
18.4.7 Capacitances
A junction capacitance results from two terms:
Transition capacitance
This capacitance exists in both forward and reverse biasing. It is the

depleted region capacitance. It depends on the voltage. In an IC, bipolar
transistors have three junctions:
Base-emitter
Base-collector
Collector substrate or base-substrate
Diusion capacitance
This capacitance exists only in forward biasing. It results from the mi-
nority carriers stored in the junction. It depends on the current. Only
forward biased junctions exhibit diusion capacitance. Normally, only
the Base-Emitter junction is forward biased but in saturation, the Base-
Collector is forward biased too.
18.4.7.1 Base-Emitter junction transition capacitance
If V BE ≤ F C · V JE
1
CT E = CJE ·
V BE M JE

1− V JE
If V BE > F C · V JE

1 V BE − F C · V JE
CT E = CJE · M JE
· 1 + M JE ·
(1 − F C) V JE · (1 − F C)
18.4.7.2 Base-Collector junction transition capacitance
If V BC ≤ F C · V JC
1
CT C = CJC ·
V BC M JC

1− V JC
If V BC > F C · V JC

1 V BC − F C · V JC
CT C = CJC · M JC
· 1 + M JC ·
(1 − F C) V JC · (1 − F C)
18.4.7.3 Collector-Substrate junction transition capacitance
If V SC ≤ F C · V JS
1
CT S = CJS ·
V SC M JS

1− V JS
If V SC > F C · V JS

1 V SC − F C · V JS
CT S = CJS · M JS
· 1 + M JS ·
(1 − F C) V JS · (1 − F C)
18.4.7.4 Overall Base-Emitter capacitance
The following graph shows the transition and diusion capacitance values ver-
sus the Base-Emitter voltage. At negative VBE values, only transition capac-
itance exists and varies. Above V BE = F C · V JE , CTE variation changes.
When VBE is sucient, collector current becomes signicant, CDE increases
exponentially and quickly becomes the dominant term.
Figure 18.12: CBE terms vs. VBE

Now we can plot the capacitance values versus collector current:
Figure 18.13: CBE terms vs. IC
18.4.8 Base resistance modulation

Emitter and collector access resistances can be considered as independent from
current. But base access resistance shows variations with current.
18.4.9 Temperature eects

The transistor temperature aects the operation. The temperature eects are
modeled as follows:
18.4.9.1 Saturation currents
18.4.9.2 Current gain
18.4.9.3 Bandgap energy
18.4.10 Noise
Noise is modeled as noise voltage or current sources associated to the transistor
various noisy elements
Figure 18.14:
18.4.10.1 Resistances
18.4.10.2 Collector current
18.4.10.3 Base current
18.4.11 Isolation diode

At properly speaking, the isolation diode is not completely included in the
original SPICE model.
The parasitic capacitance is modeled.
The parasitic forward current is not modeled.
The isolation diode is connected between collector and substrate which

is correct for vertical transistors, not for lateral.
More recent derivatives include this feature through an additional parameter

ISS and topology variants in the model declaration. Most design kits now
manage the isolation diode through sub-circuit denitions (or do not manage
it at all !).
18.4.12 Parasitic transistor

In integrated circuits, bipolar transistors have a fourth pin, named Substrate
that is common to all the transistors. Each transistor exhibits a parasitic
diode to the substrate. For a vertical NPN in a classic P-substrate process,
each transistor's diode has cathode connected to collector and common anode
connected to substrate. This diode is close to the transistor base-collector
junction. As such, it creates a parasitic transistor:
When the NPN is driven into saturation, the parasitic transistor turns on
and draws current to the substrate.
This eect is not included in the transistor model but can be modeled by a
sub-circuit including two transistors, one for the desired transistor, one for the
parasitic. Some design kits include this but some don't.
18.4.13 Matching
In a bipolar transistor, there are mainly four parameters that contribute to
mismatch:
The saturation current IS
The emitter resistance RE
The current gain BF
The low current non ideal saturation current ISE
Base access resistance RB and Early voltage VAF are strongly correlated to
current gain:
The higher the gain, the higher the base resistance and the lower the
Early voltage.
18.4.13.1 Oset voltage
Dierential ampliers oset voltage is directly generated by VBE mismatch.

At medium current that is to say in a region when leakage is negligible
and where voltage drop in RE is negligible, only IS mismatch is signicant.
This region is where the best VBE matching can be reached. Value depends
on transistor size but standard deviation on VBE mismatch can be 200 µV .
At low currents, ISE mismatch causes VBE mismatch to increase. At higher
currents, RE mismatch becomes dominant and increases VBE mismatch.
18.4.13.2 Oset current
Dierential ampliers oset current is directly generated by β mismatch. Stan-

dard deviation on β mismatch can be 3%.
18.5 Simplied model

A very common situation is:
V BC −V T
IC < IKF
In this case, expressions simplify leading to the simplied model that is useful
for sizing transistors and choosing operating point.

V BE
ICbasic ' IS · exp
VT
ICbasic
IB '
BF

V BC
IC = ICbasic · 1 −
V AF
18.6 Small signal model

The model as described so far, even the simplied version are non linear. Nowa-
days with computers and simulation we can deal with non linear computation
but in the past it was much more painful. The small signal model is a linearized
model that is only valid for small variations around the operating point. This
model is helpful as it allows calculation and helps sizing.
18.6.1 Transconductance
For the bipolar transistor, current owing from collector to emitter depends on
voltage between base and emitter.
Transconductance46.4 can be dened as:
gm = ∂IC
∂V BE = 1
VT · IS · exp V BE
VT

= IC
VT
For a bipolar transistor, transconductance depends only on collector bias cur-

rent and on temperature. No process parameter inuences the bipolar transcon-
ductance. There is just a restriction on the current range for this to be true.
Collector current must be larger than leakages and it must be low enough
so that degeneration by emitter resistance is negligible. Usually, for a given
transistor, this is true over more than six decades of collector current.
18.6.2 Input resistance

Input resistance is dened by vBE and iB as:
rBE = ∂vBE
∂iB = β
gm = β·V T
IC
18.6.3 Output resistance

Output resistance is dened by vCE and iC as:
∂vCE ∂vCB ∂vBE

rO = = +
∂iC ∂iC ∂iC
Since vBE is kept constant by assumption,
∂vCE ∂vCB 1 V AF V AF
rO = = = ∂iC
= =
∂iC ∂iC ∂vCB
IC IC
18.6.4 Input capacitance

Input capacitance in the normal, forward, non saturated operating mode is
the sum of the transition and the diusion capacitance. As the Base-Emitter
junction is forward biased, an acceptable approximation for the transition ca-
pacitance is:
CT E ' 2 · CJE
The diusion capacitance is:
IC
CDE = T F ·
VT
Then:
IC
CBE = CT E + CDE = 2 · CJE + T F ·
VT
18.6.5 Output capacitance

Output capacitance is mainly the reverse biased collector substrate capacitance.
An acceptable approximation in this case is:
CJS
CCS '
2
18.6.6 Input cuto frequencies

Two cuto frequencies have to be dened. The current gain cuto and the
transconductance cuto.
18.6.6.1 Current gain cuto frequency
When the transistor is current driven, its internal vBE is dened by the control
impedance made from rBE in parallel with cBE. This impedance, when driven
with an AC current implements a low-pass transfer function. Cuto frequency
is dened as:
1
f0 =
2 · π · rBE · cBE
18.6.6.2 Transconductance cuto frequency
When the transistor is voltage driven, its internal vBE is dened by the at-
tenuator built from the base access resistance RB and the control impedance
built from rBE and cBE. This input divider achieves a DC attenuation and a
low pass transfer function. Cuto frequency is dened as:
1
f0 = rBE·RB
2·π· rBE+RB · cBE
As usually rBE RB cuto frequency can be approximated as:
1
f0 =
2 · π · RB · cBE
18.6.6.3 Comparison of cuto frequencies
The capacitances dening both cuto frequencies are the same. Comparing
cuto frequencies is then equivalent to comparing the resistances. For the cur-
rent gain cuto, the resistance is rBE while for the transconductance cuto the
resistance is rBE in parallel with RB. Whatever rBE and RB, transconduc-
tance cuto frequency is then higher than current gain cuto. In addition, as
RB is usually lower than rBE, transconductance cuto is usually signicantly
higher than current gain cuto. In high frequencies applications, it is a good
practice to drive the bipolar transistor with a low impedance so as to benet
from the high transconductance frequency.
18.6.7 Output cuto frequency

Whatever the drive mode, output cuto frequency is dened by output impedance
that is equivalent to the load resistance in parallel with transistor output re-
sistance, load capacitance and transistor output capacitance.
18.6.8 Overall cuto

The complete transistor amplifying stage exhibits two rst order cuto fre-
quencies. If one of the two is signicantly lower than the other, the overall
cuto frequency is the lowest of the two. When the two cuto frequencies are
close to each other, the overall cuto is lower than the lowest of the two. 49.6
18.6.9 Miller eect

18.7 Eects of bias current
Let's plot, for a given bipolar transistor model, the current gain and transcon-
ductance cuto frequencies versus collector current.
18.7.1 Current gain cuto

At low currents, cBE is fairly constant and rBE is inversely proportional to the
current. So, cuto frequency is nearly proportional to collector current. Above
a given current, the diusion capacitance exceeds the transition capacitance.
From this current up, cBE is proportional to current and rBE is inversely pro-
portional to the current. So, their product is constant and the cuto frequency
does not change with current.
18.7.2 Transconductance cuto

At low currents, cBE is fairly constant and low so transconductance cuto fre-
quency is maximum. Above a given current, the diusion capacitance exceeds
the transition capacitance. From this current up, cBE is proportional to cur-
rent. As RB is fairly constant and lower than rBE, transconductance cuto
decreases when current increases. However, as already stated, transconduc-
tance cuto frequency is always higher than current gain cuto.
18.8 Eects of geometry

Basically, currents and transition capacitances are proportional to transistor
area, resistances are inversely proportional to transistor area. Current gains
and diusion capacitances do not directly depend on area. They can change
slightly because of second order eects.
This can be understood considering what happens if two identical transis-
tors are connected in parallel.
The collector currents for a given VBE sum up so globally it is doubled.
The parasitic resistances appear connected in parallel. Globally, values

are divided by two.
The transition capacitances are also connected in parallel. Globally, val-

ues are multiplied by two.
Current gain is aected only by the fact that it depends on current and
that current in each individual transistor is half the total current.
Figure 18.15:
Diusion capacitance is proportional to current. If VBE is kept, diusion

capacitance is doubled. If total current is kept, as each transistor operates
at half the current, diusion capacitance is divided by two. But as there
are two in parallel, global diusion capacitance is not changed.
So, when two identical transistors are connected in parallel, for a given collector
current, transconductance cuto frequency is not aected if collector current is
below transition current and it is doubled if collector current is above transition
current.
18.9 Sizing
Sizing is choosing transistor size and bias conditions to reach desired behavior.
Sizing is usually based on small signal model. Block performances can be
expressed as a function of transistor small signal model parameters. In turn,
small signal model parameters can be chosen to achieve block performances.
Then, transistor geometry and bias can be chosen to reach the target small
signal model parameters.
18.10 Basic transistor congurations

The bipolar transistor is basically a transconductor 46.4with nite input and
output resistances. A theoretical transconductor has four pins, A, B, C and
D. Bipolar transistors have only three pins, so, one node has to be common
between control voltage and controlled current. Each of the three pins can be
chosen to be the common pin. This lead to three basic congurations:
Common emitter conguration
Common collector conguration
Common base conguration
18.10.1 Common emitter conguration

In this conguration, input voltage is applied between base and emitter while
output current ows from collector to emitter. Load is connected between
positive supply and collector.
Input resistance is rBE = β · VT

IC + RB
Input capacitance is cBE ' 2 · CJE + T F · IC

VT
Output resistance is rO ' V AF

IC
Output capacitance is cCS ' CJS

2
Transconductance is gm = IC
VT
Figure 18.16:
Figure 18.17:
Miller capacitance is cBC ' CJC

2
Input cuto frequency if driven by a voltage source is f gm ' 1

2·π·RB·cBE
Input cuto frequency if driven by a current source is fβ ' 1

2·π·rBE·cBE
18.10.2 Common collector conguration

In this conguration, input voltage is applied between base and ground and
emitter and ground.
18.10.3 Common base conguration

In this conguration, input voltage is applied between emitter and ground and
positive supply and collector.
18.11 Design kit validation

If model parameters can be read, it is easy to look at the list. This will show
some of the limitations directly. If these parameters are encrypted, a set of
simulations is required to see limitations. The most frequent limitations for
bipolar transistor models are:
Lack of substrate isolation diode current. Only capacitance is modeled.
Lack of parasitic substrate transistor. No substrate current when tran-

sistor is driven into saturation.
Lack of temperature coecients on access resistances.
Improper EG and XTI values resulting from tting. Incorrect VBE vari-
ation with temperature.
Improper MJx values resulting from tting.
18.11.1 Substrate isolation diode current

A simple simulation can show if the substrate isolation diode is modeled. How-
ever several cases must be considered.
Vertical NPN on a P substrate: Sweeping voltage between collector and

substrate from -2V to +2 V and plotting current gives the answer. If a
signicant current appears, the diode current is modeled. If no current
appears, the diode current is not modeled.
Figure 18.18:
Lateral PNP on a P substrate: Sweeping voltage between base and sub-

strate from -2V to +2 V and plotting current gives the answer. If a
signicant current appears, the diode current is modeled. If no current
appears, the diode current is not modeled.
Vertical PNP in a N Well on a P substrate.
18.11.2 Parasitic substrate transistor

A suitable simulation can show if the parasitic transistor is included in the
design kit:
Connect base to a voltage source a couple of volts above substrate voltage.
Draw a suitable current from the emitter.
Sweep collector voltage from 2 volts above base voltage to 1 volt below.
Look at substrate pin current. If current appears when main transis-

tor base-collector junction is forward biased, the parasitic transistor is
modeled.
18.11.3 Access resistances temperature coecients

If model parameters can be read, it is easy to check these coecients. If they
can't, extracting them is a bit tricky since extracting access resistances is a
dicult task.
18.11.4 EG and XTI parameters

18.11.5 MJx parameters
MJx parameters in the models result from tting the capacitance versus reverse
voltage curves of the relevant junctions. This is a simplication since the actual
junctions in a bipolar transistor result in fact of several junctions in parallel.
Each of these junctions has its own CJ, MJ and VJ parameters. As most
junctions are quite abrupt, MJ should be close to 0.5. The dierent junctions
are made from various doping levels so they exhibit various CJ and VJ values.
When all these junctions are considered as a single junction, the CJ, VJ and MJ
parameters cannot model properly the reality. This is often visible by looking
at the MJ parameter if readable. It is often signicantly lower than 0.5. This
is a clue indicating that a complex junction assembly is modeled as a single
junction.
Chapter 19
MOS transistors
For MOS transistors, there are many models but most of them are only usable
by simulators. The only model reasonably usable for calculation is the Schich-
man and Hodges model also called Level 1 model that is no longer in use
practically in simulators. However this model is useful for sizing circuits, this
is why we will analyze it.
19.1 Symbols
MOS transistors exist in two polarities, N channel and P channel also
called NMOS and PMOS.
MOS transistors have four pins; source, gate, drain and bulk.
Pins are identied by a letter, S for source, G for gate, D for drain and B for
bulk. Currents in the four pins are identied by the pin letter as IS, IG, ID and
IB. Voltages are identied by the two pins letters as VGS, VGD, VDS, VBS...
Figure 19.1: NMOS and PMOS symbols
With the gured convention on voltages and currents:
Voltages are positive for NMOS, negative for PMOS.
Drain currents are positive for NMOS, negative for PMOS.
Source currents are negative for NMOS, positive for PMOS.
110
CHAPTER 19. MOS TRANSISTORS 111
19.2 Layout
19.3 Cross sections
In integrated circuits, transistors have to be isolated from each other by junc-
tions. Depending on the substrate polarity, MOS transistors can be imple-
mented directly or in a well. If the substrate is P type, NMOS can be im-
plemented directly. In this case, their bulk is common and connected to the
substrate. PMOS transistors have to be implemented in an N type bulk. So, if
the substrate is P type, an N well is required. If isolated NMOS are required,
their P bulk have to be isolated from each other in and N well. If substrate is
N type, above polarities have to be inverted.
The standard MOS model has only four pins as already mentioned. Sub-
circuits can implement additional pins and related components. Most design
kits do that, mainly after the layout is done. Additional components are usually
diodes.
19.3.1 Standard NMOS on P substrate
Figure 19.2: NMOS on P Substrate
This component has only three pins as Bulk and Substrate are shorted. P
region is gured here as an homogeneous region. However, a P Well is often
used around the MOS to separate Substrate doping from Bulk doping.
19.3.2 Standard isolated PMOS on P substrate
Figure 19.3: PMOS on P Substrate
This component has ve pins, the four standard MOS pins and the Substrate.
19.3.3 Isolated NMOS on P substrate

Figure 19.4: Isolated NMOS on P Substrate
This component has six pins, the four standard MOS pins plus the Well and
the Substrate.
Note: Comparing the isolated NMOS and the vertical NPN cross-sections
shows strong similarities:
Topologies are identical, N, P, N and P regions enclosed in each other.
Well can be used as collector.
Bulk can be used as base.
Source or drain can be used as emitter.Only one is required.
Gate is not used and is usually removed.
When isolated NMOS is available in a process, one can draw a vertical NPN.
Usually, silicon manufacturers include this component in the design kit and
provide model parameters.
Note: The isolated NMOS also provides an isolated PN junction between

Bulk and Drain or Source. When the diode is to be used, attention should be
paid to the Bulk-Well junction that must be reverse or at least zero biased. This
component is not often included in the design kit and silicon manufacturers
usually do not provide model parameters. These parameters normally can
be derived from the NMOS junctions parameters. Anyway it may require
additional designer work for drawing the component and then eventually for
modeling it when available on silicon samples.
19.4 Model equations

Model used here is the old, classic, MOS model from Shichman-Hodges. It is
not suited to take into account short channel eects, but for analog design, it
can give a rst order sizing that is often useful. Other models are not suited
for hand calculation.
19.4.1 Basic equations

First of all, the MOS operates basically in one of two modes or regions:
Ohmic mode when V DS ≤ V GS − V T

Saturated mode when V DS ≥ V GS − V T
Note: The simplied model is intended for use with V GS > V T
19.4.1.1 Dierence with the bipolar transistor regions and

notation
1. For the bipolar transistor, the so called saturation region is the low
VCE region while for the MOS the saturated mode is the high VDS
region.
2. For the bipolar transistor, VT is the thermodynamic voltage while for

the MOS, VT is the threshold voltage, a technological parameter.
In the following basic equations:
W is the MOS width, i.e. the size in a direction perpendicular to the

current ow.
L is the MOS length, i.e. the size in a direction parallel to the current
ow.
VT is the threshold voltage.
KP sometimes noted β is the MOS intrinsic slope, a technological param-

eter that depends on other parameters:
µ · ε0 · εR
KP = β =
T OX
µ is the carriers mobility that depends on Bulk polarity and doping
level.
ε0 is the vacuum permittivity.
εR is the gate oxide dielectric constant.
T OX is the gate oxide thickness.
Note: VT can be made positive or negative. For a NMOS, if VT is positive,

transistor is said enhancement mode or enhanced or normally o and if
VT is negative, transistor is said depletion mode or depleted or normally
on. For a PMOS, polarity is reversed.
19.4.1.2 Ohmic mode:
This mode is also known as the triode operating mode, in reference to the
three electrodes vacuum tube that operated as a variable resistance. It is also
called or linear region. As already stated, this mode occurs when V DS ≤
V GS − V T . For this reason, the term V GS − V T is noted V DSat.
W KP
ID = · · V DS · (2 · (V GS − V T ) − V DS)
L 2
IG = 0
19.4.1.3 Saturated mode:
This mode is also known as the pentode operating mode, in reference to

the ve electrodes vacuum tube that operates as a variable current source. It
is also called saturation region. As already stated, his mode occurs when
V DS ≥ V GS − V T = V DSat
W KP 2
ID = · · (V GS − V T )
L 2
IG = 0
19.4.2 Inuence of VDS

This characteristics applies in both ohmic and saturated mode. The nite
output resistance is sometimes called Early eect for the MOS transistor as it
has the same eect on output current both devices.
19.4.2.1 Ohmic mode
W KP
IDOhmic = · · V DS · (2 · (V GS − V T ) − V DS) · (1 + λ · V DS)
L 2
At low VDS values and assuming a low value of λ, an equivalent resistance
can be dened:
dV DS L 1 1
RON = = . .
dID W KP V GS − V T − V DS
19.4.2.2 Saturated mode
W KP 2
IDSaturated = · · (V GS − V T ) · (1 + λ · V DS)
L 2
19.4.3 Bulk eect

This phenomenon applies in both ohmic and saturated modes. The VT value
depends on the source-bulk voltage as follows:
√ √
V T = V T0 + Γ · Φ − V BS − Φ
In this expression,
V T0 is the VT value for V BS = 0.

Φ is the surface potential.
Γ is the bulk threshold parameter.
19.4.4 An experiment
The goal is to demonstrate the relationship between bulk eect and transition
from ohmic mode to saturation mode.
19.4.5 Noise
19.4.6 Matching
Mismatch mainly results from two parameters, VT and KP. Statistical im-
provement leads to:

∆V T AV T
σ =√
VT W ·L
and

∆KP AKP
σ =√
KP W ·L
Where AV T and AKP are usually expressed in %·m or % · µm.
19.5 Small signal model

When only small variations around the operating point are considered, the
equations can be linearized and an equivalent schematic can be drawn.
19.5.1 Transconductance
∂ID W W
gm = = · KP · (V GS − V T ) = · KP · V DSat
∂V GS L L
This expression is useful for sizing.
Transconductance can also be expressed as a function of drain current for
the sake of comparison with the bipolar transistor:
W √
r
gm = 2 · KP · · ID
L
As the expression shows:
A MOS transconductance is proportional to the drain current square root

while a bipolar transconductance is proportional to the collector current.
A MOS transconductance depends on the transistor geometry while a

bipolar transconductance does not.
19.5.2 Input capacitance

A MOS can be considered as a number of elementary MOS with channels
connected in series with a common gate and a common bulk. Because voltage
varies along the MOS channel, not all the elementary MOS are in the same
operating mode. This can be simulated to visualize this phenomenon. Let's
connect ten 0.2 µm long MOS so as to create a 2 µm long MOS. and let's bias
it to create a current source:
The bottommost MOS operate in the ohmic mode and the topmost ones
operate in the saturation mode. At some point along the channel, a transition
occurs. The transition point location depends on the bias conditions.
Figure 19.5:
The input capacitance is located mainly on the ohmic MOS transistors so

not the whole gate area accounts for the input capacitance. An acceptable
approximation is to consider that about 1/3 of the gate area is to take into
account:
1 W ·L
CIN = · ε0 · εR ·
3 T ox
19.5.3 Output resistance

∂V DS 1
rO = =
∂ID λ · ID
By analogy with the bipolar transistor, one could say that the Early voltage
is:
1
V EARLY =
λ
19.5.4 Output capacitance

Output capacitance mainly results from the reverse biased Drain-Bulk junction.
As such, it depends on two terms:
The Drain-Bulk junction area
The Drain-Bulk junction perimeter
Both terms depend on W.
The junction area is equal to the MOS W times the drain diusion width
w:
JA = W · w
The junction perimeter is equal to twice the MOS W and twice the drain
diusion width w:
JP = 2 · (W + w)
The overall junction capacitance is:
CJDB0 = CA · JA + CP · JP
Where CA is the capacitance per unit area and CP is the fringe capacitance
per unit perimeter.
In addition, as the Drain-Bulk is a reverse biased junction capacitance, it
depends on the junction voltage:
1
CJDB = CJDB0 ·
V BD M J

1− VJ
19.5.5 Miller capacitance

Miller capacitance mainly results from the fringe Drain-Gate capacitance. This
capacitance depends on gate oxide thickness, on gate poly thickness and on W.
Exact value can only be extracted from 3D simulation provided the fact the
dierent thickness values are available.
19.6 Weak inversion

When V GS < V T, simplied equations dened so far do not apply, another
operating mode called weak inversion or sub-threshold mode takes place.
In the sub-threshold mode of operation, MOS transconductance is close to
that of a bipolar transistor.
19.7 Eects of geometry

Geometry parameters, W and L, appear explicitly in equations. They have a
direct impact on the MOS transistor current, transconductance and resistances.
For static parameters only ratio

W
L accounts.
For capacitances, W and product W ·L account.
For static parameters matching, improvement factor is √

1
W ·L
.
1
f noise, varies as
√ 1
W ·L
.
Saturated mode output resistance varies with L.
19.8 Sizing
Sizing a MOS is choosing parameters W and L so that small signal parameters
meet the requirements.
19.8.1 Saturated mode

In saturated mode, a MOS is sized primarily either to generate a given current
value either to exhibit a given transconductance.
19.8.1.1 Sizing a current source
As already stated, Drain current equation is:
W KP 2 W KP 2
ID = · · (V GS − V T ) = · · (V DSat)
L 2 L 2
Then:
V GS = V T + V DSat
W 2 · ID
= 2
L KP · (V DSat)
Given the target current, the saturation voltage and the technological pa-
W
rameter KP, the MOS
L can be determined. The secondary parameters such
as matching or output resistance or input capacitance can be used to choose
W and L.19.7
19.8.1.2 Sizing a transconductor
As already stated, transconductance is:
W
gm = · KP · V DSat
L
Then:
V GS = V T + V DSat
W gm
=
L KP · V DSat
And, as a result, transconductor has to operate at drain current:
gm · V DSat
ID =
2
Given the target transconductance, the saturation voltage and the techno-
W
logical parameter KP, the MOS
L can be determined. The secondary param-
eters such as matching or output resistance or input capacitance can be used
to choose W and L.19.7
19.8.2 Ohmic mode

In ohmic mode, a MOS is sized primarily to meet a given RON value for a
given VGS value (assuming VDS=0).
W 1
=
L RON.KP.(V GS − V T )
19.9 Basic congurations

Just like for the bipolar transistor, each pin can be made common to the input
and output circuit. The MOS can the be used in the three following basic
congurations that are similar to those of the bipolar:
Common source
Common drain
Common gate
In addition, since the MOS has a fourth pin, a fourth basic conguration exists
involving the bulk:
Common bulk, the switch connection

Figure 19.6:
Figure 19.7:
Figure 19.8:
19.9.1 Common source

In this conguration, input voltage is applied between gate and source while
output current ows from drain to source. Load is connected between positive
supply and drain. This conguration is similar to the bipolar common emitter
conguration.
19.9.2 Common drain

19.9.3 Common gate
19.9.4 Common bulk or oating switch
In this conguration, input and output are drain ans source, bulk is connected
to supply, positive for PMOS and negative for NMOS and gate is connected
to control voltage. Switch is ON if control is positive with respect to bulk for
NMOS and negative with respect to bulk for PMOS.
When the switch is on, voltage on drain and source are normally identical.
The voltage to be switched with respect to the bulk voltage denes the VBS
voltage that in turn denes VT that in turn inuences RON. This is a well
known phenomenon, a switch ON resistance depends on the voltage to be
switched. For a NMOS switch, RON is minimal when voltage is close to the
negative supply voltage where the bulk is connected and RON increases with
voltage.
For a PMOS the situation is opposite. A CMOS switch is built with an
NMOS and a PMOS switches connected in parallel with gates driven with com-
plemented voltages. The resulting RON variation with voltage is signicantly
reduced.
19.10 Extracting level 1 parameters

As already stated, level 1 models are no longer in use in design kits. So, we
have to extract the level 1 parameters we need from the more complex model
actually used in the design kit.
19.10.1 KP and VT
The most important parameters are KP and VT that appear in the basic MOS
transistor equations.
VT is the MOS threshold voltage. It is expressed in volts.
KP is the MOS transconductance coecient. It is expressed in ampere

per square volt.
The method for extracting KP and VT consists in interpolating the ID vs.

VGS characteristics with a second order polynomial.
W KP 2 W KP
· V GS 2 − 2 · V GS · V T + V T 2

IDM ODEL = · ·(V GS − V T ) = ·
L 2 L 2
IDSIM U LAT ION = K2 · V GS 2 + K1 · V GS + K0
Making the two expressions equal leads to:
W KP
· = K2
L 2
W
− · KP · V T = K1
L
W KP
· · V T 2 = K0
L 2
Solving for KP and VT leads to:
K1
VT =−
2 · K2
2 · K0
KP = W
L · V T2
W
A convenient W and L set is
L = 1 which simplies a bit the calculation.
In order to avoid short channel eects that would give incorrect results, a good
choice is W = 10 µm and L = 10 µm or W = 1 µm and L = 1 µm for nodes
down to 130 nm.
A point of attention is choosing properly the VGS range for the polynomial
interpolation since the tting can be correct only above VT and within a limited
range. VDS for this extraction must be larger than VGS - VT.
A practical solution is to connect the MOS drain to the gate, to ground
the source and to force a current in the drain. Sweeping the current over three
decades ensures the dierent constraints are met:
V GS > V T
V DS > V GS − V T
The remaining question is about the current range to choose. The decades
from 0.1µA to 100 µA are normally suitable for a MOS with W = 10 µm and
L = 10 µm. This can be checked by comparing the simulated and modeled ID
vs. VGS curves.
Example Let's extract Level 1 parameters for a 3V NMOS in a 0.18 µm

process. The suggested schematic is:
The simulated ID vs. VGS curve with the above schematic is:
Loading these data into a spreadsheet and interpolating the curve with a
second order polynomial gives the following equation:
ID = 6.031771E − 05 · V GS 2 − 8.103773E − 05 · V GS + 2.719056E − 05

Figure 19.9: Extracting KP and VT
Figure 19.10: ID vs. VGS
So:
K2 = 6.031771E − 05
K1 = −8.103773E − 05
K0 = 2.719056E − 05
And then, from our formulas:
K1
VT =− = 671.76 mV
2 · K2
2 · K0
KP = W
= 120.51 µA · V −2
L · V T2
Now let's compare the simplied model and the simulation. Here are the
drain currents from the actual model and the simplied model versus VGS:
Matching looks pretty good, it is not so easy to see that there are two
curves.
Now, switching Y axis to log shows a dierence between the two curves
when VGS is close to VT.
This is normal since the simplied model does not take into account the
sub-threshold behavior while the BSIM3.3 for the transistor in the design kit
does.
These curves also show that the current range for the extraction is correct
as it is mainly located above the threshold but it includes the threshold. At
the other end, VGS does not exceed the valid range of 3 V in this case.
Figure 19.11: Comparing Level 1 to actual model (lin scale)
Figure 19.12: Comparing Level 1 to actual model (log scale)
Now, if we change the current range for the extraction to sweep from 1 µA
to 1000 µA, we notice that the VGS range reaches 6 V, far outside the valid
range and does no longer go below the threshold. The polynomial interpolation
in the spreadsheet is visibly not very good. The simplied model parameters
as extracted with the above formulas are both negative, which is not possible.
All this indicates that the current range is incorrect.
The key of this extraction method is choosing properly the current range.
Fortunately, it is quite easy to compare the simplied model and the simulation
to validate the current range and the result. Just as stated all along this book,
any result always has to be checked!
19.10.2 Tox
This parameter is normally directly accessible as it exists in most models.
However, if the data are encrypted, it might be necessary to extract it.
19.10.3 Lambda
This parameter denes the output resistance. Measuring output resistance for
a given current gives λvalue easily.
19.10.4 Gamma and Phi

These parameters are related to the threshold voltage change with respect to
the source-bulk voltage. Extracting VT as explained above for various VBS
values and tting the curve by playing on Gamma and Phi is the basic method
for extracting these parameters.

The major dierence with the bipolar transistor is that parameters, even
though accessible are not very helpful. The best practice is to run simula-
tions to check is the eect of interest is properly modeled. The most frequent
MOS modeling limitations are:
Lack of junctions current.
No modeling of weak inversion.
No modeling of bulk current.
19.11.1 Junctions current

Chapter 20
Common characteristics of bipolar

and MOS transistors
As developed in their respective chapters, the bipolar and the MOS transistor
share many characteristics in common at least in the current source region:
They are voltage controlled and exhibit some transconductance
They have an input capacitance
They have an output resistance
They have an input series resistance
They have an output capacitance
They have a Miller capacitance
The main dierence is that the bipolar has a nite input resistance while it is
innite for the MOS.
So, in fact, we can use the same equivalent schematic for both the bipolar
and the MOS transconductor and ignore the input resistance if it is used to
represent a MOS:
The input series resistance is noted RPI and stands for the bipolar RB
or the MOS RG which is negligible in most cases.
The input capacitance is noted CPI and stands for the bipolar CBE or
the MOS CGS.
The output resistance is noted RO and stands for both the bipolar and
the MOS RO.
The output capacitance is noted CO and stands for the bipolar CCS or
the MOS CDB.
The Miller capacitance is noted CM and stands for the bipolar CBC or
the MOS CGD.
Figure 20.1:
124
CHAPTER 20. COMMON CHARACTERISTICS OF BIPOLAR AND
MOS TRANSISTORS 125
The transconductance is noted gm and stands for both the bipolar and
the MOS gm.
Chapter 21
Resistors
21.1 Symbols
There are mainly three symbols for resistors:
Figure 21.1: Resistor symbols
These symbols are equivalent. A resistor is a symmetrical two pins compo-

nent.
21.2 Layout
Standard resistors are rectangular with a body and connections through con-
tacts at each end:
In order to t within acceptable dimensions, very long resistors may be
drawn with more complex shapes such as L, U, S or W:
These resistor types will be discussed later on.
Figure 21.2:
Figure 21.3:
126
CHAPTER 21. RESISTORS 127
21.3 Cross section

Resistors in integrated circuits exist in two major types. Types are named after
the material they are made from.:
Bulk resistors made from doped monocrystaline silicon inside the die
itself.
Poly-silicon resistors made from doped polycrystalline silicon over the die
in oxide.
In all the gures below, only the nal and simplied resistor structure is shown,
no details are given on process.
21.3.1 Bulk resistors

Bulk resistors can be of many dierent technological types, using various layers.
However, from a topological standpoint there are mainly two types:
P type resistors in a N well
N type resistors in the P substrate
Occasionally, N type resistors in a P Well may exist in some process.

Following gure shows a P type bulk resistor in a N well. Obviously, an
isolation diode exists between resistor body and N well. Voltage on resistor
body should always be lower than well voltage for the resistor to behave prop-
erly. This is why the N well is often connected to the most positive available
voltage, the positive supply.
Figure 21.4: Bulk resistor Cross-section
21.3.2 Poly resistors

Poly resistors have all the same topology:
Figure 21.5: Poly resistor Cross-section

21.4 Model
21.4.1 Basic equation
The model for a resistor is essentially the Ohm's law.
U =R·I
This model has just one parameter: R, the resistor value.

Temperature coecients can be added to take into account the temperature
dependence of the resistor value.

2
R (T ) = R (T ref ) · 1 + T C1 · (T − T ref ) + T C2 · (T − T ref )
This expression shows three temperature dependence parameters: Tref,

TC1 and TC2
Tref is the reference temperature. At reference temperature, resistor

has nominal value R(Tref ).
TC1 is the rst order temperature coecient

TC2 is the second order temperature coecient
21.5 Body and head resistances

In an integrated circuit, resistors are made from a constant thickness thin layer
of a given resistivity. The general expression of a constant section resistance
versus physical and geometrical parameters is:
L
R=ρ·
S
This expression shows three parameters: ρ, L and S
ρ is the resistive layer resistivity
L is the resistor length
S is the resistor section
For an integrated resistor, section S depends on resistor width W and

resistive layer thickness T:
S =W ·T
Then, for an integrated resistor:
ρ L
R= ·
T W
This expression is the product of two terms
ρ
T is called sheet resistance. It is expressed in ohms per square as it
is the resistance of a square resistor for which L=W.
L
W is called the number of squares. It has no unit. It is equivalent
to the number of square resistors connected in series. When ratio is
smaller than 1 is can be considered as the inverse of the number of
square resistors connected in parallel.
If several resistors with same width and various length are implemented in a
circuit and measured, expected values from above formula should t a linear
law. However, measured data show an ane law with a slope and an oset:
Figure 21.6: Resistance vs. Length
The oset can be considered as the resistance of a zero length body resistor.
What can this mean? It means that some extra resistance exists that does not
lie in the resistor body. It is usual to call this extra resistance Head resistance
as it is located at each end of the resistor. In the example above, the body
resistance is given by the slope and the length, the head resistance at each end
is half the oset. Here, the body resistance is 100 Ω per unit length and the
head resistance is 50 Ω at each end for a total 100 Ω.
The head resistance results from two eects:
A geometrical eect:
Figure 21.7: Geometrical eect
This gure shows a resistor with two connections on the upper side. Con-
stant voltage surfaces are plotted every 10% of the total voltage. Current ows
perpendicularly to these surfaces. There is clearly an eect around the connec-
tions as they do not use the full body width and they are located on the top
forcing the current lines to bend. This eect generates some extra resistance.
A technological eect
In order for the connection to create ohmic contacts and no parasitic

junction, a silicide is created at each resistor end. The silicide traps
Figure 21.8:
Figure 21.9:
some of the doping from the body creating a higher resistivity thin
layer at the interface.
These two eects combine to create the head resistance. Practically, this head
resistance is not completely correlated with the body resistance as it results
from dierent process steps. Head and body resistances usually exhibit dierent
temperature coecients. As a consequence, if two resistors have to be created
with an accurate ratio, playing with the body length is usually not a robust
solution: In this case, the ratio is aected by process tolerances and it depends
on temperature. The only solution for the resistor ratio to be accurate is that
the body and head contributions are the same for the two resistors. The only
practical approach is connecting a number of identical elementary resistor in
series-parallel combinations for implementing each of the two resistors. This
method suers from an area penalty but achieves a process and temperature
independent accurate resistor ratio.
21.6 Parasitic capacitance

21.6.1 Bulk resistors
These resistors are made from P silicon inside an N well or from N material in-
side a P well. Isolation is granted by biasing the well so that the isolation diode
is reverse biased. The depleted region thickness depends on the doping and on
the reverse voltage. Capacitance between resistor body and well depends on
resistor area, depleted region thickness and silicon dielectric constant.
21.6.2 Poly silicon resistors

These resistors are made from P or N doped poly-silicon inside silicon dioxide.
Isolation is grated by the huge resistivity of oxide. Capacitance depends on
resistor area, oxide thickness and oxide dielectric constant.
21.6.3 Modeling
Parasitic capacitance is distributed along the resistor body. The impedance
versus frequency of a capacitance distributed along a resistance with the other
pin grounded is:
At rst sight, this looks like a parallel R-C cell. This can be modeled as a
π equivalent circuit. Impedance versus frequency compared to the distributed
capacitance:
If we compare characteristics we notice that the model is acceptable up to
a frequency about xxx.
Above this frequency, we have to switch to a two cells model:
This model is reasonably accurate up to xxx.
Above, more cells are required
21.7 Linearity
Resistors are supposed to be linear as Ohm's law states. However, various
phenomenon aect this linear behavior and create some non linearity.
Temperature coecient. When voltage changes, dissipated power changes

and then temperature changes. So resistor value changes.
For bulk resistors, depleted region thickness modulation. Voltage across

isolation junction changes depleted region thickness. At least part of
the depleted region extends inside resistor body. When voltage changes,
actual resistor section changes so resistor value changes.
21.8 Tolerances
21.8.1 Absolute values
The absolute value of a resistor depends on its length, width, thickness and
resistivity. Each of this four parameters suers from manufacturing tolerances
so that nally integrated resistors are not accurate. Tolerance on absolute can
be as bad as ±20 % or even ±30 %.
21.8.2 Matching
Two identical resistors close to each other in the same silicon die suer together
the tolerance on absolute value from the process. However, even if their ab-
solute value is inaccurate, their relative values are far more accurate. ±1 %
is very standard, ±0.1 % is achievable. Because width and length are perpen-
dicular to each other, they suer uncorrelated tolerances. For that reason, no
matching can be granted for two resistors that are not parallel.
21.9 Thermal resistance

If some power is dissipated in a resistor, its body temperature rises above the
surrounding temperature.48.8
Here again, a dierence exists between bulk and poly-silicon resistors. Ox-
ide thermal conductivity is about 100 times lower than silicon thermal con-
ductivity. Actual thermal resistance can only be simulated with a 3D thermal
simulator. However, as a rule of thumb, we can state that poly-silicon resistors
can dissipate 100 times less power than bulk resistors for the same size and
the same temperature increase. Special mention for SOI processes in which an
oxide buried layer can signicantly increase thermal resistance.
Resistor thermal resistance partly depends on chip packaging:
For plastic package, part of the heat ows through the chip silicon sub-
strate and part of it ows through top oxide, passivation and package.
For cavity packages, heat ows mostly through the chip silicon substrate.
Upper ow through cavity gas is negligible.
In the examples hereafter, heat will be considered to ow only through chip
substrate.
21.9.1 Bulk resistor thermal resistance

Resistors are often rectangular objects with one dimension larger than the
other one. Sometimes however, they can be close to a square with two identical
dimensions. We will analyze both cases.
21.9.1.1 Square resistors
If the resistor is square shaped, constant temperature surfaces inside silicon

become spheres halves very quickly as distance to resistor body increases. Here,
one quarter of the structure is shown for clarity. Power is dissipated in the left
front top corner and ows to the back side of the chip. Next two plots show
1% and 10% thermal resistance locations:
Figure 21.10: Thermal resistance 1%
Here, 1% of the total temperature dierence takes place between the back
side and the spherical surface. So, 99% of thermal resistance is located between
spherical surface and resistor body at the left front top corner.
Figure 21.11: Thermal resistance 10%
Here, 10% of the total temperature dierence takes place between the back
side and the spherical surface. So 90% of the thermal resistance is located
between spherical surface and resistor body at the left front top corner.
The thermal resistance between two sphere halves of radius R1 and R2

(R2 > R1) is 48.10:

1 1 1
Rth = · −
γ·2·π R1 R2
Where γ is the silicon thermal conductivity.( γ = 149 W.m−1 .K −1 )

Note that if (R2 >> R1), then

1 1
Rth# ·
γ·2·π R1
In this case, thermal resistance depends only on resistor equivalent radius. This
conrms that thermal resistance is located mainly in close proximity to resistor
body, as can be seen in the plots.
What about the equivalent radius for a given resistor geometry?

There is no analytical exact solution and only Finite Element Analysis can
provide a numeric answer.
Example: A 10 µm · 10 µm, 1 µm thick bulk resistor dissipating 40 mW at

the center of a 250 µm thick 2 mm · 2 mm chip: Thermal simulation using a
3D Field Solver (EZMod3D) using Finite Elements. This corresponds to the
situation shown in the two plots just above. (For clarity, only one quarter of
the chip is shown).
Simulation results shows that maximum temperature in the center to of

resistor (the top front left corner in the plot) reaches 13.65 K with respect to
back side.
Figure 21.12:
Average temperature in resistor body is 10.93K. Equivalent thermal resis-

tance is then
10.93
0.04 = 273.25 K.W −1 .
In turn, knowing thermal resistance and thermal conductivity, we can cal-
culate equivalent radius:

1 1
R1# · = 3.909 µm
γ·2·π Rth
Corresponding volume is:
4
V1= · π.R13 = 250.2E − 18 m3
3
This value looks reasonable compared to actual resistor body volume (100E-
18). Ratio is 2.5 and can be explained by the fact the resistor body is very
thin, so it is far from a spherical form factor. Considering equivalent radius
as extracted from actual resistor body volume assuming is spherical leads to a
value that is usually smaller than actual equivalent radius. Thermal resistance
calculation based on this simple assumption is pessimistic (too high) but can
be used as a clue if no thermal simulator is available.
It can be noted that the Finite Elements Method can simulate more complex
situations such as SOI substrate and plastic packaging.
21.9.1.2 Long resistors
If the resistor is long, constant temperature surfaces inside silicon are cylinders
halves with one sphere quarter at each end very quickly as distance to resistor
body increases:
The thermal resistance between two cylinder halves of length L and radius
R1 and R2 (R2 > R1) is 48.9:
1 R2
Rth1 = · ln
γ·π·L R1
This thermal resistance is in parallel with that of the two sphere quarter:
The thermal resistance between two sphere halves of radius R1 and R2

(R2 > R1) is :

1 1 1
Rth2 = · −
γ·2·π R1 R2
This thermal resistance is in parallel with that of the two sphere quarter:
The overall thermal resistance is equal to the two in parallel:
1
Rth = 1 1
Rth1 + Rth2
1
Rth = γ·π·L γ·2·π
ln R2
+
R1 ( R1
1 1
− R2 )
21.9.2 Poly resistor thermal resistance

For poly resistors, heat has to ow through oxide to reach the silicon bulk. At
least for plastic packages, part of the heat ows through oxide to the package
but oxide thickness above poly is much larger than below poly. So, most of the
heat ows to bulk. One point to consider is that the volume of polysilicon is
quit small. So, in addition to a higher thermal resistance, poly resistors exhibit
shorter time constants thant their bulk counterparts. Globally, if signicantly
loaded, poly resistors can heat up quickly and signicantly. And because of
a dierence in dilatation coecient between poly and surrounding oxide, me-
chanical stress occurs and can lead to fracturing resistor body or oxide. This
is rare but can occur for large resistors dissipating signicant power.
21.9.2.1 Example
21.9.2.2 Reducing poly resistor thermal resistance
21.10 Misalignment
Components geometries in ICs are dened by photo-lithography involving dif-
ferent steps. At each step, the pattern dening one dimension is positioned
with respect to patterns dened at earlier steps. This positioning suers from
tolerances that lead to the so called Misalignment that involves three param-
eters:
X axis misalignment
Y axis misalignment
Angular misalignment
21.10.1 X Y Misalignment
If a component geometry is dened by only one lithography step, it does not
suers from misalignment. If a component geometry is dened by two lithog-
raphy steps, it may suer from misalignment. The impact of misalignment
depends on the component shape and size.
For a resistor, the geometry parameters are the length and the width that
are usually dened by two lithography steps:
Width is dened by the poly or diusion layer.
Length is dened by silicide or contact layer.
A rectangular resistor does not suer much from misalignment as width is

dened by one layer and length by another layer. If the layers are moves with
respect to each other, the length does not change. For instance, this is the
situation for POLY resistors with silicide block dening the body length. Is
silicide block mask is misaligned in whatever direction (here in x) body size is
not aected, so resistance is not aected:
Figure 21.13: Rectangular resistor misalignment
A U shaped resistor width is dened by one layer but the length is dened
by the positioning of the layer dening the length with respect to the resistor
body. When this position changes, the resistor value changes. This is one of the
reasons why resistors are usually single branch rectangular objects. Another
reason is that the simpler the object is, the simpler the generator used in layout
tools is.
Figure 21.14: U shaped resistor misalignment
For an S shaped resistance, the misalignment has no impact just as for

an I shaped one. More generally, odd numbers of branches are tolerant to
misalignment while even numbers are not. But again, resistors are usually
single branch rectangular objects.
21.10.2 Angular Misalignment

Eect of angular misalignment is not easy to analyze. Intuitively, rotating
one mask with respect to the other will make length edges non perpendicular
to body, but average length seems unaected. One can imagine body width
divided in a number of parallel strips. All the strips will have the same length,
so, length should not be aected signicantly. There might be some eect due
to the fact that body current ow is aligned while current ow reaching head
is bent.
° °
Numeric simulations can give some insight. Again, EZMod3D solver was
used to compare two angles: 0 and 1 (huge angle, much more than what is
°
found on a wafer). Here is a 3D view of an arbitrary geometry resistance with
heads exhibiting an angular misalignment of 1 :
Figure 21.15: Rectangular resistor angular misalignment
Resistance value has to be compared to the perfectly aligned head situation.

Extracted resistance values in both cases are:
°
R(0 ) = 5267.954
°
R(1 ) = 5261.716
Misaligned resistor value is simulated to be 0.9988 times aligned resistor value

(-0.1122%). As expected, angular misalignment has limited inuence on resis-
tance even though it was intentionally exaggerated in this example. This is
probably caused by the bending of current ow reaching resistor heads.
21.11 Gradients
Two kinds of gradients can aect resistors:
Technological gradients
Temperature gradients
21.11.1 Technological gradients

The resistors layer resistivity and the resistors geometry are dened by process
steps that can create a local gradient. This gradient has two terms:
A random term that results from random uctuations. This random

uctuation has zero average value.
A systematic term that can result from a particular wafer orientation

during a process step.
Because of the systematic gradient, two resistors located side by side may not
have the same value.
21.11.2 Temperature gradients

If power is not dissipated evenly in a chip, some places are hotter than others
causing temperature gradients. Because of the resistors temperature coecient,
two resistors located side by side may not have the same value.
21.11.3 Limiting gradients eects

Whatever the origin, gradient is expressed as a resistor change with respect to
dR
distance:
dx assuming gradient is along x axis. Then, dierence between two
identical resistors can be expressed as:
dR
∆R = ·D
dx
where D is the distance between the resistors:
Figure 21.16: Eect of gradient on 2 resistors
If four identical resistors are used instead of two, connecting the outer ones
in series to form the rst element and the inner ones in series to form the
second element, calling R1 to R4 the four resistors, p the resistors pitch and
considering R1 at position x = 0:
Figure 21.17:
dR
R2 = R1 + ·p
dx
dR
R3 = R1 + ·2·p
dx
dR
R4 = R1 + ·3·p
dx
Figure 21.18: Eect of gradient on 4 resistors
Then:
dR
R1 + R4 = 2 · R1 + ·3·p
dx
dR
R2 + R3 = 2 · R1 + · 3 · p = R1 + R4
dx
The gradient is canceled!
If the gradient is not in the x direction, it does not matter. The actual
gradient can be split in two terms, one along x and one in the perpendicular
direction y. As the resistors are aligned in y, only the gradient along x accounts
and we are back to the previous situation.
21.12 Dummies
An additional technological phenomenon can aect resistor values. When a
group of identical resistors is created, they are usually spaced evenly and lo-
cated close to each other to minimize silicon area. During the resistor body
etching, the local amount of material to be removed slightly aects the etching
speed. In particular, resistors at the end of the row are not etched exactly as
the other ones and nally their value are slightly dierent. In order to prevent
or reduce this eect, one or two so called dummies are added at each end of
the row. These are just identical resistors with the same spacing but they are
not connected. Their value is not very accurate because of etching eects but
it does not matter. The last used resistor, as it is in the same environment as
the other ones does not suer the etching eect and is just as accurate as the
other ones.
Figure 21.19:
21.13 Special resistors

Resistors are usually provided as design kit elements and they cannot be
changed easily. In some cases, Kelvin resistors can be required for accu-
racy. It is always possible to create new resistors by copying a resistor from
the design kit, translating it into polygons and editing it. The new device, of
course, must comply with the design rules, but this is easy to check with the
DRC tools. For LVS, the situation is dierent. The overhead to modify the
tools les is usually high and the modied les would no longer be sign-o. So,
the new devices can be LVS checked only manually. This is normally acceptable
as there are not many exotic devices in a design.

Resistors are simple components but a correct model taking into account all
the parasitic eects can be quite complex. The most common missing eects
are:
Correlation between process case and temperature dependence.
Parasitic diodes for bulk resistors and parasitic capacitors for poly resis-
tors.
Non-linearity.
No modeling of head resistance.
21.14.1 Extracting temperature coecients

Temperature coecients are normally visible in a resistor model. However,
models are sometimes encrypted or models can be very dicult to read because
in modern design kits, values are computed by from process case. Whatever the
reason, it can be necessary to extract temperature coecients if they are needed
for calculating some undesired eects or for checking the coupling between
process case and temperature coecients.
The method consists in simulating the resistor with swept temperature,

plotting the resistance versus temperature characteristics in a spreadsheet and
adding a tendency line using a 2nd order polynomial. Then, temperature
coecients can be extracted by reshaping to meet the model formula:
Example
21.14.2 Checking parasitic elements

21.14.3 Checking non-linearity
21.14.4 Checking head resistance
Chapter 22
Capacitors
22.1 Symbols
There are mainly three symbols for capacitors:
Figure 22.1: Capacitor symbols
These symbols are equivalent. A capacitor is a symmetrical two pins compo-

nent. However, in integrated circuits, capacitors are not exactly symmetrical
this is why the rightmost symbol is not really used while it can be used for
external non polarized capacitors.
22.2 Layout
There are various types of integrated capacitors:
MOS capacitors
POLY / N+ capacitors
POLY-POLY capacitors
MIM capacitors
MOM capacitors
143
CHAPTER 22. CAPACITORS 144
Figure 22.2: MOS Capacitor
Figure 22.3: POLY/N+ Capacitor
Figure 22.4: POLY-POLY Capacitor
22.2.1 MOS Capacitors

This type of capacitors uses the thin gate oxide as dielectric, the gate and bulk
as electrodes. It is some sort of MOS without drain and source.
These capacitors are reasonably dense at least in modern processes thanks
to the relatively thin gate oxide (Rule of thumb: 1 nm thickness per volt of
supply voltage). But these capacitors are highly non linear. They can be used
in any process without specic option.But they are not necessarily available as
a library component with a proper layout generator, a symbol and a simulation
model. In that case, a MOS must be used with drain and source connected to
bulk.
22.2.2 POLY N+ Capacitors

This type of capacitors uses the oxide as dielectric, the gate and drain/source
as electrodes.
These capacitors are less dense than MOS capacitors since they use a much
thicker oxide. But these capacitors are much more linear. They can be used in
any process without specic option, but they are not necessarily available as a
characterized component. In that case, a specic component must be created.
It is then not a very popular option since LVS may be in trouble.
22.2.3 POLY-POLY Capacitors

This type of capacitors uses two layers of POLY, the regular gate POLY and
a second POLY layer with a semi-thin oxide layer in between.
These capacitors are rather dense and linear. They require specic process
options and are not available in all processes. They tend to be replaced by
MIM capacitors
22.2.4 MIM Capacitors

This type of capacitors use one regular metal layer, usually the topmost one,
a thin layer of nitride as dielectric and a thin metal layer as second electrode.
MIM stands for Metal Isulator Metal.
These capacitors are rather dense, thanks to the high dielectric constant
of nitride and the rather small thickness. They are reasonably linear. They
require specic options and are not available in all processes.
Figure 22.5: MIM Capacitor

Figure 22.6: MOM Capacitors
22.2.5 MOM Capacitors

This type of capacitors uses regular metal layers and vias as electrodes and
surrounding oxide as dielectric. MOM stands for Metal Oxide Metal.
These capacitors do not require any process options and can be used in any
process. But they are not necessarily available as a library component with a
proper layout generator, a symbol and a simulation model. In that case, they
have to be created manually and managed as possible. It is then not a very
popular option since LVS may be in trouble. Depending on the process node
that denes metals and oxide thickness and metal min width and distance,
MOM capacitors may use vertical eld, horizontal eld or both.
22.3 Cross sections

22.3.1 MOS capacitor
22.4 Model
22.4.1 Basic equation
The capacitor model describing the relationship between voltage and current
is an integral expression:
t
1
V (t) = V 0 + I (t) · dt
C 0
This model has a single parameter C, the capacitance value.

The capacitance value depends on temperature:

2
C (T ) = C (T ref ) · 1 + T C1 · (T − T ref ) + T C2 · (T − T ref )
This expression shows three temperature dependence parameters: Tref,

TC1 and TC2
Tref is the reference temperature. At reference temperature, capac-

itor has nominal value C(Tref ).
TC1 is the rst order temperature coecient

TC2 is the second order temperature coecient
22.5 Area capacitance and peripheral capacitance

Let's start whit an experiment:
1. Let's measure the capacitance of a square piece of double sided FR4 PCB
material 10 cm (about 4 inches) side with untouched copper. Capacitance
value between the two copper planes is around 240 pF. Then, let's mea-
sure the capacitance of a smaller piece measuring 1 cm by 10 cm (about
0.4 inch by 4 inches). Capacitance value between the two copper planes
is around 25 pF.
2. Now, let's plot the measured capacitance value versus the PCB width:
Figure 22.7: FR4 capacitors
Capacitance vs. Width

3.00E-010
f(x) = 2.39E-012x + 1.36E-012
2.50E-010
2.00E-010
Capacitance (F)
1.50E-010
1.00E-010
5.00E-011
0.00E+000
0 20 40 60 80 100 120
Width (mm)
Extrapolating capacitance to zero width gives an oset value around 1.34

pF... What is that oset capacitance? Is it real and where does it come from?
To answer these questions, let's ask another question: Where is located the
235 pF capacitance? Electrostatic simulation helps answering this question.

Here is a zoom on the edge of the capacitor cross section. It shows the two
copper planes, the FR4 material in between and air around.
Figure 22.8: Fringe capacitance location
The curves on this plot show constant capacitance contribution surfaces.

The surfaces range from 10% to 90% of the maximum contribution. The higher
values are inside the FR4. So, the capacitance is mainly located between the
two copper planes, inside the FR4 material. But it is also located outside
the FR4 in the surrounding air. What is the extension around the FR4?
Well, the answer is simple, it extends to the entire universe! Of course the
contribution to the capacitance gets lower and lower as distance increases as the
electrostatic simulation plot shows. In addition, depending on signal frequency,
propagation in space around capacitor does transform impedance that is no
longer a capacitance! So, the capacitance is mainly located between the two
copper planes, but also outside. The oset capacitance that would exist if the
planes width would tend to zero is in fact the outside capacitance also known as
fringe capacitance. This capacitance does exist. It is proportional to the planes
perimeter BUT IT IS NOT LOCATED ON THE PERIMETER. It exists only
if the electric eld can extend around the planes. A rule of thumb is that
extension that contributes signicantly to the capacitance is located within a
distance once to twice the distance between the planes. This is visible on the
electrostatic simulation plot. Why is that concept not obvious? May be because
the current behavior is more intuitive to us than the potential behavior, but
also because of the range the relative permittivity can cover compared to the
range the resistivity can cover. The same phenomenon exists in a current ows
in a resistor. Most of the current ows inside the resistor but some current ows
around in the air and some current can reach the moon and much further. But
not much!
Copper resistivity is 1.6 · 10−8 Ω · m

Resistive materials resistivity values are in the 10−6 Ω · m range
Dry air resistivity is in the 109 Ω · m range
Glass resistivity is about 1017 Ω · m.
A pretty signicant range!

So, neglecting the current around a resistor does not result in a big error and
we are used to do that. But when it comes to relative permittivity values, they
range from 1 for vacuum or dry air to some hundreds, may be one thousand
for the highest available values. So, neglecting what happens outside a resistor
body is usaually not a concern, but neglecting what happens outside a capacitor
body can lead to errors. The fringe capacitance is usually much more important
than the fringe resistance.
22.6 Parasitic capacitance

In an integrated circuit, capacitors are made by two conductive layers separated
by a dielectric layer. There are several possible topologies to implement a
capacitor. Each of these uses dierent layers congurations for the electrodes
and for the dielectric. As a results, parasitic capacitance on each electrode
depends on eective capacitor topology. Main topologies are:
Vertical eld capacitors such as poly-poly and MIM capacitors
Horizontal eld capacitors such as single layer MOM capacitors
Compound eld capacitors such as multiple layers MOM capacitors
22.6.1 Vertical eld capacitors

There are many other layers around capacitor active layers, mainly under the
capacitor and in particular the substrate is the underlying layer of the entire
chip. The capacitor dielectric is usually very thin in order to achieve an accept-
able capacitance per unit area. The space between capacitor and substrate is
also lled with a dielectric, so one of the capacitor electrodes, the bottom one,
exhibits some capacitance with respect to substrate. This capacitance is para-
sitic. Depending on technology and mainly on underlying dielectric thickness,
parasitic capacitance ranges from 1 % to 10 % of a capacitor capacitance.
Parasitic capacitance is mainly located between bottom plate and underly-
ing layer. Default underlying layer is usually substrate, but it can be a well. It
is important to know for every capacitor in a circuit what is the most convenient
node to refer parasitic capacitance:
Figure 22.9: Vertical eld parasitic capacitor
If capacitor is used as bypass, the best is to connect the reference at the

same place as the cold plate.
If capacitor is used as coupling, the best is to connect the reference at

the input signal reference point.
It must also be kept in mind that for a coupling capacitor, choosing if parasitic
capacitance is connected on input or output has an impact on voltage gain:
If parasitic is on input side, there is no impact on gain, if on output, a
capacitive divider takes place.
22.6.2 Horizontal eld capacitors

22.6.3 Compound eld capacitors
22.7 Parasitic resistance
In an integrated circuit, the conductive layers dening a capacitor can be re-
sistive. This is in particular the case for poly capacitors. Electrodes resistance
result in a distributed resistance exactly in the same way resistors exhibit dis-
tributed capacitance. The dierence is that capacitors form factor can be
chosen so as to minimize resistance since capacitance depends only on area
(and a bit on perimeter as we have seen). For resistors, form factor is not free
as it denes resistance. So capacitors can be series resistance optimized while
resistors can't be capacitance optimized.
22.8 Breakdown voltage

22.9 Linearity
In integrated circuits, capacitors are made either from reverse biased junctions,
either from MOS structures either from poly-poly poly-metal or metal-metal
electrodes separated by a dielectric layer. Linearity characteristics are dierent
for the dierent structure
22.9.1 Reverse biased junctions

In such a capacitor, the depleted region thickness is strongly modulated by the
applied voltage. So is the capacitance. So, these capacitors are strongly non
linear.
22.9.2 MOS capacitors

The capacitance of a MOS capacitor depends on the applied voltage.
22.9.3 Poly capacitors

Poly capacitors linearity is better than that of MOS and junction capacitors.
But it depends on electrodes doping and siliciding.
22.9.4 Metal capacitors

These capacitors are the most linear. As far as the author knows, the capaci-
tance modulation is only caused by electrostatic forces that stress the dielectric
causing a slight electrodes distance reduction that slightly increase the capac-
itance when voltage increases.
22.10 Tolerances
In integrated circuits, tolerances for capacitors are about +/- 20% for the ab-
solute value and +/- 1% and below for matching. Achieving good matching
requires that both area and perimeter are matched because of fringe capaci-
tance.
If two identical capacitors have to realized, they have to be drawn iden-

tical, with the same form factor and the same environment.
If a capacitor ratio dierent from 1 has to be realized, particular attention

has to be paid to matching area and perimeter values and to have identical
environment.
22.11 Gradients
22.12 Dummies
22.13 Improvements
As mentioned, integrated capacitors have parasitic capacitance on the bottom
electrode. In dierential designs, balanced capacitors are required. Such a
capacitor can be implemented by splitting in in two identical capacitors of half
the total capacitance each and connecting them in parallel head to foot.

Validating design kit for capacitors is checking what parasitic eects are taken
into account. The most frequent missing eects on capacitors are:
Parasitic capacitance
Non-linearity
Series resistance
Temperature coecient
22.14.1 Extracting parasitic capacitance

22.14.2 Extracting non-linearity
22.14.3 Extracting series resistance
22.14.4 Extracting temperature coecient
Chapter 23
Inductors
Inductors used to be not very frequent in ICs for two reasons:
Only very small inductance values can be integrated, restricting usage to

high frequencies.
Quality factor is poor.
With the constant increase in frequency capability through years, inductors

have gained importance. Thanks to the large number of metal layers in modern
processes and to the thick top metal layer(s), quality factor has made signi-
cant progress. Since the two major limitations to their usage have been over-
come, inductors have become signicant components worth looking at.There
are mainly two topologies:
Spiral inductors, the most common topology
Multilayer solenoids, a more exotic topology
23.1 Spiral inductors

23.2 Multilayer solenoid
152
Chapter 24
ESD devices
Electronic components size has been reducing for decades from the rst dis-
crete components to the latest integrated ones. On the other hand, electrostatic
charges such as those we all experience when the air is dry have not changed
with time. The amount of energy ESD carry is signicant and when it is
dissipated in a device, the temperature rise depends on the device thermal ca-
pacitance. As devices got smaller and smaller, it happened that the ESD energy
became sucient to destroy the devices. In addition, devices were originally
junction based and as such, they were capable of handling the ESD current,
either in forward conduction or in reverse conduction through avalanche. But
when MOS devices appeared, gates, as completely isolated, brought new con-
cerns as they are not able to survive the ESD current that can ow only by
a destructive eect. There are then, two major reasons for adding protection
devices in ICs:
Small active devices cannot dissipate the ESD power without being de-
stroyed
MOS gates cannot survive breakdown.
ESD devices are basically diodes or equivalent devices that are normally o
and that turn on if voltage on a pin exceeds the supply voltage. Two devices
are required on each pin as ESD polarity is unknown and one diode can handle
only one polarity.
In addition to the diodes limiting the voltage about 1 V above the positive
supply and 1 V below the negative supply. But when the device is not connected
to a supply, additional devices are required to limit the voltage between the
supply rails.
ESD devices must be sized to handle the surge currents that can be large.
Three dierent standards exist to characterize the ESD sensitivity of ICs:
The Human Body Model (HBM).
The Machine Model (MM).
The Charged Device Model (CDM).
153
CHAPTER 24. ESD DEVICES 154
24.1 The Human Body Model

This model is intended to apply to ICs a discharge that is close to what a
human body does. The source is a 100 pF capacitor that is charged to the
desired voltage during the charge phase. During the test phase, capacitor is
discharged into Device Under Test (DUT) through a 1500 Ωseries resistance.
Schematic is:
Figure 24.1: HBM test bench
Waveforms through an ESD diode (capacitor voltage and diode currentcur-

rent) for a 4 kV test are:
Figure 24.2: HBM test waveforms
As expected:
Figure 24.3: MM test bench
Figure 24.4: MM test waveforms
Figure 24.5: CDM test bench
Peak current is Ipk = 4000

1500 = 2.667 A.
Current shape is a decreasing exponential. Time constant is τ = 1500.100E−
12 = 150 ns.
The standard denes that each pin is tested with respect to relevant supply
pins. Discharge is applied 3 times in each polarity. Levels are specied in
kilo-volts. Usual values are 2 kV, 4 kV. For peripheral circuits, level can be as
high as 16 kV.
A device is said to be HBM 4 kV compliant for instance if it survives the
test sequence on all pins with a capacitor charged at 4 kV.
24.2 The Machine Model

This model is intended to apply to ICs a discharge that is close to what IC
manufacturing machines are subject to do. The source is a xx pF capacitor
that is charged to the desired voltage. A xx resistance and xx inductance are
connected in series with the device under test. Schematic is:
Waveforms are:
Levels are in the hundreds of volts range. Usual values are 100 V and 200
V.
24.3 The Charged Device Model

This model is intended to apply to ICs a discharge that results from discharging
the IC itself charged to the desired voltage with respect to the underlying
ground plane.
Waveform is:
Current pulses are extremely short and may not trigger slow protection
devices.
Levels are in hundreds of volts. Usual values are 500 V, 750 V and 1000 V.
24.4 ESD protection general strategy

ESD protection is based on the fact that an ESD event may occur any time
during the circuit manufacturing or handling, during board assembly or during
application lifetime.
Figure 24.6: CDM test waveforms

24.5 ESD protection devices

24.5.1 ESD diodes
24.5.2 ESD rail clamps
24.5.2.1 Static rail clamps
24.5.2.2 Dynamic rail clamps

Chapter 25
Parasitic components
25.1 Isolation diodes

As already stated, in an integrated circuit, bulk components are isolated from
each other by reverse biased junctions. So, in an integrated circuit, there are
many isolation diodes. These diodes are normally reverse or zero biased. As
such they exhibit:
Some leakage current, normally very low but depending on temperature

and light.
Some capacitance depending on reverse voltage.
A breakdown voltage that can range from some volts to tens of volts.
If the isolation diodes are forward biased, some current appears.

Isolation diodes are more or less taken into account in design kits. During
design kit validation 18.11 19.11 21.14, this can be checked. However, Well
diodes are usually not taken into account. These diodes have to be managed,
often manually by the designer.
Some design kits include isolation diodes when layout is done by running a
parasitic extraction program.
25.2 Parasitic resistors

In integrated circuits, parasitic resistors are mostly located inside components
and they are usually taken into account by the models. Routing parasitic
resistors can be extracted by extraction tools after the layout is done and can
be taken into account in simulations at this time. The major eects of routing
parasitic resistances are:
I.R drops
Fast signal edges alterations
25.2.1 I.R Drops

I.R. drops result in performance changes.
157
CHAPTER 25. PARASITIC COMPONENTS 158
Figure 25.1: IR Drop Current Mirror
Figure 25.2: IR Drop Dierential Pair
Figure 25.3: IR Drop Mirror Strip
25.2.1.1 I.R. drop in a current mirror
For instance, if a current mirror is improperly connected to a supply rail, I.R.

drops can result in an output current that can be signicantly dierent from
the expected value.
25.2.1.2 I.R. drop in a dierential pair
If a dierential pair is improperly routed, I.R. drops can generate an oset.
25.2.1.3 I.R. drop in a multiple outputs current mirror
One common situation is a long strip of current sources.
In this situation voltages with respect to grounds are:
At rst source V1=R·N ·I

At second source V 2 = V 1 + R · (N − 1) · I = (N + N − 1) · R · I
At third source V 3 = V 2 + R · (N − 2) · I = (N + N − 1 + N − 2) ·
R · I = (3 · N − (1 + 2)) · R · I
At fourth source V 4 = V 3+R·(N − 3)·I = (N + N − 1 + N − 2 + N − 3)·
R · I = (4 · N − (1 + 2 + 3)) · R · I
PN −1 N ·(N −1)
At Nth source V N = N · N − i=1 i · R · I = 2 ·R·I
This calculation shows that the voltage drop at the last source varies quadrat-
ically with the number of sources. It is then always a good practice to have
the ground connection in the middle of the block. This divides N by two and
divides the voltage drop by 4.
25.2.1.4 Non evenly distributed currents in via arrays
Imagine current owing in a metal line and then through vias to reach another
metal layer. Usually, several vias are used to improve manufacturing yield and
to reduce series resistance. The vias are arranged in a matrix between the two
metal layers. That matrix is organized in M rows and N columns. In order to
demonstrate the point, let's choose rst M=1. The N vias can be distributed
either along the current ow direction or perpendicular to that direction.
Let's consider the case where vias are distributed along the current direc-
tion. This situation can be modeled as:
Figure 25.4:
Figure 25.5:
Figure 25.6:
The horizontal resistors gure the metal layers resistance while the vertical
resistors gure the vias resistance.
Let's now simulate this circuit with a given current. What about the current
in the dierent vias? Any idea before looking at the simulation result?
The following plot shows the via current with respect to via number.
This very simple circuit shows that the current is not evenly distributed.
25.2.2 Edges alteration

An eect of signal routing resistance is that a long line is equivalent to a
distributed R-C low-pass lter. The eect of such a lter is not only to delay
the signal, but also to slow down the signal edges. The following simulation
result
25.2.3 Conclusion
Parasitic resistance can have a signicant impact on circuits behavior and per-
formances. Today, most design tools can extract parasitic resistance and the
eects can be simulated. It is important to look in details at the simulation
results. Some eects are clearly visible, other eects are much more subtle and
require true attention.
It is strongly suggested to think about parasitic resistance during design
and more specically during layout. Parasitic extraction can show the issue,
this is good news, but the job has to be done again and this is bad news.
25.2.4 Validating design kit

Validating the design kit for parasitic resistance extraction requires going through
the design and layout ow and check extraction results of several structures for
which validation is easy.
25.2.4.1 Metal I line resistance
25.2.4.2 Metal L line resistance
25.2.4.3 Vias resistance
25.2.4.4 Metal polygon resistance
25.3 Parasitic capacitors

Two isolated conductors exhibit some capacitance between each other. When
this capacitance is unexpected, it is called parasitic capacitance. In a circuit,
adding some capacitance at some places can modify behavior or at least per-
formance. Apart from isolation diodes, parasitic capacitances are mainly due
Figure 25.7:
to connections. Routing capacitors can be extracted by extraction tools after

the layout is done and can be taken into account in simulations.
Just as for parasitic resistance, thinking about parasitic capacitances impact
during design and layout avoids doing the job again even though extraction
programs can show the issue before running the silicon.

As for parasitic resistances, validating parasitic capacitance extraction requires
walking the design ow through layout and extraction on simple structures that
validate the extraction.
25.3.1.1 Parasitic capacitances between two metal layers
Several situations have to be checked:
Overlapping connections In this situation, both the area capacitance and

the fringe capacitance can be checked.
Non-overlapping connections In this situation only fringe capacitance can

be checked.
25.3.1.2 Parasitic capacitance in the same metal layer
In this case, only the mix of area and fringe capacitances can be checked.
25.3.1.3 Parasitic capacitances to substrate and well
This test is intended to check if a distinction is made between substrate and

well for the cold side of the parasitic capacitance.
25.3.1.4 Parasitic capacitances in complex structures
This test is intended to check if screening eect is taken into account.
25.4 Parasitic MOS

In integrated circuits, parasitic PMOS transistors exist in every place where
an N type region is located between two P type regions if a metal line overlaps
the N region. The same exists for an NMOS by just swapping N type and P
type regions.
Usually, threshold voltages for these parasitic MOS are high and they are
not a concern. However, in high voltage applications, parasitic MOS can create
undesired currents and can result in trouble.
Unfortunately, parasitic MOS are usually not modeled nor taken into ac-
count by extraction. Sometimes, they are agged by verication programs and
it is the designer's responsibility to check whether they can cause issues.
Figure 25.8:
Figure 25.9:
If no data are supplied by the silicon manufacturer, the most secure ap-
proach is to implement the various parasitic MOS transistors in a test circuit
and to measure their threshold voltages.
25.5 Parasitic bipolar

In integrated circuits, parasitic bipolar transistors exist at any place where N,
P regions are arranged so as to create NPN or PNP structures. As an example,
a parasitic substrate PNP is associated to each vertical NPN:
This parasitic PNP draws current from NPN base to the P substrate if the
NPN is driven into saturation i.e. if base-collector junction is forward biased.
This current increases the NPN base current further decreasing the apparent
beta value, but it also modies the local substrate voltage which can, in turn
aect the circuit behavior. More generally, parasitic bipolar transistors, if they
are turned on, can create parasitic currents that can modify the circuit behavior
or performances.

25.6 Parasitic thyristor
When a PNP and a NPN are connected in a particular way, they implement a
dierent device: The Thyristor.
The thyristor is a trigger device that can be turned on but that requires
disconnecting the supply to turn o. This can be analyzed as follows. If the
NPN, for instance is o, its collector current is very small. This current is
multiplied by the PNP β and applied to the NPN base. It is then multiplied
by the NPN β. If the product of betas is lower than 1, the circuit remains in
the o state. Usually, the β curve for a bipolar transistor shows a signicant
value in a given current range and drops at high and low currents. Normally,
when the transistors are o, the currents are low enough so that the betas are
lower than 1. If for any reason, some current is injected, the collector currents
increase. If the collector currents are large enough for the product of betas
to be larger than one, the current increase and increase until it reached the
high value for which the product of betas falls below 1. At this point if the
current increases further, the betas decrease so the current decreases. If current
decreases, the betas increase so the current increases. This is a stable point.
The only way to stop the current is either turning the supply o or shorting
briey the base-emitter junction of one transistor.

Chapter 26
Substrate related issues
In integrated circuits, all the components are implemented by various physico-

chemical techniques inside a common substrate that achieves a mechanical and
electrical function.
The substrate is thick enough to allow wafer handling throughout the

manufacturing process.
The substrate is made from silicon for most products even though some
other possibilities exist such as gallium arsenide for very high frequency
applications or silicon carbide for very high temperature and radiation
hardened applications. Silicon On Insulator (SOI) can be used for some
high performance applications. In all but the SOI circuits, components
are isolated from each other by reverse biased diodes. In SOI, isolation
is performed by a dielectric layer.
All the components have then a parasitic capacitance to the substrate. This
does not really mean a parasitic capacitance to ground as it is the case on a
PCB with a ground plane. The reason for that is that substrate resistivity
is much higher than copper resistivity. So, all the parasitic capacitances in
fact connect to a resistive network that is connected to ground at some places.
This resistive network causes coupling between cells that are supposed to be
independent.
There is no general approach to the substrate coupling issue. However, in
any case, coupling is a three steps process:
Some cells inject parasitic signals into the substrate network.
The network carries these signals with attenuation.
Some cells receive parasitic signals from the substrate network.
Addressing substrate issues is usually dealing with the three steps:
Reducing injected parasitic signals. Generator side.
Optimizing attenuation by substrate. Transmission layer.
Reducing sensitivity to substrate signals. Receiver side.
Quotes are used since any cell can be both a generators and a receiver.
162
CHAPTER 26. SUBSTRATE RELATED ISSUES 163
Figure 26.1: Substrate attenuator
26.1 Reducing generation

Two kinds of parasitic signals are injected in the substrate.
DC coupled signals
AC coupled signals
26.1.1 DC coupled substrate signals

These are substrate current from devices like isolation diodes, parasitic bipolar
transistors and MOS transistors. Isolation diodes should be kept reverse biased,
bipolar transistors should be kept away from saturation to avoid DC currents to
be injected in the substrate. This is not always possible. For MOS transistors,
ionization current cannot be avoided in any case but it is usually low.
26.1.2 AC coupled substrate signals

These are substrate currents from reverse biased isolation junctions and other
parasitic capacitances. The injected currents amplitude is:
Proportional to the voltage swing.
Proportional to the parasitic capacitance.
Proportional to frequency.
There is not much to do with these parameters but the best must be done.
Probably the best solution is to choose a dierential structure. When two
signals of opposite phase inject in the substrate, the sum is theoretically zero.
This is not true practically as the two signals cannot be located exactly at the
same place and parasitic capacitances are not perfectly matched. However,
injected signal is signicantly reduced, often by an order of magnitude.
For routing parasitic capacitance, dierential signals inject less current.
In addition, a shielding by the rst metal layer or by poly can improve the
situation.
26.2 Optimizing attenuation

Basically, substrate attenuation results from a pi structure:
This attenuator has one coupling branch and two decoupling legs.
Each decoupling leg has to be connected to reference potentials of its cell

which can be on chip or outside, on the board. Decoupling leg impedance
completely depend on the case. Obviously, it has to be minimized.
Coupling branch resistance is more tricky. The only accurate solution is

a true 3D simulation. This kind of tools such as EZMod3D can be used
to extract substrate equivalent schematic for a given design. They can
also be used to nd some rules of thumb to deal with substrate coupling
at an early stage. that will be summarized later.
CHAPTER 26. SUBSTRATE RELATED ISSUES 164
26.2.1 Coupling resistance

Let's run some experiments using a 3D simulator to estimate coupling resis-
tance values:
26.2.1.1 Inuence of injector size
If a current is injected punctually at the surface of a large, homogeneous and

isotropic block of material with a given resistivity, constant voltage surfaces
are half spheres. The resistance between two sphere halves with radius R1 and
R2 (R2 > R1) is:48.10
26.2.1.2 Inuence of distance
26.3 Reducing sensitivity

There are basically two techniques to reduce the receiver sensitivity:
Use an intrinsically low sensitivity architecture such as a dierential cir-

cuit. The incoming parasitic signal couples identically to the two paths
of the dierential circuit and is signicantly attenuated.
Use of shielding for signal routing lines. Long signal lines should be
routed in metal 2 while a metal 1 shield should connect to the common
mode reference potential.
26.4 Thermal coupling

Substrate can inuence circuit behavior by thermal coupling. When power is
dissipated in a given volume inside a chip, heat diuses through silicon to nd
a path to the cold source. As a result, a thermal resistance exists between
power source and cold source. In addition, because of silicon specic heat,
distributed time constants slow down the diusion and a transient state exists
before steady state is reached.
Time constants range from tens of microseconds for a 100 mA capable device
to tens of milliseconds for a functional cell. They reach seconds for an entire
chip and tens of seconds for a large chip.
Chapter 27
Package considerations
In some applications, especially for very high volume very low cost, bare dice
are bonded directly on the PCB, but most ICs are used in a package that
interfaces the silicon die with the application PCB.
27.1 Package equivalent schematic

The package adds its own characteristics to the IC's characteristics:
Every connection adds some series resistance.
Every connection adds some series inductance.
Every connection exhibits some capacitance with respect to any other.
Every connection exhibits some mutual inductance with respect to any

other.
As a result, an exact equivalent schematic for a package is very dicult to

establish. In some cases, the companies providing the packages can supply
equivalent schematics. These are usually simplied models based on the fol-
lowing reasonable assumptions leading to simplication:
Screening eect takes place so parasitic capacitance mainly occurs be-

tween neighbor pins and eventually to die attach pad.
Coupling is loose so mutual inductance mainly takes place between neigh-

bor pins.
Experience has showed that simulating a circuit with series inductance requires
limiting Q factor in order to get reasonable simulation times or to prevent non
convergence. Connecting a 30 to 100 ohms in parallel to the several nanohenrys
inductance is a real must. If this resistor is not present in the package model,
it is strongly recommended to add it.
If no package model is available, a simplied one can be built using the
assumptions above. Capacitances can be extracted with a 3D simulator if
available. Inductance values can be estimated from wires and pins lengths
withe the rule of thumb of 1 nH/mm. Coupling between inductors is much
more tricky to guess and require 3D extraction.
165
CHAPTER 27. PACKAGE CONSIDERATIONS 166
27.2 Package thermal characteristics

Chapter 28
PCB considerations
The PCB around the IC achieves three basic functions:
Mechanical
Thermal
Electrical
28.1 Mechanical function

This may seem as an obvious function without any impact, but it is not really
the case:
For lead-less packages, if the PCB is bended, the solders are stressed and
may crack. Packages with leads handle this stress by transferring the
constraints to the exible leads.
If temperature is cycled, expansion coecient dierence between PCB

and package generates mechanical stress as well.
There is nothing to do in the designer's job with these issues, except may be
being aware and inuence the package selection when this kind of stress is
specied.
28.2 Thermal function

The heat resulting from power dissipation inside the chip has to nd a way out
to the ambient. This way goes through silicon, package and PCB to surround-
ing environment. For large packages, radiation and convection can take place
directly from the package itself but for tiny packages, most of the heat ows
through the PCB. The amount of copper around the IC has a direct impact on
the thermal resistance. In any case, it is a good practice to consider thermal
aspects from beginning.
167
CHAPTER 28. PCB CONSIDERATIONS 168
28.2.1 PCB Materials

There are dierent PCB dielectric materials.
FR4 is probably the most used material for PCBs
CEM3 exhibits a thermal conductivity is about 3 time higher than FR4

and can be helpful to manage signicant levels of power
For higher power levels, constructs with an aluminum substrate bring an

ecient solution but oer usually limited numbers of routing layers (1 or
2)
28.2.2 PCB thermal simulation

For signicant power levels, it can be a good practice to simulate the ther-
mal behavior using appropriate tools. At PCB level, all three heat transfer
mechanisms exist. 48.8
Simulating a PCB thermal behavior requires a tool that can handle these
three mechanisms. If enclosure is small and closed, heat transfer by conduction
is usually dominant. In that case, the problem is simpler and can be addressed
by simpler tool.
28.3 Electrical function

The PCB design of course inuences the IC operation as it adds series impedance,
parasitic capacitance, but also, as it is usually larger than the package, some
propagation related impedance transforms. It is a good practice to think, from
the beginning that the IC will be used on a PCB and that this PCB can inu-
ence the circuit performance. This allows both taking into account the PCB
in the chip design and giving guidelines for the PCB design. Again, dierent
materials bring specic benets in terms of impedance control or electrical loss.
Chapter 29
Test considerations
Integrated circuits manufacturing process even though extremely well con-

trolled never achieve 100% yield. Whatever the eorts, there are some chips
on each wafer that do not comply to the specication.
It is then mandatory to test all the chips on each wafer.
Most silicon chips are packaged, but in some cases, chips are assembled in a
module or directly on a PCB. In any case, again the manufacturing process
yiels is not 100%.
It is then mandatory to test packages or modules/PCBs.
For packages, test is very similar to chip test, only dierence is mechanical
interface. For modules or boards, test is specic and requires access points and
dedicated hardware.
29.1 Test philosophy

From a somewhat philosophical standpoint, it can be said that test does not
aim at selecting good parts, it aims at rejecting bad parts...
That may seem a detail since a part has to be good or bad!
But in fact, it is impossible to know if a part is good.
All what test can to is checking that no test fails.
But if a feature or a performance is not tested, the chip is bad and the test
does not reject it. One point of attention is that, the more robust the design
is, the more dicult the test is. When a cell is robust, even components with
degraded behavior do not impair operation. Such parts are prone to fail in the
eld but hard to detect during test unless special attention is paid, such as
pushing a cell to fault and measuring the eort it takes to do so.
169
CHAPTER 29. TEST CONSIDERATIONS 170
29.1.1 Tests selectivity

Experience teaches that some types of tests are more selective than others.
For instance, current consumption for an analog cell is a good indicator

of cell health.
Test of mixed signal circuits require programming to set the circuit in suitable
test modes. In turn, this requires that the integrated control circuit works ne.
In mixed signal circuits, digital control circuitry has to be tested before

analog stu
Before starting testing a chip, it must granted that the chip is properly con-
nected. This is particularly true for wafer probing where contacts have to be
checked.
29.2 Test sequence

For the reasons exposed above, test sequence is usually as follows:
Continuity checks: Since all pins normally have ESD protection devices,
checking these devices characteristics is a good indication that circuit pin
is connected to tester.
Digital test: Applying suitable patterns and activating the embedded test
circuitry allows validating the digital section.
Analog cells current consumption:
Analog cells bias point:
Eventually, functional test whenever possible or indirect test:
29.3 Test architecture

In order to observe and control signals inside the chip and make the test pos-
sible, dedicated hardware has to be added. This is a well known domain for
digital but something more or less similar can be implemented for analog. At
suitable places inside the chip, in test mode, switches eventually together with
buers allow controlling or observing a signal from outside through dedicated
test pins. There are mainly two possible architectures for that:
Centralized test hardware
Distributed test hardware
In the rst case, a large multiplexer with control logic connects test pins to
internal signals to be observed or controlled. In the second case, each reasonable
size cell in the circuit gets its own multiplexer and control logic. Distributed test
is much more exible and can be extended during design with only local impact.
It avoids the central multiplexer bottleneck and limits parasitic coupling. In
case a cell with embedded test is used two or more times in the circuit, test
hardware automatically expands.
Chapter 30
Reliability
Reliability of integrated circuits is an important issue that must be addressed

during the design and the implementation phases. There are mainly two origins
for ICs failure in time:
Oxide stress
Interconnections stress
Hot carriers
In this chapter, we don't consider surge events induced failures such as ESD,
or latch-up.
30.1 Oxide stress

Above the breakdown electric eld, the oxide is destroyed by the electrostatic
discharge that dissipates large amounts of energy, but below the breakdown
eld, conduction mechanisms exist that lead to oxide degradation and failure.
30.2 Interconnections stress

Interconnection metal layers and inter-layers vias are subject to a phenomenon
called electro-migration: Metal atoms move in the direction of the carriers
ow.
This phenomenon becomes signicant above a given current density that

depends on the metal alloy and on temperature.
This phenomenon is cumulative. Around a weak point, the current den-

sity is higher so atoms migrate until they reach a lower current density
area and the weak point becomes weaker and weaker until the connection
fails.
The failure rate depends on the current density and temperature according to
the following laws:
30.3 Hot carriers
171
Chapter 31
Basic integrated building blocks
These building blocks are simple transistor arrangements that have a particular
behavior that results from their topologies and from the transistor behavior and
performances that depend on sizing. Probably as much as 90% of integrated
circuitry is build from these basic building blocks. These basic building blocks
are:
Current mirrors
Dierential pairs
Voltage follower
Current mirrors turn an input current into an output current. Dierential

pairs turn an input voltage into an output current. Voltage follower turn an
input voltage into an output voltage. To complete the picture, designers need
an object that turns an input current into an output voltage. That's just an
impedance.
31.1 Current mirror

This block performs a current to current conversion. As stated in their respec-
tive sections, both the bipolar and the MOS transistors are transconductors.
Collector (Drain) current is controlled by Base-Emitter (Gate-Source) voltage.
Output resistance is large.
31.1.1 Diode connected transistor

If a transistor is connected so that input and output are shorted and if a current
is forced into that connection, feedback takes place:
If the transistor would draw less than the forced input current, input
voltage would increase causing output current to increase.
If the transistor would draw more than the forced input current, input
voltage would decrease causing output current to decrease.
This structure is usually called diode connected transistor or even diode

transistor. :
172
CHAPTER 31. BASIC INTEGRATED BUILDING BLOCKS 173
Figure 31.1: Diode connected transistors
Figure 31.2: Bipolar current mirror
Schematics are drawn for NPN and NMOS. For PNP and PMOS, principle
is the same, polarity is opposite.
The feedback permanently adjusts the transistor input voltage so that its
output current equals the forced input current. If a second transistor would be
driven with the same input voltage, it would generate the same output current.
This is the principle of the current mirror.
31.1.2 Simple current mirrors

31.1.2.1 Bipolar current mirror

k·T IC1
V BE1 = · ln
q IS1
V BE2 = V BE1
!
V BE2 IS2
IC2 = IS2 · exp k·T
= IC1 ·
q
IS1
Structural error

2
IC1 = IIN − IB1 − IB2 ' IIN · 1 −
β
2
The basic bipolar mirror structural error term is ε=
β . It must be noted
that if the mirror has more than one output, the structural error term is in-
N +1
creased. For N identical outputs, the structural error term is ε = . If
β
outputs are not all equal, the error term is more complex. Let's state that
there are N outputs and that output i has a current ratio ki with respect to
input. Then, the structural error term is:
N
1 X ki
ε= +
β i=1 β
Assuming that β is the same for all the transistor which is normally true
as they all operate at the same current density.
Random error In addition to the structural error, a random error exists.

This random error is generated by the bipolar transistors mismatch. The IS
mismatch is the major source of error term and current mismatch between
outputs while β mismatch impacts the error term.
Figure 31.3: Bipolar Current Mirror small signal model
Figure 31.4: MOS Current mirror
Output resistance If output voltage is swept, output current changes. Out-

V AF
put resistance is that of a bipolar transistor: RO = IC
Eect of saturation If output is saturated, current decreases for two rea-

sons, collector current dropping and base current rising. In a single output
mirror, it is generally not a big concern. In a multiple outputs mirror, if one
output is saturated, the current in all the other outputs decreases too because
the saturated transistor draws a signicant current that decreases the diode
transistor current.
Saturation occurs when the base-collector junction is forward biased i.e.
when the output voltage drops below the base voltage by a couple of times 26
mV.
Bandwidth If input current has an AC component superimposed to the DC

current, the output current has an AC component as well. The frequency
response can be calculated from a small signal equivalent schematic:
31.1.2.2 MOS current mirror
The MOS current mirror is build exactly as the bipolar version.
Structural error The major dierence with the bipolar mirror is that since
the gate current is negligible, there is no structural error term even if the
number of outputs is large.
Random error Just as for the bipolar mirror, a random error exists.
Output resistance Output resistance is not innite so an error term exists

if output voltage is not equal to input voltage.
Eect of saturation The word saturation is written between quotes here

as it relates to the MOS ohmic region of operation, not the saturated region.
This word is used here as it relates to the same phenomenon as for the bipolar
mirror. When output voltage is too low, the MOS enters the ohmic region
and the output current decreases. The dierence with the bipolar mirror is
that for the MOS version, the current reduction has a single origin, the change
in the MOS operating region. There is no increase in the gate current. For
that reason, in a multiple outputs mirror, even if one output is driven into
saturation, there is no impact on the other outputs.
Saturation occurs when the output MOS enters the ohmic region i.e. when
V DS ≤ V GS − V T . So, sizing a current source MOS is choosing its size so
W KP 2
that saturation voltage specication is met. As ID = L · 2 · (V GS − V T ) ,
W
this denes
L:
Figure 31.5:
Figure 31.6:
Figure 31.7:
W 2 · ID
=
L KP · V sat2
Bandwidth
31.1.3 Improved current mirrors

The simple current mirror suers from performance limitations that have been
detailed above. If these limitations cannot be accepted, some improved mirrors
exist:
31.1.3.1 Buered current mirror
This mirror addresses two issues:
The bipolar mirror structural error.
The bandwidth, for both the bipolar and the MOS versions.
31.1.3.2 Cascoded current mirror
This mirror addresses the output resistance issue.

The cascode current source is based on the cascode amplier49.5. The
current source transistor output connects to a common-base/gate stage. The
current source transistor output voltage is then fairly constant even if the
common-base/gate transistor output voltage changes.
31.1.3.3 Degenerated current mirror
This mirror addresses two issues:
Output resistance
Matching
If output voltage increases, because of the nite output resistance, the out-
put current increases. But then, the current in the resistor increases and the
voltage drop in the resistor increases. Then the base-emitter / gate-source
voltage decreases and this in turn reduces the current. This feedback eect in-
creases the output resistance. The eect on matching results from the fact that
integrated resistors can be easily made more accurate that transistors without
being very large. If the voltage drop in the resistors is large, current matching
mainly results from resistors mismatch.
Figure 31.8:
31.1.3.4 Combining improvements
The dierent improvements can be combined as needed to achieve a wide range

of performance levels. Cascoded buered degenerated current mirrors exist:
31.1.4 Eects of I.R drops

Current mirrors are often connected to the supply rails. Current in these rails
can be signicant so I.R drops can be millivolts very easily. If the diode tran-
sistor and the output transistor are connected to dierent points on the supply
rail, I.R drops create errors. And this error depends on the circuit consump-
tion that can change with signal or with operating mode. In order to avoid
this, current mirrors should be start routed on their own before connecting to
a single point on the supply rail.
31.1.5 Turning o current mirrors

A very common feature in ICs is an idle or sleep mode in which power con-
sumption is very low. This feature is usually achieved by turning o the unused
circuitry. At a basic level, turning o a functional block requires very often
turning o a current mirror. At rst sight, it seems that this is a simple task,
but especially for MOS circuits, it is not the case. One could think that turning
o the input current does turn o the outputs.
For bipolar circuits this is true as if one output would not be completely
o, it would draw some base current that would normally be larger than
the input leakage. As a result, that would turn o the mirrors.
For MOS circuits, when the input current is turned o and only leakage
is fed in the input, the VGS decreases. As the VGS decreases, the diode
connected MOS current decreases too until it reaches the input leakage
level. This occurs for a given non zero VGS. Output MOS transistors
exhibit some VT mismatch with the diode MOS so they may have some
drain current. Additional issue is that output currents turn o quite
slowly.
A concern with this matter is that simulation may not show it precisely. It
must be checked very carefully. A good practice is to force 1 nA or so in the
input and perform some Monte-Carlo runs to check the eect. During such
analysis, the designer should mind the simulator gmin parameter that can hide
the eect. The gmin value should be set to a suitable value, down to 1E-16 or
so.
The safe method to turn o a MOS mirror is not only to turn o the input
current but also to short the gate bus to the common rail with a switch that
is turned on when the mirror has to be switched o. Then, the input leakage
creates a negligible voltage drop across the switch and the mirrors cannot draw
any signicant current. Another benet of this structure is a very fast turn
o time. To start the mirror, the shorting switch must be turned o while the
mirror input current is turned on.
Figure 31.9: Dierential pair schematic
Figure 31.10: Dierential pair small signal schematic
Figure 31.11: Voltage follower
31.2 Dierential pair

This block performs a dierential voltage to current conversion. A dierential
pair is built from two transistors with emitters/sources connected together and
to a current source.
The sum of currents is kept constant while the bases/gates voltages dier-
ence controls the currents dierence.
31.2.1 Small signal analysis

The small signal equivalent schematic is:
The circuit is completely symmetrical so the voltage on the emitters con-
nection is equal to the average of the two input voltages.
31.2.2 Large signal analysis

31.3 Voltage follower
This block performs a voltage to voltage conversion with a voltage gain below
1. It is built from a common collector (common drain) congured transistor
together with a current source.
31.3.1 Small signal analysis

31.3.2 Large signal analysis
Chapter 32
Tentative analog functions

classication
When an analog designer is asked how many analog cells can exist, the answer is
often a large but very inaccurate number... But when the same analog designer
is asked to list analog functions, he has hard time nding more than 15...
Let's make an attempt to dene a list of analog functions. First of all, we
may dene two classes:
The signal generators. These blocks have a supply, of course, and an

output but no input.
The signal modiers. These blocks have a supply, of course, an input and
an output. The output depends on the input.
32.1 Signal generators

Among signal generators, one can nd two categories:
DC signal generators
Time varying signal generators
32.1.1 DC signal generators

In this category, there are mainly three members:
Voltage generators
Current generators
Arbitrary resistance generators
32.1.2 Time varying signal generators

In this category, there are mainly two sub-categories
Periodic signal generators
Non periodic signal generators
178
CHAPTER 32. TENTATIVE ANALOG FUNCTIONS CLASSIFICATION
179
32.2 Signal modiers

This large class include many categories among which:
Ampliers
Filters
Modulators
Demodulators
A-D and D-A converters
32.2.1 Ampliers
This is probably the most common category. There are many types of ampliers
dened either by their bandwidth or by their architecture or by some particular
feature.
32.2.1.1 DC coupled ampliers
32.2.1.2 Wide band ampliers
32.2.1.3 Narrow band ampliers
32.2.1.4 Low noise ampliers
32.2.1.5 Power ampliers
32.2.2 Filters
Filtering is a very common way of improving signal to spurious ratio.
32.2.3 Modulators and Demodulators

Modulation-Demodulation is a common way of packaging signals when it
comes to store or transmit them. For simple waveforms like a sine-wave or
a square wave, there are few parameters to play with. More complex modu-
lation schemes can be used, mainly in the digital world, resulting in complex
waveforms. These are not addressed here.
32.2.3.1 Sine-wave modulation
A general sine wave is described by the following expression:
V = A · sin (2 · π · f · t + ϕ) + B
A is signal amplitude
B is signal oset
f is signal frequency
ϕ is signal phase
Any of these signal parameters can be modulated.

CHAPTER 32. TENTATIVE ANALOG FUNCTIONS CLASSIFICATION
180
32.2.3.2 Square wave modulation
A square wave is dened by its amplitude, its frequency and its duty cycle.
Any of these parameters can be modulated.
32.2.4 A-D and D-A converters

This can be seen as a particular modulators-demodulators category.
Part III
Design Examples
181
Chapter 33
Square root circuit
33.1 Square root circuit architecture

Let's design a circuit architecture that performs the square root function. The
output voltage should be equal to the square root of the input voltage. Available
blocks for creating our circuit are only the four arithmetic operators.
This might seem an academic exercise, and may be it is, but it will show
an approach that proved to be ecient in many cases and it will question the
specication, a very common situation. The key is to set up a general method
for low frequency analog circuits synthesis.
For simplicity, let's assume that input and output voltages are positive and
let's ignore the considerations on input and output resistances and voltage
ranges. The transfer function writes:
√
V OU T = V IN
To be exact, for units consistency reasons, we should write:
V OU T √
= V IN
A
1
Where A is a dimensional constant. A = 1V 2
As VIN is supposed to be positive, we can write:
V OU T 2
= V IN
A2
A very common approach when a circuit must achieve such a condition is
to rewrite the equation in another way:
V OU T 2
− V IN = 0
A2
or
V OU T 2
V IN − =0
A2
When a dierence must be equal to zero, a very common implementation
is to create a loop with a large gain so that the input dierence is constantly
kept very small.
182
CHAPTER 33. SQUARE ROOT CIRCUIT 183
Figure 33.1: Square Root circuit
If amplier has gain G and oset VIO, this circuit operation can be written
as:
V OU T 2

V OU T = G · V IN − + V IO
A2
Solving for VOUT brings:
√
−A2 ± A4 + 4 · A2 · G2 · V IN + 4 · A2 · G2 · V IO
V OU T =
2·G
Which can be simplied, assuming VOUT is positive:
√
−A2 + A4 + 4 · A2 · G2 · V IN + 4 · A2 · G2 · V IO
V OU T =
2·G
It can be checked that if G is large and VIO is small:
√
V OU T ' A. V IN
33.2 Square root circuit sizing

Error is expressed as the dierence between what the circuit does and
what it is supposed to do:
√ √
√ −A2 + A4 + 4 · A2 · G2 · V IN + 4 · A2 · G2 · V IO − 2 · A · G · V IN
ε = V OU T −A· V IN =
2·G
It can be checked that the error is expressed in volt and that the formula
is consistent to volts.
This circuit has only two sizable parameters : G and VIO

CHAPTER 33. SQUARE ROOT CIRCUIT 184
These sizable parameters impact the circuit accuracy.
We need two equations to solve in order to calculate the two sizable parameters.
So our specication so far is not sucient to size the circuit. We need two
specication items related to accuracy.
1. The error can be mentally separated in two terms, one that applies when
input is zero, one that depends on input voltage.
V IN = 0

For :
√
−A2 + A4 + 4 · A2 · G2 · V IO
ε0 = V OU T =
2·G
When VIN gets large :

√ −A2
εmax = V OU T − A. V IN =
2·G
So, we need two error specication items:
Error at maximum input voltage

−A2
εmax. It is required to size the gain:
G≥ 2·εmax
Error at zero input ε0.It is required to size the oset provided the fact
the gain has been sized.
Chapter 34
MOS Voltage follower
This is a very common stage, but here we will address its sizing using the de-
pendency graph method to demonstrate it. This method is helpful in situations
where there are many variables to size.
Schematic shows a number of parameters. Some of these come from speci-
cation:
Load capacitance
Bandwidth
Some are dened by process to be used:
VT and KP
Some are variables to size:
MOS W and L
Current source value
Figure 34.1: MOS Follower
185
CHAPTER 34. MOS VOLTAGE FOLLOWER 186
Figure 34.2: Follower Small signal model
KP, VT
CGS
W, L
gm
VIN
IBIAS CLOAD
The small signal model will be used:

First, all the equations that can be dened are written:
Then, all the variables and parameters of these equations are placed in
boxes to draw a graph
Finally, links between these data are plotted as arrows.
This work can be made easier using a graph plotter such as dot
Here is the dot script:
And here is the resulting graph:
What does this graph show ?

It shows that some boxes have only departing arrows, some have only ar-
riving arrows, some have both. It also shows loops.
Chapter 35
Constant gm cell
35.1 Problem to solve

Open loop ampliers gain depends on a resistor value and a trans-conductance
value. Achieving a gain that does not depend on process nor on temperature
or supply voltage requires that the trans-conductor is biased by a so called
Constant gm Bias Cell
35.2 Problem formalization

Trans-conductor equation is:
Trans-conductance is:
35.3 Solution
If two trans-conductors with sizes 1 and M are biased at the same current I:
Now if the arrangement is such that:
Then
and
Now some general math properties:
and
To be continued. . . 1.3 Application
35.3.1 1.3.1 Case bipolar transistor

35.3.2 1.3.2 Case MOS transistor
Solving for or leads to two possible values for I:
This, in turn gives two possible values for gm:
Choosing between the two requires looking at VGS2 which can have two
values:
Since, by hypothesis, M > 1, the + sign leads to VGS2 < VT which is not
compatible with the assumed operation above threshold.
So, the only solution is the sign which gives a VGS2 above VT. The result
is:
In particular, an interesting result is for M = 4:
187
Chapter 36
Band-gap reference voltage

generator
The band gap reference idea was created by Bob Widlar. The beauty of this
concept is that it is based on an intrinsic material property, not on a process
parameter.
Important Notice: Because the lateral transistors base-emitter junction is

mainly located near the silicon surface, the VBE versus temperature charac-
teristics of lateral transistors neither complies with theory nor is consistent
from wafer to wafer. Designers are strongly advised that using lateral PNPs to
implement band-gap reference voltage generators leads to poor and inconsis-
tent results. The author had to help a designer in the case of an inconsistent
band-gap using lateral PNPs. The choice was made to use the vertical PNP
that was not modeled in the process but that gave better results!
36.1 Some band-gap architectures

The idea behind the band-gap reference voltage generator is to sum up two
values, one with a positive temperature coecient, one with a negative tem-
perature coecient. Properly choosing the amount of each value in the sum
can result in a zero temperature coecient. The values to be summed up
can be either voltages or currents. Voltages sum up when connected in series.
Currents sum up when connected in parallel.
36.1.1 Positive temperature coecients values

One naturally positive temperature coecient is the PTAT (Proportional To
Absolute Temperature) voltage. It can be turned into a current by being
applied to a resistor.
36.1.2 Negative temperature coecients values

One naturally negative temperature coecient is the forward voltage across a
PN junction. It can be turned into a current by being applied to a resistor.
188
CHAPTER 36. BAND-GAP REFERENCE VOLTAGE GENERATOR 189
36.1.3 Architectures summing up voltages

36.1.3.1 The original Widlar shunt reference
36.1.3.2 The Brockaw architecture
The two branches version The initial Brockaw version uses two branches
for the reference and error amplier
The three branches version This is a modied version with a third branch
that both increases loop gain and reduces structural error.
Architectures summing up voltages are not suited for low voltage operation
since they result in a 1.2 V value for zero temperature coecient. This was the
major reason for developing current based architectures.
36.1.4 Architectures summing up currents

Chapter 37
Linear Voltage regulator
From a very general standpoint a voltage regulator is a circuit that is intended

to deliver a constant voltage to a variable load from a variable input. The
general priciple to reach this goal consists in creating a voltage divider with
the input voltage source, two impedances and the load impedance. The input
source and the load are usually dened by the application, the regulator design
denes the two additional impedances. Depending on the case, only one of the
impedances is controlled or both are controlled.
If input voltage Vin can vary from Vmin to Vmax and load current Iout
can vary from Imin to Imax, output voltage being xed at Vout, we can write:

V out
V out = V in − Z1 · Iout +
Z2

Z1
V out · 1 + = V in − Z1 · Iout
Z2
V in − Z1 · Iout
V out = Z1
1 + Z2
If only impedance Z1 is controlled, the regulator is said to be series type.
If only impedance Z2 is controlled, the regulator is said to be shunt type. If
both are controlled, regulator is said to be compound type. These regulator
types have intrinsic properties. Let's review some of these characteristics.
37.1 Eciency
Load power can vary from P min = V out · Imin to P max = V out · Imax
37.2 Operating quadrants

A series regulator can only source current for a positive output voltage as there
is no path to sink current. It is a single quadrant regulator.
Figure 37.1:
190
CHAPTER 37. LINEAR VOLTAGE REGULATOR 191
A shunt or a compound regulator can source and sink current for a given
output voltage. They are two quadrants regulators.
For the compound regulator, if impedance Z2 connects to another voltage
source with opposite sign to Vin, the regulator is a four quandrant one, capable
of sourcing or sinking current from a positive or negative voltage.
37.3 Short circuit protection

The series and compound regulators can deliver a very large short circuit cur-
rent if no additional circuitry is provided to limit it. The shunt regulator is
intrinsically short circuit protected by xed impedance Z1.
Chapter 38
Sigma-Delta Modulator
Sigma-Delta modulators are among the most mysterious circuits. We will go

through these circuits, trying to give a real understanding of how they work
and how they can be sized using a small signal analysis.
38.1 An intuitive approach

If a digital multimeter shows an unstable least signicant digit like the following
table:
Values
1.755
1.754
1.754
1.754
1.754
1.755
1.754
1.754
1.755
1.754
One can just think display is unstable. But one can analyze the data and
gure out that value 1.754 appears 70% of time and value 1.755 30% of time.
Intuitively, one can feel that actual value is closer to 1.754. One can easily
compute the average of these ten measurements. It can be said that 1.7543 is
the most probable measurement value.
This is one of the basis of Sigma-Delta modulators: Performing many mea-

surements with a limited accuracy and computing an average value.
How valid is this approach?

This approach is fully valid within two conditions:
The measurement noise must be white.
The noise amplitude distribution must be uniform or gaussian.
Then averaging the values actually improves accuracy!
192
CHAPTER 38. SIGMA-DELTA MODULATOR 193
38.2 Delta modulators

Historically, in some situations of slowly varying high resolution measurements,
the idea came that instead of transmitting the full measurement every time,
only the dierence with previous value could be transmitted. This can reduce
the amount of data signicantly. In the worst case, if data change full range at
every measurement, there is no gain, but there is no loss. A delta modulator
in fact encodes the input signal time derivative. Hence the modulator name.
On the receiver side, an integrator can reconstruct the input signal. A Delta
modulator can be implemented this way:
Figure 38.1: Delta modulator
Digital output is converted back to analog and integrated. Input minus

integrator output is converted to digital to generate the output. The loop
tends to bring the dierence to zero, forcing the integral of output to be equal
to input. Then, output is the input derivative.
There are two major issues with this approach:
The receiver side integrator has to be initialized when transmitter side

input is forced to zero
Any oset may end up saturating the receiver integrator. This does
require periodic reset.
A possible solution is to insert an analog integrator at the input:
Figure 38.2:
The integrator can be initialized while input is forced to zero, but the oset
issue is still a concern.
Since the two integrators and the dierence amplier are linear functions,
they can be swapped and then only one integrator is required!
Figure 38.3: Sigma-Delta modulator
No more saturation!
38.2.1 Modulator number of bits

So far, no mention to ADC / DAC number of bits. This point will be ad-
dressed later. From now, we will consider only one bit. Then, ADC becomes
a comparator and DAC has only two values to generate. This is the simplest
possible implementation.
38.3 First order modulator

Now is time for going deeper in modulator operation. Here is the schematic of
a single bit rst order low-pass Sigma-Delta modulator:
Figure 38.4: First order Sigma-Delta modulator
X1
X2
VSIN In+ INT X6
Out In+
In- D Q
X4 In-
CLK
VCLK
X5
X3
FB Aout Din
1 bit DAC
Input signal is a voltage and so is DAC output. Integrator output is a

voltage. Comparator output is a dimensionless digital signal even though is
if gured by a voltage. So, comparator gain expresses in V −1 . D ip-op
output is a digital signal as well. DFF gain is dimensionless. DAC receives a
dimensionless signal and issues a voltage. Its gain has dimension V.
This modulator is a loop. So, as everytime we see a loop, question is:
Is that loop stable?

In order to answer this question, we have to analyze the open loop gain.
Loop is built from 4 blocks
Dierential input Integrator
Comparator
D ip-op
One bit DAC
Loop gain is the product of all four blocks transfer functions, taking into ac-
count the fact that loop closes on integrator negative input.
38.3.1 Dierential integrator

1
Dierential integrator Laplace transfer function is: Hint(s) = τ.s where t is
time constant. This transfer function is dimensionless as required.
38.3.2 Comparator
Comparator transfer function is more unusual. Output peak to peak is con-
stant, 1 without dimension, while input peak to peak can be anything provided
the fact it crossed zero. In addition, comparator adds some delay tdc. Then,
1 −tdc.s
comparator transfer function writes: Hcomp(s) = VP P (IN T ) .e . This
−1
transfer function dimension is V as required.
At this point, we have no idea about Vpp(INT) but we can say that in a
given situation, doubling integrator time constant divides Vpp(INT) by two.
A −tdc.s
In other words: Hint(s).Hcomp(s) = s .e where A is some constant with
dimension is V .s−1 .
−1
38.3.3 D ip-op
D ip-op transfer function is even more unusual. Output peak to peak, 1
without dimension is equal to input peak to peak. Gain module is 1. Phase
is a bit more tricky: If D changes just before clock edge, delay is negligible.
If D changes just after clock edge, delay is one clock period (assuming in-
put frequency is smaller than clock frequency). On average, since ether is no
phase relationship between D and CLK, delay is half a clock period. D ip-
s
op transfer function writes: Hdf f (s) = e− 2.F CLK . This transfer function is
dimensionless as required.
38.3.4 One bit DAC

DAC peak to peak input is 1 without dimension. DAC output is -FS /
+FS volts. DAC delay is tdd. DAC transfer function writes: Hdac(s) =
2.F S.e−tdd.s . This transfer function dimension is V as required.
38.3.5 Open Loop gain

Open Loop gain writes: Hloop(s) = −Hint(s).Hcomp(s).Hdf f (s).Hdac(s) =
s 1
− As .e−tdc.s .e− 2.F CLK .2.F S.e−tdd.s = −2.A.F S. 1s .e−(tdc+tdd+ 2.F CLK ).s . Note
that loop transfer function is dimensionless as required.
Open loop gain shows:
A constant term: −2.A.F S that is expressed in s.
An integrator:
1
s
A delay that is the sum of all loop delays: tdc + tdd + 1

2.F CLK
1
Loop gain module varies with frequency as
f . Gain module value is 2.A.F S
1
at f= 2.π .
Loop gain phase is − 3.π

2 at
π
low frequencies (−
2 for integrator and −π for
sign -)and decreases with frequency. At some frequency, phase can reach −2.π .
If gain module is larger than 1 at that frequency, the loop will oscillate.
At what frequency can this occur?

The only possible frequency is value FOSC such that total delay causes a
π
phase shift so that total phase is 2.π . This means that total delay must be
2
equal to one quarter of FOSC period:
1 1
tdc + tdd + =
2.F CLK 4.F OSC
Then:
1
F OSC = 1
4.(tdc + tdd + 2.F CLK )
If propagation delays in comparator and D ip-op are much shorter than clock
period and are neglected:
F CLK
F OSC '
2
Finally, if loop gain is large enough, loop is unstable and oscillates at half the
clock frequency. If no signal is applied at input, output should be a square
F CLK
wave at .
2
This example shows that small signal analysis can be used to predict some
behavior of a non linear mixed signal system. Now, it's time to implement this
modulator so as to simulate it.
38.4 Implementation
In order to simulate the modulator operation, LTSPICE can be used. We'll
now detail how the building blocks are made. The goal is that anyone can run
this experiment since LTSPICE is a free tool.
38.4.1 Integrator implementation

The idea is to use a controlled current source to convert dierential input
voltage into a current and to integrate this current in a capacitor. If controlled
current source transconductance is gm and capacitor value is C, then integrator
C
time constant is τ =
gm . Choosing gm = 1 results in time constant being
equal to C value. In order to simplify usage, C value is assigned parameter
value T that can be passed to the integrator from the schematic using it.
Figure 38.5: Integrator subcircuit
Out
G1 C1
In+
In- {T}
1
Figure 38.6: Integrator instance with specied time constant
X1
In+
Out
In-
T=10E-6
38.4.2 Comparator
Comparator uses LTSPICE behavioral voltage source with function u(x) that
generates a unity step at x=0. Some gain in front somewhat improves switch-
ing.
Figure 38.7: Voltage comparator
DIFF OUT
E1 B1
In+
In-
1000 V=u(V(DIFF))
38.4.3 D Flip-op
D ip-op uses just LTSPICE digital dop. For simplicity, set and reset pins
are forced inactive, inverted output is dropped and digital levels are referred
to ground.
Figure 38.8: Embedded D ip-op
A1
PRE
D D Q Q
CLK CLK Q
CLR
38.4.4 One bit DAC

One bit DAC receives a dimensionless digital signal [0,1] represented by a volt-
age [0 V,1 V] and translated it in an output voltage [-FS V, FS V]. FS stands
for Full Scale.
38.5 Simulation
Simulation requires some sizing. Here are the parameters:
Integrator time constant: 1µs

Figure 38.9: One bit DAC
Aout
E1
Din
{2*fs}
V1
{-fs}
Input signal: 0.8VP ; 2kHz

Clock: 10M Hz
DAC output: ±1V
38.5.1 Self oscillation frequency

For this simulation, input is forced to zero. Signals shown here are clock (top)
and output (bottom):
Figure 38.10: Single bit First Order Sigma-Delta modulator oscillation

V(clk)
1.6V
1.4V
1.2V
1.0V
0.8V
0.6V
0.4V
0.2V
0.0V
-0.2V
-0.4V
-0.6V
V(out)
1.5V
1.4V
1.3V
1.2V
1.1V
1.0V
0.9V
0.8V
0.7V
0.6V
0.5V
0.4V
0.3V
0.2V
0.1V
0.0V
-0.1V
-0.2V
-0.3V
-0.4V
-0.5V
Simulation conrms that with no signal at input, this modulator oscillates

at half the clock frequency. And this conrms the validity of the small signal
analysis even though it looks strange to use such an analysis with strongly non
linear and time discontinuous functions.
Now, if we look at clock and feedback signal (DAC output):
Figure 38.11: Single bit First Order Sigma-Delta modulator oscillation Feed-
back
V(clk)
1.6V
1.4V
1.2V
1.0V
0.8V
0.6V
0.4V
0.2V
0.0V
-0.2V
-0.4V
-0.6V
V(fb)
1.2V
1.0V
0.8V
0.6V
0.4V
0.2V
0.0V
-0.2V
-0.4V
-0.6V
-0.8V
-1.0V
-1.2V
Feedback signal is obviously at the same frequency as output signal but its
values range from -FS to + FS, here ±1V . Note that average value is 0V, the
input value.
Now, what happens if a time dependent signal is applied at input ?

Small signal analysis is no longer valid, but simulation is:
Figure 38.12: Single bit First Order Sigma-Delta modulator operation

V(in)
1.0V
0.8V
0.6V
0.4V
0.2V
0.0V
-0.2V
-0.4V
-0.6V
-0.8V
-1.0V
V(fb)
1.2V
1.0V
0.8V
0.6V
0.4V
0.2V
0.0V
-0.2V
-0.4V
-0.6V
-0.8V
-1.0V
-1.2V
Feedback signal frequency and duty cycle vary with signal value while the
loop tries to minimize dierence between input and feedback. It cannot do it
exactly since feedback has only two values but it does it as well as possible, on
average. Here are input signal and low pass ltered output signal:
Figure 38.13: Single bit First Order Sigma-Delta modulator input and ltered
feedback
V(in) V(lpf_fb)
1.0V
0.8V
0.6V
0.4V
0.2V
0.0V
-0.2V
-0.4V
-0.6V
-0.8V
-1.0V
Filtered feedback signal looks pretty much like input with a slight atten-
uation and a signicant phase lag. Now, if we look at ltered feedback and
ltered input using the same lter:
Figure 38.14: Single bit First Order Sigma-Delta modulator ltered input and
feedback
V(lpf_fb) V(lpf_in)
800mV
600mV
400mV
200mV
0mV
-200mV
-400mV
-600mV
-800mV
The two signals are very similar. In fact, both attenuation and phase lag
are caused by the lter. At most can we see some residual high frequency
dierence near the top and bottom of signal.
So, here we are: The modulator oscillates but it's output bit stream low-
pass ltered value is a good image of input signal value.
Now, we have to dig a bit deeper to understand operation better. First,

lets look at integrator output:
Figure 38.15: Integrator output

V(int)
200mV
160mV
120mV
80mV
40mV
0mV
-40mV
-80mV
-120mV
-160mV
-200mV
0.0ms 0.1ms 0.2ms 0.3ms 0.4ms 0.5ms 0.6ms 0.7ms 0.8ms 0.9ms 1.0ms
Integrator output is a noisy sine wave!
What about this signal spectrum?
Figure 38.16: Integrator output spectrum

V(int)
-20dB
-30dB
-40dB
-50dB
-60dB
-70dB
-80dB
-90dB
-100dB
-110dB
-120dB
-130dB
-140dB
30KHz 60KHz 90KHz 120KHz 150KHz 180KHz 210KHz 240KHz 270KHz 300KHz
In this spectrum, we can clearly see the 2 kHz signal near the left side
(mind the linear horizontal scale), and the entire spectrum looks more or less
like white noise. In fact, the loop tries to make feedback equal to input, but
it can't since feedback has only two values and changes only on clock edges.
Sometimes feedback is higher than input, sometimes lower and this occurs ran-
domly. Ultimately decision is made by comparator and is based on integrator
output. So it's no big surprise that integrator is somewhat random.
What about the output spectrum?

Of course, we van look at it, but before that lets try to guess.
How does comparator and DFF change this white noise plus sine wave into
a digital signal? Not an easy guess!
Figure 38.17: Bit stream spectrum

V(out)
0dB
-10dB
-20dB
-30dB
-40dB
-50dB
-60dB
-70dB
-80dB
-90dB
-100dB
-110dB
-120dB
-130dB
-140dB
1KHz 10KHz 100KHz 1MHz
Now, let's think again: Integrator and DAC are analog blocks. It's easy
to express their output from their input. So, we can express their input from
their output! If integrator output is white noise, integrator input should be
a noise with a +6dB/octave slope so that after integration (-6dB/octave) it
is at. So, DAC output should be a +6dB/octave noise. And so should be
the DAC input since its transfer function is just a delay. Then, output bit
stream spectrum should be +6dB/octave, just what it takes to compensate for
the integrator transfer function. Let's have a look using LTSPICE FFT (Fast
Fourier Transform):
As expected, output spectrum shows a positive slope. Even though dicult
to measure, it looks close to +6dB/octave (+20dB/decade). In addition to
noise spectrum shows signal at 2 kHz (mind the log horizontal scale)
Note: Special attention should be paid to FFT settings to plot a digital
signal spectrum. Samples should be taken only when signal is stable, between
transitions to avoid artifacts. For this reason, they are taken on inactive clock
edges. This can be managed either by changing time range for FFT data or by
changing rst clock edge position.
So, this explains why, if we lter output with a low-pass lter at say 10 kHz,
we get the signal with a very good signal to noise ratio that can be translated
in a large number of equivalent bits.
What should be the low-pass lter order?

If we use a rst order lter, noise will be white above cuto frequency and
high frequency noise will impair performance. If we use a second order lter,
only noise below cuto frequency will aect equivalent number of bits. Filter
order should be higher than integrator order.
38.5.2 Modulator saturation

What happens if input amplitude is increased to 1V?
This amplitude is the maximum the DAC can compensate for.
38.5.3 Eect of oset

Now what if we have no input signal and if integrator shows some oset?
38.5.4 Eect of time constant

38.5.5 Eect of clock frequency
38.6 Second order modulator
When a second order integrator is used, one thing changes radically.
38.7 Third order modulator

The goal here is to size a third order low pass Sigma-Delta ADC to meet the
following target specication:
Ref Parameter Min Typ Max Unit
√
I1 Input noise density 100 kHz to 420 kHz 60 nV / Hz
I2 Input voltage 1.3 Vp
T1 Third harmonic distortion -45 dB
38.8 Architecture
As a Sigma-Delta modulator is chosen architecture work is limited to choosing
modulator order, clock frequency and some implementation details.
A Sigma-Delta modulator is a chaotic self-oscillating pulse width modulator.
Output is a digital signal carrying the information in the duty cycle.
Output contains signal and a continuous spectrum random noise.
38.8.1 Clock frequency

The clock frequency denes the spurious response that has to be suppressed by
the analog anti-aliasing low-pass lter. The higher the clock to signal frequency
, the higher the attenuation for a given lter order. The system usually requires
the data to be issued at a given rate. This does not really impact the modulator
design even though it is easier to implement the clock to data-rate ratio as a
power of two.
38.8.2 Modulator order

The modulator order denes the noise shaping transfer function and then the
noise level versus frequency for a given clock frequency. Modulator order must
be two or more for the chaotic oscillation to take place. The higher the order,
the stronger the noise shaping slope, so the lower the input equivalent noise.
In order to choose properly both the modulator order and the clock fre-
quency, a simplied schematic can be used:
Figure 38.18:
Where:
Q is the Quantizer noise spectral density.
k is the Quantizer gain.
A (s) and B (s) are two lter transfer functions.
OUT is the Quantizer output.
D is the DAC gain.
From the circuit topology we can write:
OU T = k · (A (s) · V IN − B (s) · D · OU T + Q)
Solving for OUT gives:
A (s) · V IN + Q
OU T = k ·
1 + k · D · B (s)
Not surprisingly, output contains signal and noise.

Equivalent ADC input quantization noise is equal to output quantization
noise divided by closed loop gain:
Q
eQN in =
A (s)
Total noise at a Sigma-Delta ADC input not only contains quantization

noise but also electrical noise from components.
eN in = eQN in + eEN in
Of course, both noises must be considered during the design.
38.8.2.1 Closed loop gain
Closed loop gain is the ratio between output signal and input signal assuming
no noise:
A (s)
GCL = k ·
1 + k · D · B (s)
Usually, GCL is chosen to be a low-pass transfer function:
1
GCL (s) = G0 ·
1 + a1 · τ · s + a2 · τ 2 · s2 + a3 · τ 3 · s3 + · · · + aO · τ O · sO
Where O is the lter order. The ai coecients values dene the frequency
response type.
38.8.2.2 Noise transfer function
Noise transfer function is the ratio between output and quantization noise
assuming no signal:
1
NTF = k ·
1 + k · D · B (s)
Usually, GCL is chosen to be a high-pass transfer function:
τ O · sO
N T F (s) = N 0 ·
1 + a1 · τ · s + a2 · τ 2 · s2 + a3 · τ 3 · s3 + · · · + aO · τ O · sO
Where O is the lter order. The ai coecients values dene the frequency
response type.
Note: NTF and GCL share in common the same denominator.
38.8.2.3 Solving
Now let's write the two lters transfer functions as ratios:
N A (s)
A (s) =
DA (s)
N B (s)
B (s) =
DB (s)
From that, we can rearrange GCL and NTF:
N A(s) N A(s)
DA(s) DA(s) · DB (s)
GCL = k · =k·
1+ k·D· N B(s)
DB(s) DB (s) + k · D · N B(s)
DB(s)
1 DB (s)
NTF = k · N B(s)
=k·
1+k·D· DB (s) + k · D · N B (s)
DB(s)
Identifying these expressions with the previously dened low-pass and high-
pass target transfer functions:
N A(s)
1 DA(s) · DB (s)
GCL (s) = G0· = k·
1 + a1 · τ · s + a2 · τ 2 · s2 + a3 · τ 3 · s3 + · · · + aO · τ O · sO DB (s) + k · D · N B(s)
DB(s)
O O
τ ·s DB (s)
N T F (s) = N 0· = k·
1 + a1 · τ · s + a2 · τ 2 · s2 + a3 · τ 3 · s3 + · · · + aO · τ O · sO DB (s) + k · D · N B (s)
Solving leads to:
N0 = k
DB (s) = τ O · sO
1 + a1 · τ · s + a2 · τ 2 · s2 + a3 · τ 3 · s3 + · · · + aO−1 · τ O−1 · sO−1

N B (s) =
k·D
DA (s) = DB (s)
N A (s) = N A0
G0 = N A0 · k
38.8.3 Quantizer
In the above expressions, Q is the Quantizer quantization noise spectral density.
It depends on the Quantizer number of bits and sampling frequency.
Multi bit Quantizer For a multi bit Quantizer, calling V range the input
voltage range and N the number of bits, the quantization step q is:
V range
q=
2N − 1
If noise at the Quantizer input exceeds one quantization step q, feedback brings
it back within. So, peak to peak noise at Quantizer input is:
VN = q VP P
In this case, Quantizer gain is:
OU Trange 2N − 1 1
k= = N =
INrange (2 − 1) · q q
So:
k·q =1 (38.1)
If the sampling frequency is Fs, noise power spreads over [-Fs;+Fs]. Assum-
ing a triangle shaped quantization error, noise spectral density is:
q
Q = √ (38.2)
6 · Fs
Single bit Quantizer For a single bit Quantizer, there is no added eect
if the Quantizer input swing exceeds q. So, the Quantizer input swing is not
dened by the Quantizer itself, but by the modulator sizing.
Since the signal frequency is much lower than the noise frequency, the single
bit Quantizer fast varying output duty cycle depends on the slow input signal
value. The larger the noise, the larger the signal range for the output duty cycle
to go from 0 to 1. Then signal gain is dened by noise. In fact, Quantizer signal
transfer characteristic depends on noise amplitude distribution. If distribution
is uniform, transfer characteristics is linear and gain is:
1
k= (38.3)
2 · VN P k
Actual noise amplitude distribution can dier from uniform and will aect
transfer characteristic linearity. However, average gain over input swing does
not change signicantly.
Then, even for a single bit Quantizer 38.1 and 38.2 can be considered true.
Quantization noise So, whatever the Quantizer number of bits, combining

38.1 and 38.2 brings:
1
k·Q = √ (38.4)
6 · Fs
Figure 38.19:
Quantizer number of bits If a multi-bit Quantizer is to be used, both

the Quantizer and the feedback ampliers must achieve a good linearity. This
constraint disappears for single bit implementation. For this reason, the single
bit implementation is often preferred.We will chaos a single bit implementation
for the current design.
38.8.3.1 Synthesizing the lters
Filter A (s) has transfer function:
N A0
A (s) =
τ O · sO
Filter B (s) has transfer function:
1 1 + a1 · τ · s + a2 · τ 2 · s2 + a3 · τ 3 · s3 + · · · + aO−1 · τ O−1 · sO−1

B (s) = ·
k·D τ O · sO
These two transfer functions can be implemented with the following ar-
rangement:
38.8.3.2 Choosing the modulator order and the sampling

frequency
As already stated, modulator order must be larger than two for chaos to take
place and spread the quantization noise. A simple approach is to create a table
in a spreadsheet program. The analysis has three parameters:
The modulator order.
The sampling frequency.
The transfer functions time constant.
There are few possible values for the modulator order so one two dimensions
table can be created for each order. Then, the input equivalent noise can be
computed for each case and compared to the target spec. This denes the
possible region of operation.
From this analysis, we can choose a third order modulator with a sampling
frequency around 150 MHz.
38.9 Small signal analysis

The following analysis is based on a small signal modeling but produces results
of more general interest. From the analysis, the Sigma-Delta modulator can
be sized completely from the specication to meet. Actual modulator imple-
mentation requires some additional non linear analysis.
38.9.1 Schematic
In the above schematic:
k is the Quantizer eective gain.
Since digital output has no unit and Quantizer input are volts, k unit is volts−1 .
S1 is the rst integrator equivalent output harmonics source.
S2 is the second integrator equivalent output harmonics source.
S3 is the third integrator equivalent output harmonics source.
Harmonic sources units are volts.

A1 is the rst integrator feedback coecient.
A2 is the second integrator feedback coecient.
A3 is the third integrator feedback coecient.
Since digital output has no unit and dierence amplier manage voltages, A1,
A2 and A3 units are volts.
Q is the Quantizer noise spectral density source.
1
This noise unit is volts.hertz − 2
T1 is the rst integrator time constant.
T2 is the second integrator time constant.
T3 is the second integrator time constant.
Time constants units are seconds.

V1 is the rst integrator output voltage.
V2 is the second integrator output voltage.
V3 is the third integrator output voltage.
Of course, these voltages units are volts.

OUT is the Quantizer output.
As already stated, this digital output has no unit.
38.9.2 Equations
Equations for the circuit are:
IN − A1 · OU T
V1 = + S1
T1 · s
V 1 − A2 · OU T
V2= + S2
T2 · s
V 2 − A3 · OU T
V3= + S3
T3 · s
OU T = k · (V 3 + Q)
38.9.3 Calculations
From the equations above, Out can be calculated and contribution of every
term can be extracted.
The free software Eigenmath has been used to carry out the calculations.
The used script follows. Lines starting with # are comments.
38.9.4 Results
Results directly come from Eigenmath outputs.
Closed loop gain is the input to output transfer function:
k
GCL =
A1 · k + A2 · T 1 · k · s + A3 · T 1 · T 2 · k · s2 + T 1 · T 2 · T 3 · s3
That can be reshaped as:
1 1
GCL = · A2·T 1 A3·T 1·T 2 T 1·T 2·T 3
A1 1 + A1 ·s+ A1 · s2 + A1·k · s3
GCL is a third order low pass with time constant τ0 and DC gain GDC :
13
T1 · T2 · T3
τ0 = (38.5)
A1 · k
1
GDC =
A1
Cuto frequency must be higher than max signal frequency so that signal
frequency is always in a range where closed loop gain is constant. Then, closed
loop gain for signal reduces to DC value:
1
GCLSIGN AL = GDC = (38.6)
A1
38.9.4.2 Frequency response type
GCL denominator can be written as:
1 + B1 · τ 0 · s + B2 · τ 02 · s2 + B3 · τ 03 · s3
The values of coecients B1, B2 and B3 dene the frequency response

type.
Usually, the closed loop transfer function is sized to give a Butterworth
(maximally at) type response.
A third order Butterworth lter has coecients:
B1 = 2
B2 = 2
1 # CLEAR WORKSPACE
2 clear
= * *
3 # FIRST INTEGRATOR OUTPUT VOLTAGE
4 V1=(IN A1 OUT) / ( T1 s )+S1
= * *
5 # SECOND INTEGRATOR OUTPUT VOLTAGE
6 V2=(V1 A2 OUT) / ( T2 s )+S2
= * *
7 # THIRD INTEGRATOR OUTPUT VOLTAGE
* =*
8 V3=(V2 A3 OUT) / ( T3 s )+S3
9 # OUT=k ( V3+Q) SO OUT k ( V3+Q)=0
=*
10 # V3 DEPENDS ON OUT
=*
11 # THEN OUT I S SOLUTION OF OUT k ( V3+Q)=0
12 OUT=r o o t s (OUT k ( V3+Q) ,OUT)
13 # OUT CONTAINS CONTRIBUTIONS FROM Q, In , S1 . . .
14 # NOISE TRANSFER FUNCTION I S CONTRIBUTION FROM Q
15 NTF= c o e f f (OUT, Q, 1 )
16 # CLOSED LOOP GAIN I S CONTRIBUTION FROM IN
17 GCL= c o e f f (OUT, IN , 1 )
18 # CONTRIBUTION FROM S1
19 KS1= c o e f f (OUT, S1 , 1 )
21 KS2= c o e f f (OUT, S2 , 1 )
23 KS3= c o e f f (OUT, S3 , 1 )
24 # OPEN LOOP GAIN CALCULATION
25 # WITH I n , S1 , S2 and S3 = 0
= * *
26 # FIRST INTEGRATOR OUTPUT VOLTAGE
27 U1=( A1 OUT1) / ( T1 p )
= * *
28 # SECOND INTEGRATOR OUTPUT VOLTAGE
29 U2=(U1 A2 OUT1) / ( T2 p )
= * *
30 # THIRD INTEGRATOR OUTPUT VOLTAGE
* =*
31 U3=(U2 A3 OUT1) / ( T3 p )
32 # OUT1=k ( U3+Q) SO OUT1 k ( U3+Q)=0
=*
33 #U3 DEPENDS ON OUT1
=*
34 # THEN OUT1 I S SOLUTION OF OUT1 k ( U3+Q)=0
35 OUT1=r o o t s (OUT1 k ( U3+Q) ,OUT1)
36 # OPEN LOOP GAIN I S THE RATIO OF
37 # VOLTAGE AFTER Q SOURCE TO VOLTAGE BEFORE Q SOURCE
38 GOL=s i m p l i f y ( s i m p l i f y ( e v a l ( U3 ) ) / ( s i m p l i f y ( e v a l ( U3))+Q) )
39 # RESHAPING
40 NGOL=n u m e r a t o r (GOL)
41 DGOL=d e n o m i n a t o r (GOL)
42 GOL=s i m p l i f y ( c o n d e n s e (NGOL) / s i m p l i f y ( c o n d e n s e (DGOL) ) )
B3 = 1
Here, we have:
13
T1 · T2 · T3 A2 · T 1
B1 · =
A1 · k A1
And:
23
T1 · T2 · T3 A3 · T 1 · T 2
B2 · =
A1 · k A1
So:
2 1
A2 · T 1 3 · k 3
B1· = 2 1 1
A1 3 · T 2 3 · T 3 3
1 1 2
A3 · T 1 3 · T 2 3 · k 3
B2· = 1 2
A1 3 · T 3 3
Writing condition B1 = B2 brings:
A2
T2 = · τ0 (38.7)
A3
Writing condition B1 = 2 brings:
A2
T2 = · τ0 (38.8)
A3
Writing condition B2 = 2 brings:
A3 · k
T3 = · τ0 (38.9)
2
38.9.4.3 6 4.2 Noise transfer function
The noise transfer function is the quantization noise source Q to output transfer
function:
k · T 1 · T 2 · T 3 · s3
NTF =
A1 · k + A2 · T 1 · k · s + A3 · T 1 · T 2 · k · s2 + T 1 · T 2 · T 3 · s3
T 1·T 2·T 3
A1·k · s3
NTF = k · A2·T 1 A3·T 1·T 2 T 1·T 2·T 3
1+ A1 ·s+ A1 · s2 + A1·k · s3
Combining with 38.5 brings:
τ 03 · s3
NTF = k ·
1 + τ 0 · s + τ 02 · s2 + τ 03 · s3
NTF is a third order high pass with the same time constant and the same
frequency response type as GCL.
NTF high frequency gain G is:
N T F∞ = lim N T F = k
s→∞
38.9.4.4 Input equivalent noise
Quantization output noise spectral density is:
eQN out = N T F · Q
Gain from input to output is GCL, so input equivalent quantization noise

spectral density is:
eQN out NTF

eQN in = = · Q = T 1 · T 2 · T 3 · s3 · Q = τ 3 · s3 · Q (38.10)
GCL GCL
The input equivalent quantization noise spectral density increases as the
power 3 of frequency.
Together with 38.5 this brings:
τ 3 = τ 03 · A1 · k
τ1 is the time constant dening the frequency for which input equivalent
quantization noise spectral density is equal to the Quantizer quantization noise
spectral density:
1
fN1 = (38.11)
2·π·τ
38.9.4.5 Avoiding bit to bit interaction
The direct implementation used for the small signal analysis works properly
as long as all elements are ideal and especially, feedback ampliers A1 to A3
outputs change instantly.
In the implementation with actual components, feedback ampliers nite
turn on and o time results in an interaction between successive output bits.
In order to avoid this issue, a common practice is to switch on the feedback
ampliers only during half the clock period.
Keeping modulator coecient values requires doubling the gain values.
Since Ai values in the design are intended to be controlled with and output
stream of values +0.5 and -0.5, Ai values can be kept to the original values if
they are controlled with values +1 and -1 half the time.
This feedback system is called RZ (return to zero).
38.9.4.6 Loop Stability
The modulator loop has to meet the classic stability criteria in order to operate
safely. This means that open loop gain must have sucient gain margin and
phase margin.
Open loop gain

k · A1 + A2 · T 1 · s + A3 · T 1 · T 2 · s2
GOL = · exp (−T · s)
T 1 · T 2 · T 3 · s3
Open loop gain shows an asymptotic third order negative slope at low fre-
quencies and an asymptotic rst order negative slope at high frequencies. In
addition the loop delay T causes phase lag at high frequencies. Loop delay is
mainly clock related delay. The feedback is not a continuous time signal but
a pulse stream. The clock related delay is the delay between the Quantizer
input change and the middle of the feedback pulse. In addition, excess delay
exists, resulting from the intrinsic delays in the Quantizer and the feedback
coecients.
Magnitude Solving for |GOL|=1, considering the relationship between

time constants (38.7,38.8 and 38.9) leads to:
−τ 06 · ω16 + 4 · τ 04 · ω14 + 1 = 0
Where ω1 is the unity gain angular frequency.

This equation shows that unity gain frequency only depends on time con-
stant τ 0. Solving for ω1 gives:
r
1 4 1 16
ωG1 = · + δ3 + 1
τ0 3 9 · δ3
With:
r
155 283
δ= − = 1.25161
54 108
So:
2.0151
ωG1 =
τ0
Phase Considering the relationship between time constants and coe-

cients leads to:

1
arg (GOL) = π − T · ω + arctan τ 0 · ω −
2 · τ0 · ω
Then, phase margin is:

1
ϕM = T · ω1 + arctan τ 0 · ω1 −
2 · τ 0 · ω1
Phase margin in radians:
2.0151 · T
ϕM = 1.0558 −
τ0
Phase margin in degrees:
115.457 · T
ϕM = 60.4928 −
τ0
For a return to zero feedback system, calling t the additional loop delay:
3
T =t+
4 · Fs
Solving for the phase margin to be greater than a given ϕ0 value leads to:
3
Fs > 60.4928−ϕ0

4· 115.457 · τ0 − t
This equation sets a second condition on modulator time constant and

sampling frequency.
Absolute minimum limit for Fs with 0 phase margin and 0 additional loop
delay is:
1.4315
Fs >
τ0
With a third order modulator, an option is to modify the coecients so that
the closed loop response is Butterworth taking into account the additional loop
delay. This option is not analyzed here.
38.9.5 Sizing the modulator from its specication

38.9.5.1 Sizing the modulator time constant τ0
38.10shows that input equivalent noise is proportional to frequency to the power
3. Since input equivalent noise must not exceed spec Eninmax, worst case
occurs at max useful input frequency:
3
τ 3 · (2 · π · fM AX ) · Q < eQN inM AX
Then:
eQN inM AX
τ3 < 3
(2 · π · fM AX ) · Q
Together with 38.5, this brings:
eQN inM AX
τ 03 < 3 (38.12)
A1 · k · (2 · π · fM AX ) · Q
This expression shows that sizing τ 0 requires knowing parameters Q, k and

A1.
Combining 38.4 and 38.12 results in:
√
eQN inM AX · 6 · FS
τ 03 < 3
A1 · (2 · π · fM AX )
So:
√ 13
1 eQN inM AX · 6 · FS
τ0 < · (38.13)
(2 · π · fM AX ) A1
These equations show that τ 0 depend on spec parameters and design vari-
able A1. Going further in sizing τ 0 requires sizing A1.
38.9.5.2 Sizing A1
A1 is sized on modulator saturation considerations.

In order for the single bit modulator not to operate in saturation, Quantizer
output has to show activity. This means that Quantizer input must cross
the threshold permanently. In turn, this implies that noise exceeds signal at
Quantizer input:
V inP K
VP N 3 >
A1 · k
In this case, as already stated, the Quantizer output duty cycle depends
on the signal value. The larger the noise, the larger the signal range for the
output duty cycle to go from 0 to 1. Then signal gain is dened by noise:
1
k=
2 · VP N 3
Solving for A1 leads to:
A1 > 2 · V inP K (38.14)
In fact, if this condition is just met, the comparator input just crosses
zero on the noise peaks when the input signal is near its maximum value.
This condition is sucient if the noise amplitude distribution is uniform. If
noise amplitude distribution is such that probability decreases when amplitude
increases, comparator activity slows down around input signal peaks. This
phenomenon causes an increase in the peak factor. In turn, the peaks become
less frequent and so on. This leads to the modulator saturation. In order to
avoid this, A1 has to be over sized by a factor KM . This factor must depend
on the noise amplitude distribution.
Choosing KM > 1 directly gives A1:
A1 = 2 · KM · V inP K (38.15)
38.9.5.3 Going further with the modulator time constant τ0

Combining 38.13 and 38.15 brings:
1 1 1
3 6 · eQN
3
inM AX · FS
6
τ0 = 1 1 (38.16)
2 6 · KM 3 · V inP K · 2 · π · fM AX
So, nally, τ0 can be sized from specication parameters and a single as-
sumption on KM.
Combining 38.6 and 38.15 brings:
1
GCLSIGN AL = (38.17)
2 · KM · V inP K
38.9.5.5 Sizing A2
A2 is sized on rst integrator output saturation considerations. None of the

three integrators output swing must reach saturation level for the modulator
to operate properly. On each integrator output, the signal results from the
input signal and the shaped quantization noise. Since these two sources are
uncorrelated, the peak value can be as high as the sum of the signal peak value
and the noise peak values.
The signal peak value at each integrator output can be calculated from the
input signal peak value and the gains from input to each integrator output.
The noise peak value at each integrator output can be calculated from the
noise RMS value and a crest factor. The RMS noise at each integrator output
results from the noise integration across frequency. The Q noise source is white
thanks to the modulator chaotic oscillation.
First integrator output signal Since signal frequency is much below cuto,
transfer function reduces to DC value and then, input contribution reduces to:
A2
V 1in = · V in (38.18)
A1
First integrator output noise Contribution from noise at rst integrator

output is:
T 2 · T 3 · s2
V 1Q = A2 A3 1
·Q
1+ A1 · T1 · s + A1 · T 1 · T 2 · s2 + A1·k · T 1 · T 2 · T 3 · s3
The transfer function shows two time constants, τ0 and τ 1.

τ0 comes from 38.5
τ1 is dened by: τ1 =
√
T2 · T3
Together with 38.8 and 38.9 this brings:
r
k · A2
τ1 = τ0 ·
2
τ0 denes frequency cuto frequency f0 and τ1 denes cuto frequency f1:
1
f0 =
2 · π · τ0
1
f1 =
2 · π · τ1
Gain from numerator is:
2
f
GN 1 (f ) =
f1
Gain from denominator has two asymptotic branches:
below f0: GD11 (f ) = 1


3
f0
above f0: GD12 (f ) = f
Then, the transfer function from Q to the rst integrator output has two asymp-
totic branches:
below f0: (+40 dB / decade slope )
above f0: (-20 dB / decade slope )
Maximum gain occurs at f0 and value is:
2
f0 k · A2
G1QM AX (f = f 0) = =
f1 2
As a consequence, noise spectral density at rst integrator output peaks at

f0 and value is:
Noise power at rst integrator output is the integral across frequency of the
squared noise voltage.
Integration can be simplied by observing that power can be divided in two
terms, one term, P1, for frequencies below f0 and one term, P2, for frequencies
above f0.
Below f0, noise density is:
So:
is such that for:
So:
And then:
Above f0, noise density is:
So:
is such that for:
So:
And then:
Noise peak voltage at rst integrator output is:
Equation 23
First integrator output peak voltage Finally, summing Equation 22 and

Equation 23, total peak voltage at rst integrator output is:
This peak voltage must be smaller than integrator 1 saturation voltageV1max
Equation 24
Then, solving for A2 brings:
Equation 25
Replacing f0 and A1 with their expressions brings:
Equation 26
A2 can be sized from specication parameters, assumptions on KM and
PF1, and one implementation constraint on V1max.
38.9.5.6 Sizing A3
A3 is sized on second integrator saturation considerations.

Second integrator output signal Again, since signal frequency is much

below cuto, transfer function reduces to DC value and then, input contribution
reduces to:
Equation 27
Second integrator output noise Noise contribution is:

The transfer function shows three time constants 0, 2 and 3:
0 comes from Equation 1, 2 is dened by:
And 3 is dened by:
The time constants dene frequencies with respective indexes. Combining
with Equation 4 and Equation 6 brings:
And:

Gain from numerator has two asymptotic branches:
Below f2: Above f2:

Gain from denominator is the same as for rst integrator:
below f0: above f0:
Since:

The transfer function has three asymptotic branches:
Below : (+20 dB / decade) From to : (+40 dB / decade) Above :
(-20 dB / decade)
Gain value at is Gain value at is
Noise power can be divided in three terms, one for each asymptotic branch:
Below , noise is:
is such that for:
So:
From to , noise is:
Since:
Then:
is such that for:
So:
Above , noise is:
is such that for:
So:
Units for P2 are V2 which is correct.
Finally, noise peak voltage at second integrator output is:
Equation 28
Second integrator output peak voltage Summing Equation 27 and Equa-

tion 28, total peak voltage at second integrator output is:
Equation 29
Again, this peak voltage must be lower than the rst integrator output
saturation voltage V2max:
Equation 30
Solving for A3 brings:
Equation 31
Replacing f0 and A1 with their expressions brings:
Equation 32
A3 can be sized only from specication parameters, assumptions on KM
and PF2, and one implementation constraint V2max.
38.9.5.7 Sizing T1
T1 can be sized using Equation 5.

Replacing 0, A1 and A2 with their expressions brings:
Equation 33
38.9.5.8 Sizing T2
T2 can be sized using Equation 4.
38.9.5.9 Sizing T3
T3 appears in Equation 6.
But unfortunately, k is required to compute T3.
k is dened by Equation 11.
The lower the noise q is, the higher the gain k.
And since the noise q appears at the third integrator output, the larger the
time constant T3 is, the smaller the noise.
So, nally, the larger the time constant T3 is, the larger k, but actual T3
value is not a concern, it is a degree of freedom in the design.
38.9.5.10 Sizing summary
Finally, all the design parameters can be calculated from specication param-
eters, the KM factor, assumptions on PF1 and PF2, and implementation con-
straints on V1max and V2max.
Since PF1 and PF3 are noise peak factors, a value of 3 is a reasonable
assumption.
V1max and V2max are usually lower than supply voltage by some hundreds
of mV at each end. Values can be assumed easily.
Then, only KM is unknown, but all the design parameters can be expressed
versus KM. If KM is large enough, no modulator saturation occurs, if KM is
too low, modulator saturation occurs.

The sizing sequence can be:

Choose KM > 1 Size the design Simulate it with maximum input
voltage Trim KM until modulator is stable
It can be interesting that the closed loop gain is a power of 2 so that the
digital output can reect the input voltage by a simple logical shift.
38.9.6 SIZING EXAMPLE

Given the following specication:
Fs = 120 MHz Fmax = 480 kHz Enin = 30 nV / Hz1/2 Vinpk = 1.3
And the following assumptions:
V1max = 1 V V2max = 1 V PF1=3 PF2=3
An interesting choice is:
This gives:
This gain can be easily compensated by shifting the ADC output by two
bits towards the MSB.
With this choice:
Equation 18 gives A1 = 4
Equation 20
Equation 25 gives A2 = 1.99554
Equation 31 gives A3 = 1.4527
Equation 5 gives T1 = 7.77878e-8
Equation 4 gives T2 = 2.66542e-8
Equation 6 gives T3 = 1.40938e-8 * k
38.9.6.1 Validation
Validation of this sizing is done using scilab, free software (Scilab Home Page)
ADC3 schematic is:
With Integrator1:
Integrator2:
And Integrator3:
Values are just as computed above. Third integrator time constant shows
that comparator signal gain has been arbitrarily set to 2.
Results Results include peak factors, closed loop gain, integrators outputs,
comparator gain and input noise.
Peak factors With the computed values, simulated peak factors

are 3.2 instead of 3. 6.1.1.2 Low pass ltered input and output signals
Graph shows input (green) and output (black) signals. Each signal is ltered
by two second order Butterworth 1 MHz low pass lters. Gain is exactly 0.25
as expected.
First integrator output First integrator output for 1.3 Vpk input signal
shows that peak does not exceed 1 V, which is the value for V1max.
Second integrator output Second integrator output for 1.3 Vpk input
signal shows that peak does not exceed 1 V, which is the value for V2max.
Third integrator output Third integrator output for 1.3 Vpk input
signal shows that noise peak exceeds signal peak, which was a design target.
Plot also shows that saturation is just beginning since noise stretches around
signal peaks.
Comparator eective gain Comparator gain can be checked using X-Y

plot of low pass ltered output versus low pass ltered input. Graph shows a
gain of about 2, as expected.
Input equivalent noise Displaying input noise density requires some

processing that was done in scilab. This processing includes computing input
noise from output noise, normalizing noise with a Hanning windowing and
averaging over some (11 here) values.
Result shows that input noise density at 480 kHz is 30.4 nV.Hz-1/2. This
value is very close to the design target (30 nV.Hz-1/2).
Noise oor at low frequencies probably results from rounding eects but is
not a concern since it is much below specication.
Slope between 100 kHz and 10 MHz is that of a third order high pass lter
as expected
A very small amount of third harmonic denotes the very beginning of mod-
ulators saturation.
Results Summary Parameter Calculation/Constraint Simulation Unit Closed

loop gain 0.25 0.25 _ 1st integrator output peak voltage <1 0.98 V 2nd in-
tegrator output peak voltage <1 0.92 V Input equivalent noise at 480 kHz 30
30.4 nV/Hz1/2
All these results show very good agreement with calculations. This validates
the calculations.
38.9.7 IMPLEMENTING THE ADC

Turning the behavioral ADC into an actual one requires considering implemen-
tation architecture and non ideal behaviors.
38.9.7.1 Architecture
The preferred implementation in integrated circuits is based on a dierential

implementation.
7.1.1 Integrators Integrators in integrated circuits are implemented using

OTAs and capacitors. Implementation can be open loop type or feedback type.
Actual integrators are non ideal and exhibit non linearity, and noise.
38.9.7.2 Non linearity
Integrators non linearity results in output harmonics and inter-modulation be-

tween signal and noise.
Additional specication item is output harmonic contents:
H3OUT = -45 dB
Dierential implementation basically generates only odd harmonics. Only
harmonic 3 will be considered at this point.
7.2.1 Output harmonic contents Fundamental output term is given by

Equation 2
Third harmonic output term results from the third harmonic contributions
of the three integrators.
These harmonic terms sum up with their respective phases.
7.2.1.1 Third harmonic from rst integrator Any signal added to

the rst integrator output reaches the ADC output with a gain:
KS1 is the product of a third order low pass with time constant from Equa-
tion 1 by a rst order derivator with time constant .
Such a transfer function achieves a +20 dB / decade slope from DC to the
frequency f0 and a 40 dB / decade above f0, with:
Calling input signal frequency n, since 3.n is lower than f0, gain value at
is:
And phase is +90 . °

With the sizing from above:
7.2.1.2 S2 to Output transfer That can be reshaped as:

KS2 is the product of a third order low pass lter with time constant 0 by
a second order derivator with time constant 4.
frequency f0 and 20 dB / decade above f0.
Peak gain occurs at and gain value at is:
Again, input signal frequency third harmonic is lower than f0, so gain value
°
at is:
And phase is + 180 .
7.2.1.3 S3 to Output transfer A third order high pass with time con-
stant 0:
And gain k.
frequency f0:
°
Gain value at is:
And phase is +270 .
7.2.1.4 Total Output third harmonic contents If the three integra-

tors have the same non linearity, since the swings at their inputs are about the
same, the amount of harmonics at their outputs is about the same.
Gains for harmonics from integrators outputs to output are such that:
So, the major contributor to the output harmonics is the rst integrator.
This one must then be much more linear than the other ones.
7.2.1.4.1 Verication With the sizing from above, adding a third order non-
linearity on the integrators in the scilab platform show the following results.
7.2.1.4.1.1 Harmonics from rst integrator. For an output third

harmonic specication of -45 dB, third order term for rst integrator must not
exceed 1.3e-2 V/V3 relative to 1 V/V rst order term. In order to provide
margin and to keep provision for other integrators non-linearity, value should
be kept below 7E-3.
7.2.1.4.1.2 Harmonics from second integrator. For an output third

harmonic specication of -45 dB, third order term for second integrator must
not exceed 0.18 V/V3 relative to 1 V/V rst order term. In order to provide
margin and to keep provision for other integrators non-linearity, value should
be kept below 0.1. The curve is not plotted above 0.2 because the modulator
stops working when the non linearity is such that the transfer curve is no longer
monotonic. This would not occur with an actual integrator that saturates but
stays monotonic. Here, a simple third order model is used and it exhibits non
monotonic behavior. This result also shows that second integrator non-linearity
can be much higher than for rst integrator.
7.2.1.4.1.3 Harmonics from third integrator. This result also shows

that third integrator non-linearity can be much higher than for rst and sec-
ond integrator. In fact, the modulator stops working because of non monotonic
transfer characteristics before output harmonic contents exceeds the specica-
tion. Anyway, if the second and third integrator use the same OTA, if it is
sized to be good enough for the second integrator it is good enough for the
third integrator.
So far, only the time constant is dened. Now actual capacitor and trans-
conductance values have to be dened.
At this point, the integrator topology has to be chosen. It can be either
open loop or closed loop.
7.2.2 Open loop type integrator For the open loop type, the integrator
non-linearity is directly that of the OTA.
Time constant is:
In this expression, C is the capacitor value and G is the OTA trans-
conductance.
In this case there are many options for choosing C and G. It is a good
practice to use a small capacitor value since this leads to a small silicon area
and it also minimizes the current. The lower limit for the capacitor value is
that is must be large with respect to the parasitic capacitors. The pF range is
suitable for that reason.
For integrator 1, table gives suitable C and G values and associated output
current for the max input voltage (Vin =1.3 Vp). It also gives the target G3
value to meet the harmonic specication.
C G1 Iout G3 1.00E-13 1.29E-06 6.81E-06 9.00E-09 2.00E-13 2.57E-06
1.36E-05 1.80E-08 5.00E-13 6.43E-06 3.41E-05 4.50E-08 1.00E-12 1.29E-05
6.81E-05 9.00E-08 2.00E-12 2.57E-05 1.36E-04 1.80E-07 5.00E-12 6.43E-05
3.41E-04 4.50E-07 1.00E-11 1.29E-04 6.81E-04 9.00E-07 2.00E-11 2.57E-04
1.36E-03 1.80E-06
The question at this point is to know whether it is possible or not to syn-
thesize an OTA with these requirements.
Calculation shows that even for a degenerated dierential pair, reaching
these linearity gures is out of reach at these high currents. Calculation details
are not reported here but exist in another document.
The only solution for the rst integrator is to use a feedback type.
7.2.3 Feedback type integrator For a closed loop type integrator, provided
the fact the OTA trans-conductance is large enough, the time constant is:
In this expression, C is the capacitor value and R is the resistor value.
In this case there are many options for choosing C and R. It is a good
practice to use a small capacitor value since this leads to a small silicon area
and it also minimizes the current. But a small C value leads to a large R value
and noise is the concern for sizing.
If the amplier's open loop transfer characteristics is:
And if the amplier is included in a loop with a front-end gain k and a
feedback gain B, closed loop output voltage Taylor expansion gives:
For an inverting amplier, calling Z1 the impedance to the input and Z2
the feedback impedance:
The familiar result

For an operational amplier R.C inverting integrator:
If the amplier is an OTA with transfer characteristics:
Then previous result applies with:
And:
Then:
Equation 34
And:
Equation 35
7.2.4 Sizing the rst integrator OTA Sizing the OTA is mainly dening
the rst and third order trans-conductance coecients.
7.2.4.1 First order trans-conductance
7.2.4.2 Third order trans-conductance Third order trans-conductance

gm3 can be sized from Equation 35 with a design target on K3.
As the signal frequency is below the integrator unity gain frequency, de-
nominator is close to 1.
Worst case for gm3 is minimum frequency
7.2.5 Second integrator
Again, with the second integrator, given the time constant, choosing the
capacitor value results in a trans-conductance value and an output current
value. Given also the linearity constraint, the trans-conductor can be specied.
The lower linearity requirement and the lower required currents at this point
make an open loop implementation possible.
TO BE COMPLETED
7.2.6 Other non-linearity eects
In addition to producing output harmonics, trans-conductors non-linearity
generates inter-modulation with noise. This eect increases the apparent noise.
Inter-modulation has to be evaluated in order to be kept within acceptable
limits.
At maximum input level, inter-modulation does take place and leads to a
linearity constraint which is more stringent than the one resulting from the
harmonic specication.
But at max input level the input noise specication is not relevant. If a
disturber at max level exists, useful signal cannot be less than 45 dB below.
Again in this case, the input noise spec is not relevant, the input noise just
needs to be low enough to provide the requested signal to noise ratio.
The worst case for inter-modulation occurs when useful signal is at mini-
mum level and a disturber at maximum possible level exists. In this case, the
input noise spec applies and this sets the limit for inter-modulation.
Values from spec are -67 dBm for signal and -22 dBm for disturber for an
input noise spec of 30 nV.Hz1/2.
The question is to know which from inter-modulation and harmonics denes
the linearity requirements for the OTA.
TO BE COMPLETED
7.3 Sizing the dierential implementation
The dierential implementation is based on a feedback type rst integrator

and open loop type second and third integrators.
7.3.1 Feedback type integrator 1
If G1 is very large:
Integrator as dened for calculations above:
Output writes:
Identifying expressions gives:
And:
Equation 36
Sizing gave:
A1 = 4 T1 = 7.77878E-8
The implementation has one degree of freedom since three component values
are required to set values for two design parameters
R1 is the degree of freedom. For a given R1 value, C1 and D1 values can
be chosen to achieve the target A1 and T1.
R1 value is constrained by electrical noise consideration.

Input electrical noise power is mainly the sum of two terms:
The two R1 resistors noise power The two D1 current sources noise
power
Equation 37
Noise power from the two R1 resistors is:
Equation 38
If the current sources are made from simple MOS transistors, considering
that in a return to zero feedback system the sources are on half the time, noise
from the sources is:

Equation 39 In this expression:
is the current sources duty cycle ( = 0.5). gm1 is the current source
trans-conductance.
In each current source MOS:
Equation 40
Since FB swings 0.5, current in behavioral the current sources is:
Practically, current sources are implemented with transistors and can either
source or sink current depending on the transistor polarity, but current can ow
only in one direction. Achieving a bidirectional current source requires using
two currents sources switched alternatively on or o.
FB is then a [0,1] signal and four current sources controlled by FB and
complemented FB implement the same functionality and characteristics that
the behavioral sources.
In this case, each of the four sources value is Isource.
And since the return to zero feedback system requires more current value
during part of the time, each of the four current sources value is:
Equation 41
From Equation 18 and Equation 36, a relationship exists between R1 and
D1:
Equation 42
Given the current sources saturation voltage VDSAT:
Combining with Equation 41 and Equation 42 brings:
Equation 43
Combining Equation 39 and Equation 43 brings:
Equation 44
Noise from the current sources does not depend on the duty cycle since it
aects both the current value and its contribution.
Then, putting together Equation 37, Equation 38 and Equation 44, the
input electrical noise power is:
Equation 45
Equation 45 can be reversed to express R1:
Equation 46
If input electrical noise power must not exceed PNINMAX, R1 must not
exceed R1MAX:
Equation 47
With the values from sizing above and assuming VDSAT = 0.7 V and
PNINMAX = 2.5 E-15 (50 nV.Hz1/2):
R1MAX = 25.97 k
In addition, Equation 40 denes the current sources MOS size:
In order to use integer numbers:
R1 = 25 k
Then D1 = 80 A and C1 = 3.11 pF
7.3.2 Open loop type integrator
Identifying expressions gives:
And:
Sizing gave:
A2 = 2 T2 = 26.65 ns A3 = 1.5 T3 = k * 14.1 ns
Again, circuit has three component values to achieve two design parameters.
Degree of freedom is G.
Actual sizing is based on C values that must be large enough so that para-
sitic and routing have limited impact.
In addition, minimizing the design eort suggests to use the same trans-
conductor for the two integrators.
Finally, choosing Cs in the 1 to 2 pF range brings, after rounding:
G2 = G3 = 30 S D2 = 60 A D3 = 45 A C2 = 1.6 pF C3 = 845.6 fF * k =
1.7 pF for k=2
With this dierential implementation sizing, running a simulation in Ca-
dence using voltage controlled current sources gives the following results:
7.3.2.1 First integrator dierential output
Plot shows that swing is very close to scilab simulation result and to target
(1 V peak).
7.3.2.2 Second integrator dierential output
Plot shows that swing is very close to scilab simulation result.
7.3.2.3 Third integrator dierential output
Plots shows the same beginning of saturation as scilab. 7.3.2.4 Comparator
transfer characteristics
Comparator shows signal gain around 2, close to expectations from C3
sizing. Picture is a bit dierent from scilab results, the signal is cleaner. The
dierence results from dierent x and y lters sizing (lower cuto frequency
here).
7.3.2.5 Input equivalent noise
Graph shows result is very close to scilab output. Value at 480 kHz is very
close to 30 nV/Hz1/2 which was the design target.
The small amount of third harmonics in the output spectrum denotes the
beginning of saturation.
7.4 Implementing the dierential modulator

Next steps include implementing the behavioral blocks with transistors.
This was done step by step but the results are not yet written in the report.
During the implementation, the major concern was the increase in the noise
oor.
Some of the elements to care about in order to avoid this noise increase:
7.4.1 Matching of P and N current sources
Any mismatch between the P and N current sources results in an increase
of the low frequency noise oor. The smaller the rst integrator OTA trans-
conductance, the higher the noise oor. Active matching of P and N sources
current using an additional branch is required to keep the noise to an acceptable
level. Accordingly, rst integrator OTA trans-conductance has to be as high
as 2 mS. 7.4.2 Charge injection by the current switches
The switches have to be as small as possible and transfer gates must be
used to keep the noise oor to an acceptable level. 7.4.3 Non true dierential
comparator
Any dierential delay on the current switches results in an increase in the
noise oor.
Part IV
Techniques
229
This part presents a number of techniques aimed at

addressing various issues that occur frequently in IC design.
Chapter 39
Analyzing operating point DC

stability
An analog cell functionality and performance depends on its operating point46.2.

This results from the fact that components characteristics depend on their pro-
cess parameters, on their sizing, but also on the operating point.
It is then important that a cell operating point is exactly what is required
to meet the target specication. This looks clear and it is what the circuit
designer targets but some phenomenons can cause trouble:
Some cells exhibit more than one operating point.
Some operating points are DC stable, some are not.
The DC stable operating points can be AC stable or not.
Provided the fact the operating point is actually what is required, at least four
conditions are required for the cell to work ne:
The operating point must be unique
It must be DC stable
It must be AC stable
It must be robust.
Checking these four points is not so straightforward and requires a method

that is described in this chapter.
39.1 Example
Let's start with an example:
231
CHAPTER 39. ANALYZING OPERATING POINT DC STABILITY 232
Figure 39.1: Two inverters loop
This schematic shows two inverters connected as a loop and a voltage source
to supply the inverters (Only digital designers don't need to supply their cir-
cuit!). Lets simulate this circuit operating point46.2 and display it on the
schematic:
Figure 39.2: Two inverters loop Operating Point
This result is strange. Inverters input and output voltages are equal to
about 2.397 V for a 5 volts supply. And the two inverters draw a signicant
147.7 micro-amps current from the supply.
If you wire this circuit with two inverters from a good old CD4049 hex
inverter in the lab (don't forget to tie the unused inverters input to ground)
you will never nd this operating point. Instead, you will notice that one
inverter output is 0 V and the other one is 5 V.
Why is the simulator result dierent from the lab result ?

To try answering this question, let's open the loop and sweep the rst
inverter input voltage from 0 V to 5 V.
Figure 39.3: Two inverters Open Loop
The output voltage of rst inverter versus input voltage looks like a standard
CMOS inverter transfer characteristics:
Figure 39.4: One Inverter Transfer Characteristics
And the second inverter output voltage versus rst inverter input voltage
is sharper with, of course an opposite slope:
Figure 39.5: Two Inverters Transfer Characteristics
Now when the loop is closed and left free, the rst inverter input voltage is
equal to the second inverter output voltage. If we plot together the open loop
input and output voltages, we notice that the two curves cross each other in
three dierent points.
Figure 39.6: Two Inverters Loop Operating Points
At each intersection point, output voltage is equal to input voltage, the

condition that has to be satised at the operating points. So, an operating
point exists each time the two curves cross each other.
So, here, there are three possible operating points. The leftmost (0,0) and
rightmost (5,5) ones are those you can nd in the lab. The center one (2.4,2.4)
is the one the simulator nds.
Now, we can explain why the lab and the simulator give dierent results:
The extreme operating points are DC stable while the center one is not.
How can we say that?

The input line has a slope +1, obviously since we plot input voltage versus
input voltage. When the output curve crosses the input line, either the output
slope is higher than +1 and the operating point is DC unstable, or the slope
is lower than +1 and the operating point is DC stable.
So our circuit has two DC stable operating points, the extreme ones, and
one DC unstable, the center one. In the lab, only DC stable operating points
can exist.
But why does the simulator give only the DC unstable operating point?
This is because of symmetry. The two inverters are exactly the same for
the simulator so only a balanced solution can be found. But this is mainly
because simulators try to nd an operating point but they do not care about
DC stability.
Figure 39.7:
So, it is strongly suggested to question the operating point the simulator

provides.
What about AC stability?
As long as the slope is higher than -1, there is no concern with AC stability.
Loop gain magnitude is lower than 1, loop cannot oscillate. If slope is lower
than -1, AC stability has to be checked.
DC unstable operating points are generally not a concern as circuits cannot
stay in this state. But as soon as there are more than one DC stable operating
points, the concern is: Is not there any undesired DC stable operating point?
39.2 Generalizing
What kind of circuits can have multiple stable DC operating points?
This is a dicult question to answer exactly. Experience shows that mainly
loops can exhibit more than one operating point. Theoretically, a simple circuit
with a non monotonic characteristic device and a resistor could exhibit multiple
operating points, but such a device is hard to nd. One example is a thyristor in
series with a resistor, but this is not an usual functional circuit. So, practically,
considering that only loops may have multiple operating points is a reasonable
assumption.
How many operating points are there in a circuit?

Again, this is a dicult question. Let's try an empirical approach:
First, let's assume that only loops have multiple operating points.
The method for detecting operating points is opening the loop and sweep-
ing the input.
The idea is that the loop response is nite even if the input is swept widely.
This can expressed in the fact that output vs. input characteristic has
horizontal branches at each end.
Then, the line with +1 slope, has to cross the transfer curve an odd
number of times.
This is denitely not a demonstration but it gives a good idea.

From experience, the author can state that most circuits have only one
operating point, some have three, and only one in 25 years appeared to have
ve.
39.3 Example: PTAT current source

This is the bipolar version of the constant gm bias cell.35
Here we will not address design, nor sizing, just operating point stability
and uniqueness.
Figure 39.8:
In this case, the loop operates in current mode. We can divide the schematic
in two parts:
The bottom Widlar current mirror
The top regular current mirror
39.3.1 Widlar mirror transfer characteristics

When currents are low, voltage drop in resistor is small compared to VBE.
Currents are then in the same ratio as transistors size. When input current
increases, output current increases in the transistors size ratio which is, by
assumption, larger than 1. Slope around 0 is M.
When currents are large, drop in resistor is large. At this point, we have to
assume that a small resistance exists in the input transistor emitter. Currents
are in the inverse ratio of resistances. When input current increases, output
current increases in the inverse ratio of resistors. By assumption output slope
is smaller than 1.
The exact curve can be drawn by a simulator.
39.3.2 Regular mirror transfer characteristics

Obviously, this transfer is linear with gain 1 at least at rst order.
39.3.3 Operating points

If the two parts are connected together, the input of one part is equal to
the output of the other. If the two characteristics are plotted together, one
operating point exist every time the two curves cross each other. This occurs
around zero and around the target current. Apparently, there are two operating
points. This is in contradiction with our previous statement that there is
always an odd number of operating points. In fact, if input current is swept
in the negative region, output current for both mirrors stays stuck at zero.
The operating point around zero is then a double point. Practically, because
of mismatch and leakage, this double point may exist, it may not or it may
split in two points. If this point does not exist, good news, only the desired
operating point exists and everything is ne. If the double point or two points
exist, one is DC stable, one is not. No concern with the DC unstable one,
but the stable one must be suppressed for the circuit not to stay in this state.
The class of circuits intended to suppress undesired operating points is called
kick-up circuits, because most undesired operating points are around the o
state.
Chapter 40
The dependency graph method
This method is proposed to help the designer during the sizing phase. It
is aimed at dening the sizing sequence by detecting free parameters, linked
parameters and constraints.
There is one dependency graph for each cell characteristics.
Each graph is built starting from the set of equations that express the
cell characteristic as a function of components or sub-blocks parameters.
Characteristics or parameters are gured as a boxes and dependencies

are gured as arrows.
The graph is built step by step until it reaches primary parameters. Primary
parameters are parameters that do not depend on anything. Among primary
parameters are the constants of physics that are useless for sizing, but also
geometry and bias parameters that are free for sizing.
The method for building the graph is:
Writing all the possible equations. The list can be extended later if some
equations are missing.
Manually drawing boxes for parameters and arrows for dependencies on

a large sheet of paper. This step may require several iterations to reach
a nice graph. Graph drawing tools such as dot can be used. Dot
processes an input text le to generate the graph in variety of graphic
le formats. Text description has basically two sections, the boxes and
the links. It is particularly well suited for our purpose. The graph dot
creates sorts the boxes in layers. The rst layer contains the boxes that
do not receive links, the second layer contains boxes that receive links
from the rst layer and so on.
The graph gives a good overview of the sizing sequence, it show loops.
A loop, as the name states is a closed sequence of boxes connected by

links.
Usually, the non linear equations system complexity makes it impossible to

solve it analytically. But at this point, all the parameters have numeric values
238
CHAPTER 40. THE DEPENDENCY GRAPH METHOD 239
and it is possible to solve the system numerically. The point is to nd a multiple
variables, non linear solver...
Fortunately, such a solver is always available in an IC designer's environ-
ment, even though it is usually not used explicitly for that purpose. This tool
is an electrical-behavioral simulator. The simulator can be used in the DC
domain with an analog approach. The quotes indicate that the word analog
is used in its original meaning. In the analog domain, voltages and currents
may gure other physical data such as speed or frequency or length or whatever
parameter.
The free parameters can be swept so as to see how circuit performance
changes. It is then often possible to reach a reasonable sizing after a couple of
experiments. These simulations are extremely fast, so many trials can be made
very quickly.
The curves shape not only can give parameters value to reach the target
performance but it also gives information on the sizing robustness. It is a good
practice to size a circuit so that performance does not change much with the
parameters values. If a performance vs. parameter curve has a sharp region
and a soft region, sizing in the soft region is more robust.
Chapter 41
The gmin stepping method
In CMOS circuits, a common issue is oating gates.

If a CMOS inverter input is driven by a weak node, it may bias so that a
signicant current ows through.
In normal operation this phenomenon usually does not take place, but oc-
currence in power down or standby modes has proved to be a cause for re-
designs.
Normally, true oating gates i.e. gates connected to nothing are detected
by design checkers. But gates driven by weak nodes are not.
A weak node exists in situations like tri-state outputs when disabled. The
voltage on such a node is undened. More precisely, the voltage depends on
the leakage currents of all the devices connected to the node. These leakage
currents are subject to change from part to part, with temperature and through
time.
Standard simulation may not show the issue.
A method that would reveal weak nodes would reduce the redesigns they
may cause.
41.1 Suggested method

The method suggested here uses an internal parameter commonly available in
most simulators. This parameter is often called gmin after SPICE used this
name.
41.1.1 Gmin
Gmin denes the minimum conductance of any semiconductor device non-
isolated branch. This is equivalent to saying that any non-isolated pair of
nodes in a semiconductor device has a 1/gmin resistor in parallel.
Graph shows drain-source resistance with VGS=0 for gmin=1e-6;1e-9;1e-
12.
Clearly, if some current ows in the device, dynamic resistance is lower than
1/gmin but in no case it can be larger than 1/gmin.
If the same is done with a gate source branch, no such phenomenon occurs,
current is zero.
240
CHAPTER 41. THE GMIN STEPPING METHOD 241
If two instances are connected in parallel, dynamic resistance never exceeds

1/(2.gmin). If a multiplier is used, only one branch exists and dynamic resis-
tance never exceeds 1/gmin. In other words, one gmin conductance is added
per device branch whatever the device size is.
But, on the other hand, additional conductance from the device itself de-
pends on device size.
Chapter 42
The noise peaking method
This method provides good condence in a circuit AC stability even in situ-

ations where the source of instability is hidden deep in the circuit, in places
like bias cells or in case of multiple interacting loops. This method is both
fast, ecient and analytical. Not only does it reveal instabilities but also it
identies the source of instability.
242
Chapter 43
Robust design techniques
A robust design is a design that survives process tolerances and provides a

consistent manufacturing yield over time. Techniques exist that can lead to
robust designs.
43.1 General principle

The underlying idea is that it is possible to design a circuit in such a way that
its performance is made insensitive to process parameters in a given distribu-
tion range. More precisely, the idea is that within a given process parameters
distribution range, the circuit performance can stay within specication limits.
If this is possible, then any chip with process parameters within range is
good and the yield is as good as possible. Additionally, it is possible to push
the design closer to the limits of the process parameter distribution and then
to improve the performance.
43.2 Introduction
The functionality and performances of an analog cell mainly depends on bias,
component geometry and process parameters.
The normal process tolerance results in process parameters spreading.

These parameters are dierent from lot to lot, from wafer to wafer and
from device to device. There is no possible action from the designer to
prevent this spreading.
The component geometry can be chosen at design level so as to minimize

undesired eects. But when chosen, apart from manufacturing tolerance,
the component geometry is the same for all the chips and cannot be used
to compensate for parameter variations.
The bias point is a set of electrical variables that is chosen by the designer
in order to meet the circuit performance. Of course, the bias point is
sensitive to process parameters. If no special care is taken, the bias point
spreading is added to the active components spreading and the result is
poor. On the other hand, some compensation or feedback mechanism can
be added in the bias system so that the result is improved. Generally, it
is possible to improve both performance and yield.
243
CHAPTER 43. ROBUST DESIGN TECHNIQUES 244
Figure 43.1:
43.3 Implementation.
There are basically four dierent techniques that can be used to improve the
design robustness. Of course, these techniques are frequently mixed together
to obtain the best possible result. These four techniques are :
Using low sensitivity architectures.
Compensating for tolerances.
Using feedback.
Trimming to compensate process.
43.3.1 Low sensitivity architectures.

It is a very common situation that the designer can choose from several solu-
tions in a given design situation. At properly speaking, no real choice can take
place if only one solution exists.
Some solutions exhibit intrinsically a low sensitivity to some design vari-
ables. Usually, the component count is a little bit higher for these solutions
than for less robust solutions.
Selecting these solutions naturally results in robust solutions.
43.3.1.1 Example of low sensitivity solution.
In a situation where a designer has to use a bipolar current mirror operating

at a given current I, several types of mirrors can be used :
Simple current mirror.
Buered current mirror.
Degenerated current mirror.
43.3.1.2 Simple current mirror
In a simple current mirror, the structural current error is :
2·I
∆I =
β
Where β is the bipolar transistor current gain.
The output resistance is :
V AF
ROU T =
I
where VAF is the bipolar transistor Early voltage.
43.3.1.3 Buered current mirror
In a buered current mirror, the structural current error is :
2·I
∆I =
β2
where β is the bipolar transistor current gain. the output resistance is not
modied.
For a β ranging from 50 to 200, the simple mirror can exhibit 4 % current
error while the buered version will never exceed 0.08 %.
No dierence between these two solutions regarding the output resistance.
43.3.1.4 Conclusion
So, the buered mirror is a better solution, at the expense of an additional

transistor.
43.3.2 Compensation techniques.

The principle of the compensation techniques is based on the fact that the
relative tolerance in an integrated circuit is much tighter than the absolute
tolerance. For example, a resistor value is as inaccurate as +/- 20 %, but in a
given chip, the ratio of two resistor values is usually better than 1%.
If a cell characteristics depends on ratios rather than absolute values, the
design will be more robust.
43.3.3 Feedback techniques.

The general theory of feedback shows that the closed loop gain of a loop ex-
hibiting a direct path gain A and feedback gain B is : If A.B is much larger
than 1, then . A is usually implemented using transistors and the value of A
can suer large tolerances. B is usually a ratio of resistors and can be reason-
ably accurate. Even if A is inaccurate, G can be accurate provided the fact A
is large enough.
43.3.3.1 Example of feedback technique
Back to the current mirror example. The output resistance of a degenerated

current mirror is : where RE is the emitter resistance and VT the thermal
voltage, 26 mV at room temperature. This is an eect of the feedback.
Selecting the product RE.IE properly results in increasing the output resis-
tance, reducing the dependence of the output current to the output voltage.
So the degenerated mirror is a better solution at the expense of two addi-
tional resistors and a higher saturation voltage.
43.3.4 Trimming techniques

These techniques are used when absolute values cannot be avoided. An example
is a lter time constant. The time constant depends on actual R and C values.
For given R and C in a process:
If tolerance on time constant has to be smaller than natural value from

process, Trimming, also called calibration is required.
Trimming requires that any element to be trimmed is build from discrete
values and switches. Since process centering is common to the whole chip,
switch control can be done by a bus.
There are basically two options for trimming:
Final test trimming
Real time trimming
43.3.4.1 Final test trimming
This technique is suitable when target parameter is stable with respect to time
and temperature.
In this case, parameters can be measured during chip nal test and trimming
bus value can be computed. This requires that the chip has some non volatile
memory to store the bus value. As there are usually not many bits to store,
the NVM can be implemented as fuses or zapped zeners if no true NVM is
available. Of course, if E2PROM is available, it can do the job.
43.3.4.2 Real time trimming
In case the parameters is not stable versus time or temperature, or in case no

non volatile memory is available, real time trimming must be considered. In
this case, parameter must be measured in real time or at least often enough,
for instance each time the circuit is turned on.
The problem is that an accurate reference is required to measure the target
parameter.
As an example, if the circuit uses a crystal for clocking and requires to trim
an RC product, an RC oscillator can be built and its frequency can be measured
using the crystal as a reference. Then the RC product can be trimmed in real
time by an on chip state machine.
43.4 Unexpected consequences of the robust by design

approach.
When the various techniques resulting in a robust design are combined together,
the design can be very insensitive to the component parameters.
It can be so insensitive that even if one component in the design is nearly
failing, the cell will operate properly. Such a part will not be rejected during
the production test but could fail quickly in the application if the nearly failing
component actually fails after some hours of operation.
In other words, the techniques used to improve the production yield can
hide some failure mechanisms and result in early failures in the application.
This means that special attention has to be paid to test. Not only has
the operation to be checked, but also margin must be evaluated. It can be
necessary, sometimes to open the loops or to check operation over a range of
bias values etc. . .
If real time trimming is used, all the trimming values have to be checked
during nal test since it is dicult to dene which value will be used during
the product life.
All this impacts the test time and the test hardware inside the circuit and
then impacts the product cost.
So, nally, if only cost is the concern, a balance must be found between
reaching a good yield to reduce cost and keeping silicon and test time costs
low.
If quality and reliability are real concerns, then this the robust design ap-
proach is a must but it comes at some cost.
Chapter 44
Safe design techniques
A safe design is a design that minimizes the risk of design errors. A number of
techniques exist that make design safer
A design can be dened as safe if it is really what the designer had in mind
and if it operates really as expected. As such, it is not related to design quality,
the fact that the design meets its specication, but it is related to the fact that
the designer did not make implementation errors.
The day to day design activity implies a huge number of actions that are
not completely safe individually. The probability of making no error at all is
then extremely low.
Examples of errors:
mistyping when entering a component name or value.
wrong selection when applying a property change.
In case such an error occurs, a balanced structure can turn to an unbalanced

one. For instance, if only one of the two transistors in a dierential pair is
modied, a structural oset can be added.
On the other hand, changing transistor sizes in more than one cell, (an
amplier and its bias) is error prone and boring.
One possible approach when many instances of a P-Cell appear with the
same values, especially in more than one cell is to create a single component
cell.
Such a cell contains only one P-Cell component. Its symbol can be given a
look close to that of the P-Cell so that the schematics using it look like if using
the P-Cell directly.
The benet of this approach is that in case the one value has to be changed,
changing it inside the single component cell applies it in all the instances.
More generally speaking, factoring common things is a safe design technique
even though experience shows that only few designers use it.
248
Chapter 45
Surface optimization: R-C cell
R-C cells are in use in oscillators or lters for instance. The major requirement
for an R-C cell is the time constant that denes either the cuto frequency
or the oscillation frequency. Except if noise considerations dene the resistor
value and then the capacitor, a good choice in integrated circuit is to minimize
the cell area so as to minimize its cost. Obviously the R-C cell area is the sum
of the capacitor area and the resistor area. The capacitor area is proportional
to the capacitance value and the resistor area is proportional to the resistance
value. This is a classic design situation where a sum must be minimized while
the product is kept constant.
AREA = CAREA + RAREA
CAREA = A · C
RAREA = B · R
τ =R·C
So:
τ
R=
C
τ
AREA = A · C + B ·
C
dAREA
Solving for
dC =0 leads to an extremal value for AREA.
dAREA B·τ
=A− =0
dC C2
A · C2 − B · τ = 0
r
B·τ
C=
A
r
A·τ
R=
B
√
RAREA = CAREA = A·B·τ
249
CHAPTER 45. SURFACE OPTIMIZATION: R-C CELL 250
45.1 Example
If an R-C cell with τ = 200µs has to be implemented in a process with a
capacitance density CA = 1 nF/mm2 = 10−3 F/m2 , with a sheet resistance
−6
RS = 1 kΩ/ and with a resistor width RW = 1 µm = 10 m.
First, lets calculate constants A and B:
CAREA
A=
C
C
CAREA =
CA
1
A= = 1000 m2 /F
CA
RAREA
B=
R
RAREA = RW · RL
R · RW
RL =
RS
RW 2
B= = 10−15 m2 /Ω
RS
Then:
r r
B·τ 10−15 · 2 · 10−4
C= = = 14.14 pF
A 1000
r r
A·τ 1000 · 2 · 10−4
R= = = 14.14 M Ω
B 10−15
√
AREA = 2 · A · B · τ = 28.20 · 10−9 m2
The resulting time constant is τ = 200µs as expected. If we play around

with R and C values:
For C = 10 pF , R = 20 M Ω
CAREA = A · C = 1000 · 10−11 = 10 · 10−9 m2
RAREA = B · R = 10−15 · 20 · 106 = 20 · 10−9 m2

AREA = 30 · 10−9 m2
CHAPTER 45. SURFACE OPTIMIZATION: R-C CELL 251
Figure 45.1:
For C = 20 pF , R = 10 M Ω
CAREA = A · C = 1000 · 2 · 10−11 = 20 · 10−9 m2
RAREA = B · R = 10−15 · 10 · 106 = 10 · 10−9 m2

AREA = 30 · 10−9 m2
In both cases, moving from the optimal cell either by increasing or decreasing
the capacitor increases the cell area. But we can notice that changing the
capacitor value by -30 / + 40 % with respect to optimum only aects area
by 7.1 %. The optimum sizing optimizes the cell area, but this optimum is
not very sharp. The following graph shows the R-C cell total area versus the
capacitance value:
Part V
Basic concepts
252
Chapter 46
Glossary
46.1 Conductance
Conductance, usually noted G is the inverse of resistance.46.3
Ohm's law can be expressed in two forms:
The direct: V =R·I

The inverse: I =G·V
46.1.1 Linear device

For a linear device:
I =G·V
I dI
G= =
V dV
46.1.2 Ane device

For an ane device:
I = G · (V − E)

I E
=G· 1− 6= G
V V
dI
G=
dV
46.1.3 Non linear device

For a non linear device:
Two conductance expressions can be dened:
The static conductance: G= I

V
The dynamic conductance: g= dI

dV
Traditionally, capital letters are used for static values and small letters are
used for dynamic values.Both the static and dynamic trans-conductance values
depend on the operating point.
253
CHAPTER 46. GLOSSARY 254
46.2 Operating point

An electrical circuit operating point is a state of equilibrium a circuit reaches
whenever this state does exist.
46.2.1 Example
A simple example is connecting a generator to a load. Each of the devices has
its own voltage-current characteristics. When they are connected together, the
voltage and the current are the same for the two devices. The system reaches
the point at the intersection of the two characteristics.
Figure 46.1: Generator-Load Operating Point
At the operating point, the Kirchho laws are satised. For complex cir-
cuits with many nodes and branches, the only practical method for nding the
operating point is to solve the Kirchho equations.
46.2.2 DC stability
The operating point can be DC unstable or DC stable.
46.2.2.1 Mechanical example
This is similar to a mechanical equilibrium. If a metal ball is placed inside a

cup, it will stay there: If some vibration move the ball a bit, it has to rise from
the bottom of the cup and gravity will bring it back to the bottom. Equilibrium
is statically stable. Now if a metal ball is placed on the top of another xed
large metal ball. Theoretically, it can stay there. But if a vibration moves it a
bit, it will move down as it moves from the top and gravity will move it further.
This equilibrium is statically unstable. For an electrical circuit, the equilibrium
point is called operating point and can be DC stable or DC unstable.
46.2.3 AC stability
If DC stable it can be AC unstable or AC stable.
46.2.3.1 Mechanical example
If a mass is hung to a spring, the system will nd an equilibrium dened by

the mass and the spring stiness. This equilibrium is statically stable. If a
y lands on the mass, the spring will get slightly longer to compensate for the
mass increase. If the y goes away, the mass will get back to the previous
point.
Now if someone pulls on the mass so as to create a signicant change in the
spring length and then releases the traction, what happens?
The mass will reach back its equilibrium point after some time but with
damped oscillation. The time or the number of periods it takes depends on the
damping factor. If damping is strong, system is dynamically stable. If reaches
back equilibrium without oscillation. If there is no damping at all, the system
will oscillate forever, it is dynamically unstable.
46.3 Resistance
46.3.1 Linear device
A pure resistor characteristics is linear.48.5
V =R·I
Coecient R is the resistance:
V dV
R= =
I dI
46.3.2 Ane device

Now, if we consider a battery cell and plot V the voltage across the cell versus
I the current through the cell, we notice an ane law:
V =E+R·I
where E is cell internal voltage and R the cell internal resistance.
Open circuit voltage (I = 0) is V 0 = E.

Short circuit current (V = 0) is I0 = − E
R
If we calculate ratio between V and I:
V E
= + R 6= R
I I
This value depends on I and is not equal to R. The cell internal resistance can
be extracted as:
dV
R=
dI
dV
This simple example shows that R= dI is a more general denition of resis-
tance, it works for linear and ane devices.
46.3.3 Non linear resistance

Now, let's consider a light bulb and let's sweep the voltage from 0 to the normal
operating voltage. At low voltage, current is low. The power that is dissipated
in the bulb is low so its temperature increase is low and the bulb exhibits a low
resistance. As the voltage is increased, the current increases, the dissipated
power increases and the temperature increases. As a result, the resistance
increases. So the voltage versus current curve slope increases when voltage and
current increase.If we plot the voltage versus current characteristics, we get
something like:
Figure 46.2: Static and Dynamic Impedance
The actual curve may be dierent from that but the principle does not
change. On such a characteristics, two resistances can be dened:
The static resistance: R = V

I This resistance is gured as the straight
line from the graph origin (0,0) to the point (V0,I0).
The dynamic resistance: r =dV v

dI = i This resistance is gured by the
curve slope around point (V0,I0). Slope value depends on V0 I0.
Traditionally, capital letters are used for static values and small letters are used
for dynamic values. Both the static and the dynamic resistance depend on the
operating point.46.2
46.3.4 Conclusion
Only purely linear devices have a constant static resistance. For such devices,
the dynamic resistance is equal to the static resistance. For all other devices,
ane or non linear, the static and the dynamic resistance depend on the oper-
ating point.
The dynamic resistance describes more accurately the device behavior around
the operating point.
46.4 Trans-conductance
As the name states, trans-conductance is a conductance46.1. Prex trans that
stands for transfer states that the current owing between two nodes depends
on the voltage between two other nodes. Trans-conductance is sometimes called
mutual conductance. This is the reason why trans-conductance use symbols
GM and gm.
I (C, D)
Gm =
V (A, B)
dI (C, D)
gm =
dV (A, B)
46.5 Trans-resistance
As the name states, trans-resistance is a resistance46.3. Prex trans that
stands for transfer states that the current owing between two nodes depends
on the voltage between two other nodes. Trans-resistance is sometimes called
mutual resistance. This is the reason why trans-resistance use symbols RM
and rm.
V (A, B)
Rm =
I (C, D)
dV (A, B)
gm =
dI (C, D)
Chapter 47
Maths for electronic designers
This chapter is intended to introduce or refresh some useful math concepts for
designers. It is not a math course, math specialists should not read this section
!
47.1 Statistics
As a start point, let's play dice.
47.1.1 One die statistics

If we play with only one die, we can get values from 1 to 6 with the same
probability. Average value over a large number of runs is 3.5. Probability of
2
getting a value between 3 and 4 inclusively is
6 . The sum of probabilities is 1,
obviously: The die has to give a value, and that value has to be between 1 and
6!
47.1.2 Two dice statistics

Now if we play with two dice and sum up the values, we can range from 2 to
12. But what about the probabilities? You can write in a table the possible
values for one die and for each of these the possible values of the other die.
This is easy to check in a spreadsheet like Excel or Open-Oce.org Calc.
258
CHAPTER 47. MATHS FOR ELECTRONIC DESIGNERS 259
Die 1 Die 2 Sum
1 1 2
1 2 3
1 3 4
1 4 5
1 5 6
1 6 7
2 1 3
2 2 4
2 3 5
2 4 6
2 5 7
2 6 8
3 1 4
3 2 5
3 3 6
3 4 7
3 5 8
3 6 9
4 1 5
4 2 6
4 3 7
4 4 8
4 5 9
4 6 10
5 1 6
5 2 7
5 3 8
5 4 9
5 5 10
5 6 11
6 1 7
6 2 8
6 3 9
6 4 10
6 5 11
6 6 12
You get 36 possibilities. In the rightmost column that sums the dice values,
you can see that:
Values 2 and 12 occur just once.
Values 3 and 11 occur twice.
Values 4 and 10 occur three times.
Values 5 and 9 occur four times.
Values 6 and 8 occur ve times.
Value 7 occurs six times.

Let's plot probability versus value:
Figure 47.1: Two dice probability chart
Values for each die have the same probabilities but the situation is com-
pletely dierent for the sum. Value 7 appears twice more probable than 4 and
10.
Average value per die is still 3.5. But now, probability of getting a value
16
between 3 and 4 (between 6 and 8 for the sum) inclusively is
36 . It has been
4
multiplied by
3 with respect to the single die play.
47.1.3 Three dice statistics

With three dice, values range from 3 to 18. Again this can be done in a
spreadsheet. There are 63 = 216 possibilities with the following occurrences:
Values 3 and 18 occur just once.
Values 4 and 17 occur three times.
Values 5 and 16 occur six times.
Values 6 and 15 occur ten times.
Values 7 and 14 occur fteen times.
Values 8 and 13 occur twenty one times.

Values 9 and 12 occur twenty ve times.
Values 10 and 11 occur twenty seven times.
Average per die is still 3.5 and now probability of getting a value between 3
104 13
and 4 inclusively is
216 . It has been multiplied by 9 with respect to the one
die play.
47.1.4 Graphs
We can plot together the graphs for 1, 2 and 3 dice. To allow comparison, x
axis gives value par die. Y axis plot probabilities for the three games.
Figure 47.2: One to Three dice probability chart
Note that the denite integral of all these curves from 1 to 6 are equal
to 1. Here denite integral is an improper term as we deal with integers.
The right expression would be summing up the values times the step for each
curve.
From this simple example, we can see that summing up random variables
with uniformly distributed values results in non uniformly distributed values.
The curve with three dice is bell shaped. From three uniform random variables
up, the behavior starts looking like a Gaussian curve. With four dice, let's
compare the density of probability to the Gaussian law:
Figure 47.3: Four dice vs. Gaussian
Pretty good agreement!

This explains why many statistical measurement appear as Gaussian. If
four or more independent physical parameters condition the measured data,
even if each parameter is uniformly distributed, just as for our dice, the data
distribution is close to a Gaussian.
47.1.5 Conclusion
From a simple example, we have established a useful law for designers: statisti-
cal improvement. If a component is aected by a given tolerance, connecting a
number of components as a single component results in an improved tolerance
at the expense of area. The tolerance improves as the inverse of the square
root of the number.
Chapter 48
Physics for electronic designers
This chapter is intended to introduce or refresh some useful physics concepts

for designers.
48.1 Carriers in dierent media

One always thinks of electrons as the carrier for electricity. This is true in
metals. But in other media, it is not always the case. Think of an electrolyte.
In this media, carriers are ions. In semiconductors, carriers are electrons or
holes depending on the material doping that denes polarity.
How can we say that?

The fundamental experiment showing this, that can also determine whether
a piece of semiconductor is P type or N type is the Hall eect. If a current
ows in a material and a magnetic eld is applied perpendicular to the cur-
rent, the carriers trajectory is bent in a direction that depends on the carriers
polarity. Then charges accumulate in a direction that is perpendicular to both
the current and the magnetic eld until the resulting electric eld compen-
sates for the magnetic eld so that the carriers trajectory is restored. In that
equilibrium state, the transverse voltage is proportional to the current and to
the magnetic eld. The voltage polarity depends on the material polarity. It
can be checked that both voltage polarities exist depending on the material
doping. This demonstrates that in N type material, carriers are negative and
in P type material, they are positive. These positive carriers are called holes
as they look like a missing electron. They weigh about three times as much
as electrons. This is normal since in a semiconductor material that has four
peripheral electrons per atom with doping atoms with only three peripheral
electrons, moving one hole in a given direction is somewhat equivalent to mov-
ing three electrons in the opposite direction.
What happens when current ows from one media to another one?
This is typically what happens when metal connects to P type semiconduc-
tor. In metals carriers are electrons. In P type semiconductors, carriers are
holes. The current carrier changes in transition regions.
263
CHAPTER 48. PHYSICS FOR ELECTRONIC DESIGNERS 264
Figure 48.1:
48.2 Combination of equilibrium states

If the input of a linear system is the sum of two elementary inputs, the output
is the sum of the elementary outputs resulting each from one of the elementary
inputs.
Out = A · In
Now:
If In = 0, Out = Out0 = 0
If In = x1, Out = Out1 = A · x1
If In = x2, Out = Out2 = A · x2
If In = x1 + x2, Out = A · (x1 + x2) = Out1 + Out2
This property is often used to simplify circuit calculations as it allows contri-
butions to be calculated separately and summed up later:
It can be noted that this property applies only to linear systems. It does
not apply even to ane systems and neither to non linear systems. Practically,
if an ane system exhibits a small oset term, this property can be considered
granted and it is often used:
Out = A · In + B
Now:
If In = 0, Out = Out0 = B
If In = x1, Out = Out1 = A · x1 + B
If In = x2, Out = Out2 = A · x2 + B
If In = x1 + x2, Out = A · (x1 + x2) + B = Out1 + Out2 − B
If B ' 0, then Out ' Out1 + Out2
However, results should always be checked in such cases as they are poten-
tially incorrect
48.3 Kirchho laws

In any electric circuit at equilibrium, the two Kirchho laws apply:
The Kirchho Current Law (KCL)
The Kirchho Voltage Law (KVL)
48.3.1 Kirchho Current Law

This law states that the sum of currents at a node is zero.
Figure 48.2:
48.3.2 Kirchho Voltage Law

This law states that the sum of voltages around a loop is zero.
48.4 Norton-Thévenin equivalent circuits

Circuit theory makes extensive use of ideal voltage and current sources.
An ideal voltage source generates a voltage that does not depend on

current.
An ideal current source generates a current whatever the voltage.
Actual sources exhibit some internal resistance that make them non ideal. A
voltage source has its internal resistance connected in series while a current
source has its internal resistance connected in parallel. Internal resistance is
usually low for a voltage source and high for a current source. However, low
and high are relative values and one can wonder about medium internal
resistances.Is a source with a medium internal resistance a voltage source or
a current source?
Well, it depends... It depends on the load. We can say that if a source
internal resistance is lower than the load resistance, we are more on the voltage
source side. On the contrary, if a source internal resistance is higher than the
load resistance, we are more on the current source side. But we can go further:
If we hide a source and its internal impedance in a box and give access only to
the external connections, there is no means of making the dierence between a
voltage source or a current source only by measuring the voltage versus current
characteristics. They are equivalent. This is the basis for the Norton-Thévenin
equivalence or Norton-Thévenin transform.
To go even further, we can say that we are always allowed to use that
transform if it makes calculations easier.
48.5 Ohm's law

48.6 P-N junction.
P-N junctions are extremely common in ICs. They are the base of the bipolar
transistor operation. They exist in MOS transistors and in many other com-
ponents as parasitic or isolation diodes. It is then important to understand the
operation of the P-N junctions.
As the name states, a PN junction is made from two dierent semiconductor
materials in contact.
48.6.1 PN junction in equilibrium.

48.6.2 Reverse biased PN junction.
48.6.3 Forward biased PN junction.
48.6.4 Illuminated reverse biased PN junction.
48.6.5 Two interacting junctions.
48.7 Propagation
Let's make an experiment again. A pulse generator, 3 meters of coax cable,
some resistors and an oscilloscope are sucient to demonstrate propagation.
48.8 Heat transfer

Heat ows from hot points to cold points in the global systems behavior at-
tempts to reach a minimum energy state. Heat transfer uses three distinct
mechanisms even though in many situations these mechanisms superimpose:
Conduction
Convection
Radiation
48.8.1 Conduction
This mechanism takes place in materials. At microscopic scale, it is related
to transferring atoms thermal agitation to neighbors. At large scale, conduc-
tion is described by a diusion equation. Heat ux (power) is proportional to
temperature gradient and to material thermal conductivity. This behavior is
consistent with ohms law and a thermal resistance can be dened. Thanks to
material specic heat, conduction is not instantaneous. Dynamic behavior can
be described by a distributed R-C network
48.8.2 Convection
In gases and liquids, convection superimposes with conduction. When a cer-
tain amount of material is heated, it dilates. Since its mass is constant, its
density decreases. Then Archimedes thrust takes place and pushes the mate-
rial up while colder material replaces it. This is natural convection. Again,
this mechanism tends to an equilibrium state. Since Archimedes thrust exists
only in a gravity eld, convection does not exist without gravity. Convection
can signicantly reduce thermal resistance with respect to conduction only. In
order to reduce thermal resistance further, forced convection can be used. A
fan increases the air ow or a pump increases the water ow to increases the
renewal rate at the hot point and evacuate more power. There is no simple law
for convection that depends on many factors and usually requires experimen-
tation.
48.8.3 Radiation
Materials above absolute zero temperature radiate power as electromagnetic
waves. When a wave reaches a material, it is partly absorbed and heats the
material. This mechanism tends to balance temperatures of interacting mate-
rials. Radiated power is proportional to an emission coecient, to Stephan's
°
constant and to the power 4 of absolute temperature. It becomes dominant at
high temperatures usually several hundreds of C. For semiconductor devices
it is usually not dominant but can slightly reduce thermal resistance. This is
basically why heat sinks are black that exhibits a higher emission coecient
than natural metal colors.
48.9 Resistance between two cylinders

The calculation is based on integration. Let's consider two concentric cylinders
with length L and radius r and r+dr, where dr is a very small distance. The
cylinders areas are very similar and equal to:
A=2·π·r·L
Resistance is proportional to resistivity ρ, proportional to current ow
length and inversely proportional to area. In this case length is equal to dr
then:
dr
dR = ρ ·
2·π·r·L
Now, we can sum up these elementary resistances from inner radius R1 to
outer radius R2:
R2
ρ ρ R2 ρ ρ R2
R= ·dr = ·[ln r]R1 = ·(ln R2 − ln R1) = ·ln
R1 2·π·r·L 2·π·L 2·π·L 2·π·L R1
As a log is involved, the resistance does not change much. And the re-
sistance does not depend on R1 or R2 absolute value but it depends on the
ratio.
In integrated circuits, all the components are located at the surface of the
silicon chip, so usually only cylinder halves have to be considered. The resis-
tance is then doubled:
ρ R2
R= · ln
π·L R1
48.10 Resistance between two spheres

The calculation is based on integration. Let's consider two concentric spheres
with radius r and r+dr, where dr is a very small distance. The spheres areas
are very similar and equal to:
A = 4 · π · r2
Resistance is proportional to resistivity ρ, proportional to current ow
length and inversely proportional to area. In this case length is equal to dr
then:
dr
dR = ρ ·
4 · π · r2
Now, we can sum up these elementary resistances from inner radius R1 to
outer radius R2:
R2 R2
ρ ρ −1 ρ 1 1
R= · dr = · = · −
R1 4 · π · r2 4·π r R1 4·π R1 R2
If R2 → ∞:
ρ
R=
4 · π · R1
This resistance characterizes the inner sphere and does not depend on the
location of the outer sphere. The outer surface can dier from a sphere, the
result does not change.
An intermediate case is R1 R2:
ρ
R'
4 · π · R1
In integrated circuits, all the components are located at the surface of the
silicon chip, so usually only sphere halves have to be considered. The resistance
is then doubled:
ρ
R'
2 · π · R1
This calculation takes place when it comes to evaluate the electrical resis-
tance of a substrate or well tie or the thermal resistance of a small component.
Chapter 49
Electronics for electronic designers
This chapter is intended to introduce or refresh some useful electronics concepts

with emphasis on design.
49.1 Feedback
Feedback is a very common technique that is used extensively in electronic
circuits. The basic principle of feedback, as its name states it, is to feed the
output of the circuit back to an input so as to compare the actual output to
the target and use the dierence information to modify the output. This is a
powerful technique to improve output accuracy with respect to a circuit that
would not use feedback. When feedback is used, the circuit looks like a loop
and is often called servo-loop, feedback loop and sometimes loop.
When a loop is used, a concern always exist with stability. If the output
phase shift is large enough, the correction may not drive the system in a stable
state but it may enter into oscillation.
The general schematic for a loop is:
Open loop gain:
GOL = A · B
Closed loop gain:
A
GCL =
1+A·B
The major interest of a feedback system appears when product A·B is
much larger than 1. In this case:
A 1
GCL ' =
A·B B
The closed loop gain in this case does not depend on A. Usually, A is an
amplier and B is a voltage divider. Gain A is subject to inaccuracies while B
can be made fairly accurate.
Figure 49.1:
269
CHAPTER 49. ELECTRONICS FOR ELECTRONIC DESIGNERS 270
Figure 49.2:
As A and B terms depend on frequency, it may happen at some frequency

A · B = −1
°
that which means that open loop gain module is 1 and open loop
gain phase is -180 .
If this occurs, the closed loop gain gets innite for that frequency.
What does that mean?

This means that the output can be non zero even if input is extremely
small. In particular, even without input signal, input noise is always present.
The loop will selectively amplify the noise at a particular frequency and will
create a signal. This is the way harmonic oscillators are built. So, if open loop
gain equals -1, the loop is an oscillator. If this is not the goal, this situation
must by avoided. This is called stabilizing the loop.
So far, the loop was considered as an abstract object and signals in the loop
are undened.
49.2 Impedance matching circuits

When a generator exhibits an internal impedance Z, a question can be:
What is the best possible load impedance for that generator?

To answer this question, let's start with an experiment. Let's consider a
circuit built from a voltage source with open circuit voltage V 0 = 10 V , with
internal resistance RIN T = 10 Ω and a load resistance RLOAD . What about
the voltage, the current, the power?
RLOAD
V =V0·
RIN T + RLOAD
V0
I=
RIN T + RLOAD
2
V0
P = RLOAD ·
RIN T + RLOAD
Now let's sweep the load resistance RLOAD from 0 to ∞ and lets plot the
voltage, the current and the power.
49.3 Simple passive circuits

The impedance and gain versus frequency characteristics of simple passive cir-
cuits are important as they allow building equivalent schematic and simplify
circuit calculations.
49.3.1 R-C High pass lter

This lter lters out low frequencies. Schematic is:
Transfer function is:
Cuto frequency is:
Figure 49.3:
Figure 49.4:
Figure 49.5:
1
f0 =
2·π·R·C
Input and output impedance expressions are:
Group delay is:
It must be noted that source and load impedance can signicantly impact
the transfer function.
49.3.2 R-C Low pass lter

This lter lters out low frequencies. Schematic is:
Transfer function is:
Cuto frequency is:
1
f0 =
2·π·R·C
Input and output impedance expressions are:
Group delay is:
It must be noted that source and load impedance can signicantly impact
the transfer function.
49.3.3 R-C parallel impedance

When a resistor and a capacitor are connected in parallel, resulting impedance
versus frequency is:
If driven by a current source, this cell achieves a rst order low-pass lter
function. Cuto frequency is:
1
f0 =
2·π·R·C
When a circuit element exhibits an impedance versus frequency that looks
like that of a parallel R-C cell, it can be modeled as a parallel R-C cell and
behaves the same.
Figure 49.6:
Figure 49.7:
Figure 49.8:
Figure 49.9:
49.3.4 R-C series impedance

49.3.5 R-L High pass lter
49.3.6 R-L Low pass lter
49.3.7 R-L parallel impedance
49.3.8 R-L series impedance
49.4 Miller eect
This eect was originally a parasitic eect. In ICs, it is a common practice to
use this eect.
If an amplier with voltage gain A, innite input impedance and negligible
output impedance is shorted by an impedance Z between input and output:
What is the input impedance of the system? The input impedance is:
V IN
ZIN =
IIN
Input current, by assumption, ows only in impedance Z:
V IN − V OU T
IIN =
Z
And we know that:
V OU T = A · V IN
Then:
V IN · (1 − A)
IIN =
Z
So:
V IN Z
ZIN = =
IIN 1−A
In case A is negative and large:
Z
ZIN '
|A|
Basically, the Miller eect dramatically reduces an inverting amplier input
impedance if some coupling exists between input and output that behaves like
an impedance.
Figure 49.10:
Figure 49.11:
Figure 49.12:
In particular, if coupling impedance Z is a capacitance C:
1
Z=
2·π·f ·C
1
ZIN '
2 · π · f · |A| · C
Which is equivalent to the impedance of a capacitor:
C 0 = |A| · C
The input capacitance appears multiplied by the amplier gain! This is a

concern for any common-emitter or common-source amplifying stage as they
are inverting. The collector-base or drain-gate capacitance causes an increase in
the input capacitance that can, in turn, reduce the bandwidth or the slew-rate
by a load eect on the driving stage.
In ICs, Miller eect is often used to stabilize loops as it allows large apparent
capacitors without using large capacitors, saving silicon area then minimizing
cost. The loop architecture is generally tailored so as to create a dominant pole
at the input of a large gain stage by using Miller eect. Sometimes, an extra
amplier is used just for the purpose of stabilizing the loop since the amplier
that multiplies the capacitance is often smaller than the equivalent capacitor.
The drawback of this method is the amplier current consumption.
49.5 Cascode amplier

The so called cascode amplier has been created long time ago to limit the
parasitic Miller eect. A cascode amplier is built by stacking a common
emitter/source amplier and a common base/gate stage:
The common emitter/source amplier would suer from the Miller eect
but since its input to output gain is -1, the eect is limited to an added equiv-
alent input capacitance twice the input to output capacitance value.
The common base/gate stage does not exhibit any parasitic Miller eect
since its input is driven with a constant voltage and can be bypassed suitably.
In addition, the common base/gate transistor can be made small as it does
not impact the overall noise signicantly and this improves the output cuto
frequency.
The two drawbacks of the cascode amplier are:
The need for two transistors instead of one, but this is not a concern in
an IC.
The need for a larger supply voltage or a smaller available swing.

49.6 Equivalent cuto frequency of two rst order

low-pass lter
When a circuit exhibits two rst order low-pass cuto frequencies, the equiv-
alent cuto frequency, the -3 dB point depends of course of the two cuto
frequencies.
Chapter 50
Materials properties
Several materials are commonly used in integrated circuits. These materials

are mainly silicon, and silicon dioxide. Other materials of interest are mold
compound, and FR4 epoxy as they are in the immediate environment of ICs.
50.1 Electrical data

50.1.1 Silicon
Silicon is the most widely used material inside ICs. All components but true
capacitors are built from silicon.
50.1.1.1 Dielectric constant
εR = 12.9
50.1.1.2 Carriers Mobility
In semiconductors, two types of carriers exist:
Electrons
Holes
Two mechanisms limit mobility:
Free carriers density
Interaction with lattice
Depending on doping level, actual mobility is dened by one mechanism or the

other.
50.1.1.3 Resistivity
50.1.1.4 Breakdown electrical eld
50.1.2 Silicon dioxide

Silicon oxide is probably the most used material after silicon in ICs. Capacitors
are built from metal and oxide and the dielectric layers between connection
layers are made from oxide.
275
CHAPTER 50. MATERIALS PROPERTIES 276
εR = 3.9
EB = 109 V /m
50.1.3 Silicon nitride

Silicon nitride is used as a passivation layer over the metal stack and nal oxide.
εR =
EB = V /m
50.1.4 Mold compound

Mold compound is the material surrounding silicon in molded plastic packaged
ICs.
εR =
EB = V /m
50.1.5 FR4 epoxy

PCBs, often made from FR4 material are the ICs environment outside the
package.
εR =
EB = V /m
50.2 Thermal data

50.2.1 Silicon
50.2.1.1 Thermal conductivity
50.2.1.2 Thermal coecient of expansion
50.2.1.3 Specic heat



50.2.5 FR4 epoxy

50.3 Mechanical data

50.3.1 Silicon
50.3.1.1 Density
50.3.1.2 Young's modulus
50.3.1.3 Tensile strength

50.3.2.1 Density

50.3.3.1 Density

50.3.4.1 Density

Chapter 51
Tools
A number of CAD tools are helpful in day to day design even though the
real design tool is the one the designer has between his ears. As the acronym
suggests, CAD tool are intended to help and assist the designer in his task.
51.1 Spreadsheet
Spreadsheet tools are among the simplest and most available ones. A prob-
lem that can be solved using a spreadsheet should not be solved with a more
complex tool. This is a matter of eciency but also it requires to formalize
the problem properly which is the rst step of solving. Microsoft Excel and
OpenOce Calc are among the most polular spreadsheet tools.
51.1.1 Using a spreadsheet to manage specications

51.1.2 Using a spreadsheet to perform calculations
51.2 CAS (Computer Algebra System)
CAS tools such as eigenmath or xcas are helpful to perform symbolic calcula-
tions.
51.2.1 Using xcas to solve a circuit tranfer function

51.3 Behavioral simulators
These tools such as Matlab/Simulink or Scilab/Xcos, but also most electrical
simulators through behavioral description languages are helpful to dene blocks
specication and to check complex systems operation.
51.4 Electrical simulators

These tools, more or less derived from ancestor program SPICE are probably
the most important tools for analog designers. LTSPICE is probably the most
eective free SPICE derived simulator.
279
Chapter 52
Index
280
Index
A
Architecture, 56
C
Cells, 32
S
Sizing, 62
Specication, 49
281

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Analog IC Designer's Handbook

September 23, 2020

Top-Down method at work in analog IC design

I Analog integrated circuit development 14

4 TOP-DOWN Design Flow 35

17 Basic analog IC design elements 88

19 MOS transistors 110

20 Common characteristics of bipolar and MOS transistors 124

21.4 Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

24 ESD devices 153

25 Parasitic components 157

26 Substrate related issues 162

26.3 Reducing sensitivity . . . . . . . . . . . . . . . . . . . . . . . . 164

27 Package considerations 165

28 PCB considerations 167

29 Test considerations 169

31 Basic integrated building blocks 172

32 Tentative analog functions classication 178

IIIDesign Examples 181

34 MOS Voltage follower 185

35 Constant gm cell 187

36 Band-gap reference voltage generator 188

37 Linear Voltage regulator 190

37.3 Short circuit protection . . . . . . . . . . . . . . . . . . . . . . 191

38 Sigma-Delta Modulator 192

40 The dependency graph method 238

41 The gmin stepping method 240

42 The noise peaking method 242

43 Robust design techniques 243

44 Safe design techniques 248

45 Surface optimization: R-C cell 249

V Basic concepts 252

47 Maths for electronic designers 258

49 Electronics for electronic designers 269

50 Materials properties 275

1.1 Product Life . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.1 Development Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1 Hierarchical Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

18.1 Bipolar transistors symbols . . . . . . . . . . . . . . . . . . . . . . 90

18.2 Vertical NPN Cross-section . . . . . . . . . . . . . . . . . . . . . . 91

19.1 NMOS and PMOS symbols . . . . . . . . . . . . . . . . . . . . . . 110

21.1 Resistor symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

21.18Eect of gradient on 4 resistors . . . . . . . . . . . . . . . . . . . . 141

22.1 Capacitor symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

24.1 HBM test bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

25.1 IR Drop Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . 158

26.1 Substrate attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . 163

31.1 Diode connected transistors . . . . . . . . . . . . . . . . . . . . . . 173

33.1 Square Root circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

34.1 MOS Follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

38.1 Delta modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

39.1 Two inverters loop . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

46.1 Generator-Load Operating Point . . . . . . . . . . . . . . . . . . . 254

47.1 Two dice probability chart . . . . . . . . . . . . . . . . . . . . . . . 260

Analog integrated circuit

 If you know and practice methods that have proved to be ecient, go on

 If you are interested in looking at methods that might be dierent from

1.1 TOP-DOWN design methodology example

Common arguments against the TOP-DOWN method are that it is less

32 Tentative analog functions classication 178

21.18Eect of gradient on 4 resistors . . . . . . . . . . . . . . . . . . . . 141

If you know and practice methods that have proved to be ecient, go on

If you are interested in looking at methods that might be dierent from

TOP-DOWN design can be even more creative than BOTTOM-UP de-

The time it takes to write a specication is really worth it.

1.1.1 Why dening before doing?

Starting with the number of oors undened can result in a house

Another approach could be to oversize the basement so that it can support

Again, specifying rst is worth the money.

And specifying does not disable creativity nor inspiration...

It would be useless to think of a single oor rooms organization if nally

Most uncontrolled delays and costs result from rework.

Dening things before doing.

Organizing the work ow and sharing the work load.

Dening the product functions.

Dening the product performances.

A product denition is usually a list of functions it must achieve together with

Production capacity must be able to face the market demand.

Production cost with respect to sales price must ensure revenue.

Production quality and consistency must satisfy customers.

A new product has grabbed the market

The product primary use has disappeared or narrowed

Parts can be required for maintenance.

The volumes for maintenance have been under-evaluated.

Specication is available and can be used to restart the design process.

Design documentation is available and helps the designers.

Good designs are robust enough to be transferred to another technology

Everything starts with a Specication phase: Dening what is to be

Once the design is completed, the product can be manufactured. Manu-

If validation succeeds, the development is over and it's time for

If validation fails, some rework is required, either changing the spec-

be evaluated. Denition correctness with respect to customer need must be

IC Manufacturing requires expensive tooling such as masks and wafer

IC Manufacturing process is highly collective: Thousands of products are

The product is a single piece of silicon containing thousands to millions

When it comes to specify an IC, the rst questions are really:

After the design is completed, a Data-sheet is issued. This document

Checking the circuit versus its specication should ideally be done by

Checking cells versus expectations should ideally be done by the designers

During the specication step, data are periodically exchanged between

The design phase as a whole is a loop and even a recursive loop as we

Manufacturing normally includes process control at every step.

includes the required elements for manufacturing the product eciently:

Implementing and validating these choices.

Material. The material the object will be made from.

Shape. The global object shape.

Size. The object physical dimensions.

The material has intrinsic properties such as hardness, resistivity, or

A list of options to choose from.

A set of criteria to compare options and make a choice.

Technical criteria like performance or reliability