A

Project Report
On
CLOCK GENERATOR WITH ALARM
Submitted to
in partial fulfilment of the requirement for the award of Degree of
BACHELOR OF TECHNOLOGY
In

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Submitted by

B Sai Deepthi {N190115}

G Sharon {R190834}

N Gayathri {R190047}

N Mounika {R190881}

Under the Guidance of

D.DEVIKA (M.Tech)
Assistant Professor.
Department of E.C.E

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
RAGIV GANDHI UNIVERSITY OF KNOWLEDGE AND TECHNOLOGIES

R.K.Valley, Vempalli(M), Y.S.R. Kadapa(D), Andhra Pradesh, 516330.

(2021 – 2025)

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 1|Page

 DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
RAGIV GANDHI UNIVERSITY OF KNOWLEDGE AND TECHNOLOGIES

R.K.Valley, Vempalli(M), Y.S.R. Kadapa(D), Andhra Pradesh, 516330.

(2021 – 2025)

CERTIFICATE

This is to certify that the project report entitled “CLOCK GENERATOR WITH ALARM”
bonafide record of the project work done and submitted by
B Sai Deepthi {N190115}
G Sharon {R190834}
N Gayathri {R190512}
N Mounika {R190368}
for the partial fulfilment of the requirements for the award of B.Tech Degree in ELECTRONICS
AND COMMUNICATION ENGINEERING, RGUKT RK Valley.

SUPERVISOR (GUIDE) Head of the Department

D. Devika MOHAN RAJU
Assistant Professor Assistant Professor
RGUKT,RK Valley RGUKT,RK Valley
Kadapa-516330 Kadapa -516330
External Viva-Voce Exam Held on

INTERNAL EXAMINER EXTERNAL EXAMINER

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 2|Page

 DECLARATION
We hereby declare that the project report entitled “CLOCK GENERATOR WITH ALARM”

submitted to the Department of ELECTRONICS AND COMMUNICATION ENGINEERING in partial

fulfilment of requirements to complete Mini Project in 3 rd year in B.Tech. This project is the result of our
own effort.
Project Associates
B Sai Deepthi {N190115}
G Sharon {R190834}
N Gayathri {R190047}
N Mounika {R190881}

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 3|Page

 ACKNOWLEDGEMENT
An endeavor of a long period can be successful only with the advice of many well wishers. I take this
opportunity to express my deep gratitude and appreciation to all those who encouraged for successful
completion of the project work.
I am thankful to my project guide Ms. D. DEVIKA, Assistant Professor in the Department of E.C.E,
RAGIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, R.K. Valley, for her valuable
guidance and suggestions in analyzing and testing through the period, till the end of the project completion.
My special thanks to Mr. M. MOHAN RAJU, Head of the Department of E.C.E, RAGIV GANDHI
UNIVERSITY OF KNOWLEDGE AND TECHNOLOGIES, R.K. Valley, during the progress of project
work, for his timely suggestions and help inspite of his busy schedule.
We have immense please in expressing our heartly thanks to our director Mr. A.V.S S KUMARA
SWAMI GUPTA.
Finally, I wish to convey my gratitude and express sincere thanks to all P.R.C (Project Review
Committee) members, friends and lab technicians, one and all who have helped to complete the project work
successfully.

Project Associates
B Sai Deepthi {N190115}
G Sharon {R190834}
N Gayathri {R190047}
N Mounika {R190881}

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 4|Page

 ABSTRACT

Nowadays everybody is using clocks and Alarms.Without a Clock it’s too difficult to get pass a day .It plays a
vital role in daily life. Clocks are being used to know the exact time.Alarms are used to wakeup ,set reminder
at particular time .Without alarms we cannot wakeup on time due laziness or tired.Alarms are used for Time
management.

We are implementing “CLOCK GENERATOR WITH ALARM”.So design of clock along with alarm is
needed.At first we are generating a clock.

The clock generated is in 24-hour format.After generating the clock ,we are initializing the clock time to a
particular value in order to set the Alarm.Then after we Enable and disable the alarm. After sometime we need
to stop the alarm and the clock should be operated normally.

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 5|Page

 INDEX

CHAPTERS TITLE PAGE NO

- Title Page 1
- Certificate 2
- Declaration 3
- Acknowledgement 4
- Abstract 5
- Index 6-7
Chapter - 1 Introduction 8-9
1.Traditional analogue clocks
2.Digital alarm clocks
3.Existing Technologies
Chapter - 2 Overview of Verilog Programming 10
Language
2.1 Concise Syntax
2.2 Event-Driven Modeling
2.3 Hardware Description:
Chapter - 3 Importance of Clock Generator With 11
Alarm
3.1 Importance
3.2 User Validation
3.3 Objective
Chapter - 4 4.1 Component 12
4.2 Verilog Language
4.3 Using Verilog For Simulation
Chapter - 5 5.1 Features/Objectives 13-14
5.2 Block Diagram
5.3Flow Chart
Chapter - 6 Specifications 15-16
Chapter - 7 Code 17-20
Chapter - 8 Testbench 21-24
Chapter - 9 Output Waveform 25
Chapter - 10 10.1 Proposed Technoloy 26-30
10.2 Advantages of Alarm Clock
10.3 Disadvantages of Alarm Clock
10.4 Conclusion
RGUKT RK VALLEY, Dept. of E.C.E, 10.5 Future Scope
Idupulapaya, Kadapa 6|Page
10.6 Contributions
 Chapter - 9 Output Waveform 25

Chapter - 10 10.1 Proposed Technoloy 26-30

10.2 Advantages of Alarm Clock
10.3 Disadvantages of Alarm Clock
10.4 Conclusion
10.5 Future Scope
10.6 Contributions

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 7|Page

 CHAPTER – 1

INTRODUCTION

An alarm clock is a clock that is design to alert an individual or group of individual at a specified time. The
primary function of this clock is to awaken people from there night’s sleep or short naps.We are generating a
clock with 7 output signals including alarm signal, hour,minute,and second. The clock generated is in a 24
hour format .Alarm have been in use for centuries because they slove a real problems-ensuring wake up on time.
The First alarm clock was invented in 1787 by Levi Hulchins in the USA.But it rings at 4 o’clock in the
morning.The first alarm with mechanical and adjustable time was palented in 1847 by French Antoine Redier.
The first radio alarm clock was invented by James F.Reynolds,in the 1940’s and another design was also
invented by Paul L.Schroth.
Alarm are used in mobile phone,watches and computers.Many alarm clocks have radio
receivers that can be set to start playing at specified time and are known has clock radios.Some alarm clock
can set multiple alarm.
There are two types of alarm clocks

1.Traditional analogue clocks:

Traditional mechanical alarm clocks have one are two bells that ring by means of a
mainspring that power a gear to quickly move a hammer back and forth between two bells or
between the interior sides of a single bell.the bell is rung by an electromagnetic circuit and
armature to turn the circuit on and off repeatedly.

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 8|Page

2.Digital alarm clocks:

Digital alarm clocks can make other noises.Simple battery-powered alarm clocks make a lound buzzing are
beeping sound to wake a sleeper,while novelty alarm clock can speak,laugh,sing,or play sound from nature.
The earliest patent for a digital Alarm clock was registered by D.E Protzmann and others on October 23,1956,
in the United States.Protzmann and his associates also patented another digital clock in 1970,which was said to
use a minimal amount of moving parts.

3.Existing Technologies:

1. Computer Alarms:Alarm clock software programs have been developed for personal computers.They are
Web based alarm clocks,some of which may allow a virtually unlimited number of alarm times and
personalized tones.However,unlike mobile phone alarms ,they have some limitations.They do not work when the
computer shut off or in sleep mode.

2.Mobile phone Alarms:Many modern mobile phones features built-in alarm clock that do not need the phone
to be switched on for the alarm to ring off.Some of these mobile phones features the ability for the user to set
the alarms ringtone and in some cases music can be downloaded to the phone and then choosen to play for
walking.

3.Watch Alarms:The vibrations of a mechanical alarm also offer a real connection between the wearer and the
watch.The alarm itself was set within a 12-hour period and attached to a cam under a dial.When triggered ,the
cam activates a lever which then releases the energy from the alarms mainspring to power a hammer.

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 9|Page

 CHAPTER - 2
2. Overview of Verilog Programming Language
2.1 Concise Syntax:

Verilog is known for its concise and powerful syntax, allowing developers to describe complex
hardware behavior in a clear and efficient manner.

2.2 Event-Driven Modeling:

Verilog uses an event driven simulation model, making it an ideal choice for digital design and
verification, especially for systems with asynchronous components.

2.3 Hardware Description:

It is a hardware description language, enabling designers to model and simulate digital systems and
circuits, making it an integral language in the field of electronic design automation.

Fig. 1

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 10 | P a g e

 CHAPTER - 3
3. Importance of Clock Generator With Alarm

3.1 Importance:

PDigital clocks are inexpensive and easy to use. Depending on the product designs, these devices can
be small hence easy to incorporate into all kinds of devices such as radios, cars, computers, cell
phones, standard ovens, televisions etc. These clocks give more accurate time readings than regular
analog clocks.Moreover these devices are easier to understand and have an easier time these devices
are easier to understand and have an easier time concept. The alarm and stopwatch functionalities
are also straight forward.

3.2 User Validation:

● 12-hour and 24-hour time formats

●  Different displays for hours, minutes and seconds
●  Customizable intensity of buzzer sounds for alarm

3.3 : Objective

we have implemented both 12-hour and 24-hour digital clocks in Verilog and Proteus. Digital clocks
are preferred nowadays for precise time keeping. These are also very easy to use. In our clock we have
also implemented alarm and stopwatch functionality. So, users can set time according to their
requirements. The outputs are shown on seven-segment displays, hence seven-segment controllers are
also implemented.

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 11 | P a g e

 CHAPTER - 4
4.1 Component:

Xilinx Software:Xilinx solutions enables smarter,connected,and differentiated systems,integrating

the highest levels of software-based intelligence with hardware optimization and any-to-any
Connectivity. Xilinx serves the aerospace and defense industry with
commercial,industrial,military,and space grade products.

The xilinx ISE is primarily used for circuit synthesis and design,while ISIM or the
ModelSim logic simulator is used for system-level testing.

The languages used in xilinx are C and C++.

4.2 Verilog Language:

Verilog is one fo the two most common Hardware Description languages(HDL) used by integrated
circuits(IC)designers. The other one is VHDL. Verilog can be used to describe designs at four
levels of abstraction. They are the algorithmic level,the register transfer level, the gate level and
the switch level. After a design passes basic the functional validations, it must be synthesized into
a netlist of components of a target library.The target library is the specification of the hardware
that the design is being synthesized to.Verilog constructs used in the Verilog description of
A clock is design for its verification or those for timing checks and timing specificationsare not
synthesizable. A verilog design that is to be synthesized must use language constructs that have a
clear hardware correspondence.

4.3 Using Verilog For Simulation:

The basic structure of Verilog in which all hardware components and testbenches are described is
called a module. Language constructs, in accordance to Verilog syntax and semantics form the

inside of a module. These constructs are designed to facilitate the description of hardware
components for simulation, synthesis, and specification of testbenches to specify test data and
monitor circuit responses

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 12 | P a g e

 CHAPTER – 5

5.1 Features/Objectives:

1. Clock generation
2. Initializing clock time to a particular value
3. Setting time for Alarm
4. Enabling and disabling alarm
5. Stopping the Alarm

5.2 Block Diagram:

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 13 | P a g e

Input Signals:reset,clk,H_in0,H_in1,M_in1,M_in0,LD_alarm,LD_time,STOP_al,AL_ON

Output Signals:Alarm,H_out1,H_out0,M_out1,M_out0,S_out1,S_out0

InternalSignals:tmp_1s,clk_1s,tmp_hour,tmp_minute,tmp_second,c_hour1,a_hour1,c_hour0,a_h
our0,c_min1,a_min1,c_min0,a_min0,c_sec1,a_sec1,c_sec0,a_sec0.

5.3 FLOW CHART

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 14 | P a g e

 CHAPTER – 6

6.1 Specifications :

We can give an initial time value to the system when reset signal=1 or by turning the signal LD_time=1. You
can further set the alarm time by turning LD_alarm=1.

The alarm is enabled or disabled using the input AL_ON. The alarm rings only if AL_ON is 1. STOP_al
signal is used to stop the alarm. The input clock given as input is 10Hz. We have generated a clk with time
period 1 second from this input clock and used it to increment seconds and further minutes and hours.

• reset : Active high reset pulse, to set the time to the input hour and minute (as
defined by the H_in1, H_in0, M_in1, and M_in0 inputs) and the second to 00. It
should also set the alarm value to 0.00.00, and to set the Alarm (output) low.For
normal operation, this input pin should be 0

• clk : A 10Hz input clock. This should be used to generate each real-timesecond.
H_in1 : A 2-bit input used to set the most significant hour digit of the clock (if LD_time=1),or the most
significant hour digit of the alarm (if LD_alarm=1). Valid values are 0 to 2.

• H_in0 : A 4-bit input used to set the least significant hour digit of the clock (iF LD_time=1) or the least
significant hour digit of the alarm (if LD_alarm=1). Valid values are 0 to 9.

• M_in1 : A 4-bit input used to set the most significant minute digit of the clock (if LD_time=1),or the most
significant minute digit of the alarm (if LD_alarm=1). Valid values are 0 to 5.

• M_in0 : A 4-bit input used to set the least significant minute digit of the clock (if LD_time=1),or the least
significant minute digit of the alarm (if LD_alarm=1). Valid values are 0 to 9.

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 15 | P a g e

LD_time : If LD_time=1, the time should be set to the values on the inputs H_in1, H_in0, M_in1, and
M_in0. The second time should be set to 0.If LD_time=0, the clock should act normally (i.e. second should
be incremented every 10 clock
Cycles).

• LD_alarm : If LD_alarm=1, the alarm time should be set to the values on the inputs H_in1, H_in0, M_in1,
and M_in0.If LD_alarm=0, the clock should act normally.

• STOP_al : If the Alarm (output) is high, then STOP_al=1 will bring the output back low.

• AL_ON : If high, the alarm is ON (and Alarm will go high if the alarm time equals the real time). I f low
the the alarm function is OFF.

• Alarm : This will go high if the alarm time equals the current time, and AL_ON is high. This will remain
high, until STOP_al goes high, which will bring Alarm back low.

• clk_1s : 1-s clock

• tmp_1s : count for creating 1-s clock tmp_hour, tmp_minute, tmp_second : counter for clock hour, minute
And second.

• c_hour1,a_hour1 : The most significant hour digit of the temp clock and alarm.

• c_hour0,a_hour0 : The least significant hour digit of the temp clock and alarm.

• c_min1,a_min1 : The most significant minute digit of the temp clock and alarm.

• c_min0,a_min0 : The least significant minute digit of the temp clock and alarm.

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 16 | P a g e

 CHAPTER - 7

7.1 Code:

module Aclock(
input reset,
input clk,
input [1:0] H_in1,
input [3:0] H_in0,
input [3:0] M_in1,
input [3:0] M_in0,
input LD_time,
input LD_alarm,
input STOP_al,
input AL_ON,
output reg Alarm,
output [1:0] H_out1,
output [3:0] H_out0,
output [3:0] M_out1,
output [3:0] M_out0,
output [3:0] S_out1,
output [3:0] S_out0);
reg clk_1s;
reg [3:0] tmp_1s;
reg [5:0] tmp_hour, tmp_minute, tmp_second;
reg [1:0] c_hour1,a_hour1;
reg [3:0] c_hour0,a_hour0;
reg [3:0] c_min1,a_min1;
reg [3:0] c_min0,a_min0;
reg [3:0] c_sec1,a_sec1;
reg [3:0] c_sec0,a_sec0;
function [3:0] mod_10;
input [5:0] number;
begin
mod_10 = (number >=50) ? 5 : ((number >= 40)? 4 :((number >= 30)? 3 :((number >= 20)? 2 :
((number >= 10)? 1 :0))));
end

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 17 | P a g e

endfunction
always @(posedge clk_1s or posedge reset )
begin
if(reset) begin
a_hour1 <= 2'b00;
a_hour0 <= 4'b0000;
a_min1 <= 4'b0000;
a_min0 <= 4'b0000;
a_sec1 <= 4'b0000;
a_sec0 <= 4'b0000;
tmp_hour <= H_in1*10 + H_in0;
tmp_minute <= M_in1*10 + M_in0;
tmp_second <= 0;
endelse begin
if(LD_alarm) begin
a_hour1 <= H_in1;
a_hour0 <= H_in0;
a_min1 <= M_in1;
a_min0 <= M_in0;
a_sec1 <= 4'b0000;
a_sec0 <= 4'b0000;
end
if(LD_time) begin
tmp_hour <= H_in1*10 + H_in0;
tmp_minute <= M_in1*10 + M_in0;
tmp_second <= 0;
end
else begin
tmp_second <= tmp_second + 1;
if(tmp_second >=59) begin
tmp_minute <= tmp_minute + 1;
tmp_second <= 0;
if(tmp_minute >=59) begin
tmp_minute <= 0;
tmp_hour <= tmp_hour + 1;
if(tmp_hour >= 24) begin
tmp_hour <= 0;
end
RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 18 | P a g e
end
end
end
end
always @(posedge clk or posedge reset)
begin
if(reset)
begin
tmp_1s <= 0;
clk_1s <= 0;
end
else begin
tmp_1s <= tmp_1s + 1;
if(tmp_1s <= 5)
clk_1s <= 0;
else if (tmp_1s >= 10) begin
clk_1s <= 1;
tmp_1s <= 1;
end
else
clk_1s <= 1;
end
endalways @(*) begin
if(tmp_hour>=20) begin
c_hour1 = 2;
end
else begin
if(tmp_hour >=10)
c_hour1 = 1;
else
c_hour1 = 0;
end
c_hour0 = tmp_hour - c_hour1*10;
c_min1 = mod_10(tmp_minute);
c_min0 = tmp_minute - c_min1*10;
c_sec1 = mod_10(tmp_second);
c_sec0

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 19 | P a g e

end
always @(posedge clk_1s or posedge reset)
begin
if(reset)
Alarm <=0;
else begin
if({a_hour1,a_hour0,a_min1,a_min0}=={c_hour1,c_hour0,c_min1,c_min0})
begin
if(AL_ON) Alarm <= 1;
end
if(STOP_al) Alarm <=0;
end
end
assign H_out1 = c_hour1;
assign H_out0 = c_hour0;
assign M_out1 = c_min1;
assign M_out0 = c_min0;
assign S_out1 = c_sec1;
assign S_out0 = c_sec0;
endmodule

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 20 | P a g e

 CHAPTER – 8

8.1 Testbench:

module Testbench;
reg reset;
reg clk;
reg [1:0] H_in1;
reg [3:0] H_in0;
reg [3:0] M_in1;
reg [3:0] M_in0;
reg LD_time;
reg LD_alarm;
reg STOP_al;
reg AL_ON;
// Outputs
wire Alarm;
wire [1:0] H_out1;
wire [3:0] H_out0;
wire [3:0] M_out1;
wire [3:0] M_out0;
wire [3:0] S_out1;
wire [3:0] S_out0;
Aclock uut (
.reset(reset),
.clk(clk),
.H_in1(H_in1),
.H_in0(H_in0),
.M_in1(M_in1),
.M_in0(M_in0),
.LD_time(LD_time),
.LD_alarm(LD_alarm),
.STOP_al(STOP_al),
.AL_ON(AL_ON),
.Alarm(Alarm),

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 21 | P a g e

H_out1(H_out1),
.H_out0(H_out0),
.M_out1(M_out1),
.M_out0(M_out0),
.S_out1(S_out1),
.S_out0(S_out0)
);
initial begin
clk = 0;
forever #50 clk = ~clk;
endinitial begin
// Initialize Inputs
reset = 1;
H_in1 = 1;
H_in0 = 0;
M_in1 = 1;
M_in0 = 9;
LD_time = 0;
LD_alarm = 1;
STOP_al = 0;
AL_ON = 0;
#40;
reset = 0;
H_in1 = 1;
H_in0 = 0;
M_in1 = 2;
M_in0 = 0;
LD_time = 0;
LD_alarm = 1;
STOP_al = 0;
AL_ON = 1;
#40;
reset = 0;
H_in1 = 1;
H_in0 = 0;
M_in1 = 2;
M_in0 = 0;

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 22 | P a g e

LD_time = 0;
LD_alarm = 0;
STOP_al = 0;
AL_ON = 1;
wait(Alarm);
#10;
#10;
#10;
#10;
#10;
#10;
STOP_al = 1;
end
endmodule

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 23 | P a g e

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 24 | P a g e
 CHAPTER – 9

9.1 Output Waveform:

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 25 | P a g e

 CHAPTER - 10

10.1 Proposed Technoloy:

● Proposed method could include advanced features like customizable alarm tones.
● smart home integration.
● even bio-sensors to walk you up at the optimalsleep stage.
● Innovtion in technology could lead to more personalized and efficient alarm clock
solutions.

1Hz pulse from 555 timer drives the first counter from the right, so it counts up each second, acts as a divide
by 10 counter. After counting 9, this counter resets itself to 0 and sends a carry over to the next counters clock
input, so the next counter increases one count. Then, after the second counter reaches 5 and is about to count
to 6, it resets itself to 0 and sends a clock pulse to the third counter. Thus, it acts as a divide by 6 counter.
Third counter again works as a divide by 10 counter and the fourth counter acts as a divide by 6 counter in the
previous way. So we get counts for seconds and minutes. The fifth counter sends a carry over clock pulse to
the sixth counter after counting 9, then resets itself to 0.

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 26 | P a g e

10.2 Advantages of Alarm Clock:

• Alarm clocks can also be helpful for keeping sleep schedules regular.
• Waking Up around the same time each day is beneficial for our internal biological clocks.
• Using an alarm clock can help keep our schedule consistent and normalize our sleep patterns.
• Some alarm clocks have brightly-lit faces and while good for seeing the time .
● Alarm clocks can help normalize sleep schedules, ensure punctuality, and provide peace of mind about
waking up on time.
● However, there are potential downsides to alarm clocks, including sleep anxiety, stress from sudden
wake-ups, and disruption of natural circadian rhythms.
● Unlike digital devices such as smartphones and computers, which are distracting with their notifications
and alerts, a wall clock provides a constant visual reminder of the time, helping you stay on track and
manage your schedule more effectively.
●
It can help improve your sleep quality, eliminate distractions, save your phone's battery life, provide a less
stressful wake-up experience, and be more reliable.
●
alarm clock may help you remember to get up in time for breakfast and supper, as well as to remind you of
key activities that day.
●
clocks can keep time accurately for long periods, barring power cuts; over months they are more accurate
than a typical quartz clock.

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 27 | P a g e

10.3 Disadvantages of Alarm Clock

• Waking up abruptly can cause higher blood pressure and heart rate.
• Alarm clocks provoke stress to the heart.
• Alarm can certainly cause hearing loss.
•Multiple alarms repeatedly cause the brain to start waking up and then settle again,only to be disturbed five
minutes later.
•The repetitive awekenings disrupt sleep quality.
•Sleepers can become accustomed to the sound of their alarm clock if it has been used for a
period of time,making it less effective.

10.4 Conclusion:

We implemented Clock Generator with Alarm using verilog.When the alarm time matches with the real clock
time ,then the alarm will be raised.Otherwise the alarm does not ring and the clock will be operated normally.
The clock is incremented by each one second(1second=10 input clock cycles).The Alarm is raised then it needs
to be turned off after some time.This way we set alarms because they are very essential in our daily life.

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 28 | P a g e

10.5 Future Scope:

• Scientific studies on sleep having shown that sleep stage at awakening is an important factor in amplifying
sleep inertia.The alarm clocks use sensing technologies such as EEG electrodes and accelerometers to wake
people from sleep.Dawn simulators are another technology meant to mediate these effects.

• Sleepers can become accustomed to the sound of their alarm clock if it has been used for a period of time,
making it less effective.Due to progressive alarm clocks complex waking procedure,they can deter this adapt
to more stimuli than just a simple sound alert.
●
The Verilog code can be used to design an IC for digital clock. This will make the clock circuit even smaller
● Analog clock mode can be added Display can be upgraded to more marketable formats
● Current date display can be added
● The IC implementation can be added to other devices
● Device screen saver effects can be added
● Daylight saving time may be added along with the incorporation of automatic synchronization by a radio
time signal so that available clocks don’t need to be readjusted Proteus circuit can be improved by making
it smaller and more efficient for practical implementation
●
Clock font customization can be added
●
Different sound effects for the alarm can be added
●
Other visualization effects can be added

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 29 | P a g e

Light Based Alarm Clocks:

The deaf and hard of hearing are often unable to perceive auditory alarms when
alseep.They may use alarms with a light in their bedroom that slowly rises in order to mimic the
rising sun.It actually triggers hormones in your body to slowly wake you up.
Alarms Clocks in the future will wake you up with a Scent:

Sleepion:It is one up-and-coming japanese product.Sleepions uses aromatherapy oils to create

scents,lights and sounds to promote sleep.The lavender oil increases the percentage of deep sleep
time.

10.6 Contributions:

Khondker Shihabul Hoque (ID 1606067) :

Implemented the Verilog HDL code and algorithm of digital alarm clock
with stopwatch and simulated the timing diagrams.

Uddrity Mansur (ID 1606069) :

Implemented the 1Hz clock pulse circuit, Main Clock Circuit
and Stopwatch Circuit in Proteus and simulated them.

Md Ashraful Islam (ID 1606085) :

Implemented the alarm input mechanism, comparator circuit and
buzzer to ring the alarm.

RGUKT RK VALLEY, Dept. of E.C.E, Idupulapaya, Kadapa 30 | P a g e