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Miniproject 2

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0% found this document useful (0 votes)
10 views24 pages

Miniproject 2

Uploaded by

Ammu Honey
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CLOCK GENERATOR WITH ALARM

USING XILINX

PRESENTED BY:
B Sai Deepthi - N190115
G Sharon - R190834
N Mounika - R190881
N Gayathri - R190047
OBJECTIVES:

• Introduction

Exsisting and proposed methods

Features
• Block Diagram
• Flow Chart
• Code and Test bench
• Output Waveforms
• Conclusion

Future Scope
INTRODUCTION:
An alarm clock is a clock that is design to alert an individual
or group of individual at a specified time. The primary
function of this clock is to awaken people from there night’s
sleep or short naps.We are generating a clock with 7 output
signals including alarm signal, hour,minute,and second. The
clock generated is in a 24 hour format .Alarm have been in
use for centuries because they slove a real problems-
ensuring wake up on time.
The First alarm clock was invented in 1787 by Levi
Hulchins in the USA.But it rings at 4 o’clock in the
morning.The first alarm with mechanical and
adjustable time was palented in 1847 by French
Antoine Redier.The first radio alarm clock was
invented by James F.Reynolds,in the 1940’s and
another design was also invented by Paul L.Schroth.
Alarm are used in mobile phone,watches and
computers.Many alarm clocks have radio receivers
that can be set to start playing at specified time
and are known has clock radios.Some
alarm clock can set multiple alarm

5
EXISTING TECHNOLOGIES:

Existing method for clock generator with alarm’s


typically involve setting a specific time for the alarm
to ring,often using buttons or a digital interface.
PROPOSED TECHNOLOGIES:

Proposed method could include advanced features like


customizable alarm tones,smart home integration,or
even bio-sensors to walk you up at the optimal
sleepstage.Innovtion in technology could lead to more
personalized and efficient alarm clock solutions.
FEATURES:
1. Clock generation

2. Initializing clock time to a particular value

3. Setting time for Alarm

4. Enabling and disabling alarm

5. Stopping the Alarm


BLOCK DIAGRAM:
Input Signals:reset,clk,H_in0,H_in1,M_in1,M_in0,LD_alarm,LD_time,
STOP_al,AL_ON
Output Signals:Alarm,H_out1,H_out0,M_out1,M_out0,S_out1,S_out0
Internal Signals:tmp_1s,clk_1s,tmp_hour,tmp_minute,tmp_second,
c_hour1,a_hour1,c_hour0,a_hour0,c_min1,a_min1,c_min0,a_min0,c_sec
1,a_sec1,c_sec0,a_sec0.
FLOW CHART:

10
Verilog Code:
module Aclock(
input reset,
input clk,
input [1:0] H_in1,
input [3:0] H_in0,
input [3:0] M_in1,
input [3:0] M_in0,
input LD_time,
input LD_alarm,
input STOP_al,
input AL_ON,
output reg Alarm,
output [1:0] H_out1,
output [3:0] H_out0,
output [3:0] M_out1,
output [3:0] M_out0,
output [3:0] S_out1,
output [3:0] S_out0);
reg clk_1s;
reg [3:0] tmp_1s;
reg [5:0] tmp_hour, tmp_minute, tmp_second;
reg [1:0] c_hour1,a_hour1;
reg [3:0] c_hour0,a_hour0;
reg [3:0] c_min1,a_min1;
reg [3:0] c_min0,a_min0;
reg [3:0] c_sec1,a_sec1;
reg [3:0] c_sec0,a_sec0;
function [3:0] mod_10;
input [5:0] number;
begin
mod_10 = (number >=50) ? 5 : ((number >= 40)? 4 :((number >= 30)? 3 :((number >=
20)? 2 :((number >= 10)? 1 :0))));
end
endfunction
always @(posedge clk_1s or posedge reset )
begin
if(reset) begin
a_hour1 <= 2'b00;
a_hour0 <= 4'b0000;
a_min1 <= 4'b0000;
a_min0 <= 4'b0000;
a_sec1 <= 4'b0000;
a_sec0 <= 4'b0000;
tmp_hour <= H_in1*10 + H_in0;
tmp_minute <= M_in1*10 + M_in0;
tmp_second <= 0;
end
else begin
if(LD_alarm) begin
a_hour1 <= H_in1;
a_hour0 <= H_in0;
a_min1 <= M_in1;
a_min0 <= M_in0;
a_sec1 <= 4'b0000;
a_sec0 <= 4'b0000;
end
if(LD_time) begin
tmp_hour <= H_in1*10 + H_in0;
tmp_minute <= M_in1*10 + M_in0;
tmp_second <= 0;
end
else begin
tmp_second <= tmp_second + 1;
if(tmp_second >=59) begin
tmp_minute <= tmp_minute + 1;
tmp_second <= 0;
if(tmp_minute >=59) begin
tmp_minute <= 0;
tmp_hour <= tmp_hour + 1;
if(tmp_hour >= 24) begin
tmp_hour <= 0;
end
end
end
end
end
end
always @(posedge clk or posedge reset)
begin
if(reset)
begin
tmp_1s <= 0;
clk_1s <= 0;
end
else begin
tmp_1s <= tmp_1s + 1;
always @(posedge clk_1s or posedge reset)
begin
if(reset)
Alarm <=0;
else begin
if({a_hour1,a_hour0,a_min1,a_min0}=={c_hour1,c_hour0,c_min1,c_min0})
begin
if(AL_ON) Alarm <= 1;
end
if(STOP_al) Alarm <=0;

end
end

assign H_out1 = c_hour1;


assign H_out0 = c_hour0;
assign M_out1 = c_min1;
assign M_out0 = c_min0;
assign S_out1 = c_sec1;
assign S_out0 = c_sec0;

endmodule
Testbench:
module Testbench;
reg reset;
reg clk;
reg [1:0] H_in1;
reg [3:0] H_in0;
reg [3:0] M_in1;
reg [3:0] M_in0;
reg LD_time;
reg LD_alarm;
reg STOP_al;
reg AL_ON;
// Outputs
wire Alarm;
wire [1:0] H_out1;
wire [3:0] H_out0;
wire [3:0] M_out1;
wire [3:0] M_out0;
wire [3:0] S_out1;
wire [3:0] S_out0;

Aclock uut (
.reset(reset),
.clk(clk),
.H_in1(H_in1),
.H_in0(H_in0),
.M_in1(M_in1),
.M_in0(M_in0),
.LD_time(LD_time),
.LD_alarm(LD_alarm),
.STOP_al(STOP_al),
.AL_ON(AL_ON),
.Alarm(Alarm),
.H_out1(H_out1),
.H_out0(H_out0),
.M_out1(M_out1),
.M_out0(M_out0),
.S_out1(S_out1),
.S_out0(S_out0)
);
initial begin
clk = 0;
forever #50 clk = ~clk;
end
initial begin
// Initialize Inputs
reset = 1;
H_in1 = 1;
H_in0 = 0;
M_in1 = 1;
M_in0 = 9;
LD_time = 0;
LD_alarm = 1;
STOP_al = 0;
AL_ON = 0;
#40;
reset = 0;
H_in1 = 1;
H_in0 = 0;
M_in1 = 2;
M_in0 = 0;
LD_time = 0;
LD_alarm = 1;
STOP_al = 0;
AL_ON = 1;
#40;
reset = 0;
H_in1 = 1;
H_in0 = 0;
M_in1 = 2;
M_in0 = 0;
LD_time = 0;
LD_alarm = 0;
STOP_al = 0;
AL_ON = 1;
wait(Alarm);
#10;
#10;
#10;
#10;
#10;
#10;
STOP_al = 1;
end
endmodule
OUTPUT WAVEFORMS:
Advantages of Alarm Clock:


Alarm clocks can also be helpful for keeping
sleep schedules regular.
• Waking Up around the same time each day is
beneficial for our internal biological clocks.

Using an alarm clock can help keep our schedule
consistent and normalize our sleep
Patterns.

Some alarm clocks have brightly-lit faces and
while good for seeing the time .
Disadvantages of Alarm Clock:

• Waking up abruptly can cause higher blood


pressure and heart rate.
• Alarm clocks provoke stress to the heart.
• Alarm can certainly cause hearing loss.

Multiple alarms repeatedly cause the brain to start
waking up and then settle again,only tobe
disturbed five minutes later.

The repetitive awekenings disrupt sleep quality.

Sleepers can become accustomed to the sound of
their alarm clock if it has been used for a Period of
time,making it less effective.
Conclusion:
We implemented Clock Generator with Alarm using
verilog.When the alarm time matches with the real clock
time ,then the alarm will be raised.Otherwise the alarm
does not ring and the clock will be operated normally.The
clock is incremented by each one second(1second=10
input clock cycles).The Alarm is raised then it needs to be
turned off after some time.This way we set alarms
because they are very essential in our daily life.
Future Scope:

• Scientific studies on sleep having shown that sleep


stage at awakening is an important factor in amplifying
sleep inertia.The alarm clocks use sensing technologies
such as EEG electrodes and accelerometers to wake
people from sleep.Dawn simulators are another
technology meant to mediate these effects.
• Sleepers can become accustomed to the sound of their
alarm clock if it has been used for a period of
time,making it less effective.Due to
progressive alarm clocks complex
wakingprocedure,they can deter this
adapt to more stimuli than just a simple
sound alert.
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