EX1
library ieee;
use ieee.std_logic_1164.all;
entity project11 is
port(a,b,c:in bit;x:out bit);
end project11;
architecture XOR_GATE of project11 is
begin
x<=((not a) and b and c) or (a and (not b) and c) or (a and b and (not c)) or (a and b and c);
end XOR_GATE;
EX2
library ieee;
use ieee.std_logic_1164.all;
entity Exp2 is
port (a : in std_logic_vector (2 downto 0 );
o :out std_logic_vector (1 downto 0 ));
end Exp2
Architecture test Of Exp2 is
begin with a select
o<= "00" when "000",
"11" when "001",
"11" when "010",
"01" when "011",
"10" when "100",
"00" when "101",
"00" when "110",
"11" when others;
end test;
BART 2
library ieee;
use ieee.std_logic_1164.all;
entity EXX2 is
port (a:in std_logic_vector(2 downto 0);
y:out std_logic_vector(1 downto 0));
end EXX2;
architecture full of EXX2 is
begin
with a select
y<="00" when "000",
"11" when "001",
"11" when "010",
"01" when "011",
"10" when "100",
"00" when "101",
"00" when "110",
"11" when others;
end full;
EX3 A
library ieee;
use ieee.std_logic_1164.all;
entity EX3 is
port (a:in std_logic_vector(2 downto 0);
z:out std_logic_vector(7 downto 0));
end EX3;
architecture decoder of EX3 is
begin
process (a)
begin
if a="000" then z<="00000001";
elsif a="001" then z<="00000010";
elsif a="010" then z<="00000100";
elsif a="011" then z<="00001000";
elsif a="100" then z<="00010000";
elsif a="101" then z<="00100000";
elsif a="110" then z<="01000000";
elsif a="111" then z<="10000000";
end if ;
end process;
end decoder;
EX3 B
library ieee;
use ieee.std_logic_1164.all;
entity EXX3 is
port (a:in std_logic_vector(2 downto 0);
z:out std_logic_vector(7 downto 0));
end EXx3;
architecture dec of EXX3 is
begin
process (a)
begin
case a is
when "000"=>z<="00000001";
when "001"=>z<="00000010";
when "010"=>z<="00000100";
when "011"=>z<="00001000";
when "100"=>z<="00010000";
when "101"=>z<="00100000";
when "110"=>z<="01000000";
when others =>z<="10000000";
end case;
end process;
end dec;
EX4
library ieee;
use ieee.std_logic_1164.all;
entity EX4 is
port(A,B,D:in std_logic;D0,D1,D2,D3:out std_logic);
end EX4;
architecture de_MUX of EX4 is
component INV
port (x:in std_logic;z:out std_logic);
end component;
component AND3GATE
port (x,y,z:in std_logic;p:out std_logic);
end component;
signal Abar,Bbar:std_logic;
begin
A1:INV port map(A,Abar);
A2:INV port map(B,Bbar);
A3:AND3GATE port map(D,Abar,Bbar,D0);
A4:AND3GATE port map(Abar,B,D,D1);
A5:AND3GATE port map(A,Bbar,D,D2);
A6:AND3GATE port map(A,B,D,D3);
end de_MUX;
library ieee;
use ieee.std_logic_1164.all;
entity INV is
port(x:in std_logic;z:out std_logic);
end INV;
architecture de_MUX of INV is
begin
z <= not x;
end de_MUX;
library ieee;
use ieee.std_logic_1164.all;
entity AND3GATE is
port(x,y,z:in std_logic;p:out std_logic);
end AND3GATE;
architecture de_MUX of AND3GATE is
begin
p <= x and y and z;
end de_MUX;
