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System Verilog 2

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21 views15 pages

System Verilog 2

Uploaded by

ansupritha935
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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verilog => HDL

-> module based testbenches


-> c language
-> extension files are saved in .v format
-> reg and wire datatypes

system verilog => HDL and HVL

-> class based testbenches


-> c++ or cpp
-> extension files are saved in .svh
-> logic(reg and wire), enum, string, struct, union

Data Types in System Verilog:

signed datatypes: can hold both positive and negative


unsigned datatypes: can hold only positive values

2-state data type : can hold only 0 or 1 values


4-state data type : can have 0,1,x,z

datatypes 2state size unsigned/signed

/4state

1. bit => 2-state = 1-bit = unsigned


2. byte => 2-state = 8-bit = signed
3. int => 2-state = 32-bit = signed
4. shortint => 2-state = 16-bit = signed
5. longint => 2-state = 64-bit = signed
6. integer => 4-state = 32-bit = signed
7. reg => 4-state = user defined = unsigned
8. wire => 4-state = user defined = unsigned
9. logic => 4-state = user defined = unsigned
10. real => 4-state = 64-bit = double datatypes
11. shortreal=> 4-state = 32-bit = floating values
12. time => 4-state = 64-bit = unsigned
13. realtime => can be used with real data type

void datatype, string, user-defined, event, enumeration datatypes

array:

collection of homogenous elements is called an array(same data type or


variables).

arrays are two type:

1.fixed size array

syntax: data_type array_name[value];

module fixed_array;
int array_1[4];(compact declaration)
//int array_1[3:0](verbose declaration)
initial begin
array_1='{0,1,2,3};
end
$display("display array_1");
foreach(array_1[i])
$display("\t array_1[%0d]=%0d", i,array_1[i]);
endmodule

memory is allocated in compile time


memory is same throught the stimulation

2.dynamic array :
sytax: data_type array_name []
methods: new[],size(),delete()

module dy_array;
int array_1[];
//int array_1[3:0](verbose declaration)
initial begin
dy_array = new[4];(1st method)

array_1='{0,1,2,3};
end
array_1.delete();(2nd method)
$display("display array_1");
foreach(array_1[i])
$display("\t array_1[%0d]=%0d", i,array_1[i]);
$display("size of the array=%0d",array_1.size());
array_1=new[8](array_1); (3rd method)
$display("size of the array after resizing=%0d",array_1.size());
endmodule

memory is allocated in run time


we can incerese and decrease the memory throught the simulation

3.associative array (unknown memory):

syntax:data_type array_name[intex_type or *];

it stores entries in sprase matrix and also memory allocated whenever we


need unless it is like a dyanamic array

Methods:
num()
delete()
exist()
fisrt()
last()
next()
prev()

4. Queue
syntax: data_type queue[$];

-> memory is allocated in run time


-> queue supports adding or removing the elements
-> It acts as FIFO or LIFO

methods:
size()
delete()
push_front()
push_back()
pop_front()
pop_back()

Types of Queue:

1) Bounded Queue - size is specified


2) Unbounded Queue - size of the queue is not specified

packed and unpacked array:

packed array:

-> dimensions are declared before identifier are called packed arrays
-> these are contigious set of bits
-> it supports single data type reg, logic, bit, enum
syntax: bit[2:0][3:0] array;

unpacked array:

-> dimensions are declared after identifier is called unpacked array


-> it may or maynot contigious set of
-> it can be of any datatype

syntax: bit array[2:0][3:0];

Procedural Statements and Flow Control

Blocking Statements:
-> In blocking the statements execute in serial/sequentially
-> it is indicated with "="
-> It will execute at current timestamp

Non-Blocking Statements:

-> It executes paralally (all the statements execute at same time)


-> It is represented with "<="
-> it will execute at end of the timestamp

Unique if:
-> the statements will execute in parallel

conditions are for run-time error:

1. More than one condition is true


2. No condition is true and it doesn't follow corresponding else (run-time error)

Task

contain time consuming elements


#5, #10 -> delay elements
task can call tasks and functions
Function
return 0
it doesnt contain time elements
It doesnt have delays
functions cannot have tasks
it is executing at 0-time simulation

Argument Passing:

1. argument pass by value => any changes in arguments will not be visible outside
of the subroutine
2. argument pass by reference => any changes in argument will be visible outside
of the subroutine
3. argument pass by name => string => it specfies words/names
4. argument pass by position =>

const keyword => any changes made in arguments in function with const keyword will
give you compiler error

1. argument pass by value:

any changes in arguments will not be visible outside of the subroutine

Ex:

function int sum(int x,y);


x=x+y;
return x+y;
endfunction

intial begin
x = 6;
y = 3;
z = sum(x,y);
end

$display("vslue of x=%0d", x);


$display("value of y=%0d",y);
$display("value of z=%0d",z);

Why class are implemented in System verilog??

1. verilog things are static in nature


2. you cannot change the values at run-time
3. in system verilog you can change the values at run-time (bcz of classes)

class:

it is a user-defined type which consists of methods(functions and tasks) and


properties
values can be changed at run-time in classes
it contains handles to access variables

class <class_name>

//functionality
endclass

This keyword:

=> it refers to current class properties


=> inorder to avoid conflit between class properties and properties which are
defined in methods

class bindu;
int a;
int b;

funtion void(int a,b);


this.a = a;
this.b = b;

endfunction
endclass

Static Property and Static Methods:

Static: The keyword static is assigned to property or method

It is variable which is shared across multiple instances

static property:

syntax:

static <data_type> <property_name>;

static method:

static tasks/function <method_name>;

class packet;

packet
pkt1
pkt2

Class Assignment:

Same memory location it will be allocated and which can be accessed by two
different handles. If any handle will change class properties,
it will reflect the same changes when your accessing by another handle.

EX:
class packet;

bit[31:0] data;
int start_addr; = 2
int end_addr; = 5

endclass
pkt1;
pkt2;

pkt2 = pkt1
pkt1.data

Shallow Copy:

objects will not be copied, only there handles are copied i.e., properties of class
are copied, unlike the objects

Limitation of shallow copy:

if your having an object then the handles as well object will share same memory

Deep Copy:

Deep copy will copy all the class members and its nested class
in deep both objects and handles are copied
to perform a deep copy, we need a method called copy
By adding copy method, new object will be created and then all class properties
will be copied to a new handle

Inheritance:

Inheritance is one of the OOP concept


It allows the user to create classes based on the existing classes.
Here we use extends keyword to derive the child class
Inheriting base/parent class to the child class

Example:

class parent; //parent class or base class

//properties
endclass

class child extends parent;


//properties of child class

endclass

module tb;
child = new();

endmodule

Polymorphism:

Polymorphism is nothing but many forms i.e.,


Here parent class can invoke child class properties and methods which has same name
by using virtual keyword

-> As we know, the derived class object can override methods of its base class.
Similarly, the base class object can also override the method of one of the child
classes.
-> It means a base class method has different forms based on derived class
implementation.
-> To use many forms of the method, the virtual keyword must be used in the method
definition.

polymorphism = virtual methods + Inheritance

If any method is declared as virtual in the parent class then by default same
method works as virtual in child class

1. parent class method should be virtual


2. p = c is possible, c = p is not possible

super keyword:

if you want to access parent class properties into child class


parent class properties are overridden by child class by using super keyword
within the new function you need to write super.new

Casting:

It is the process of coverting one data type to other data type


The method of data type conversion is nothing but casting

1. static casting => these are not applicable to OOP, bcz these are not
dynamic in nature
=> static is nothing but the data type will be fixed
=> value, variable, expression

Example:

module prateek;
real r;
int i;

initial begin
r = (2*3.5);
i = int'(3*5);
$display("r = %0f, i =%0d", r,i);
end

endmodule

2. dynamic casting =>

=> it is possible to cast parent class into child class


=> dynamic casting can be checked during runtime, will not be changed during
compile time
=> $cast(destination = c, source = p)

syntax : parent_class = class_class; //possible and it is legal


child_class = parent_class; //not possible, it is illegal

$cast(child_class,parent_class);
Data Hiding and Encapsulation:

Datahiding: we can limit the accessibility of the users


Encapsulation: Hiding of the data within the class and making it available only
through the methods

By default all the class members are public, by using data hiding concept we can
make the class members as private

1. Local : it cannot access local properties inside the child class as well as
outside the class
2. Protected / Private : it can access in child class but outside of the class is
not possible(it will lead to compilation error)

Abstract class:

A class declared with keyword virtual then we call it is abstract class, it doesn't
let anyone to use this class, except its extended/derived class

abstract class cannot be instantiate, it can only be inherited


If you instantiate abstract class, then it will throw fatal error i.e., (parent
class and child class methods must have same names)

syntax:

virtual class<class_name>
//

endclass

Virtual Methods:

Methods declared with keyword virtual are reffered to as virtual methods

A function which is declared with a virtual keyword before the function is called
as virtual function
A task which is declared with a virtual keyword before the task is called as
virtual task

syntax:

virtual function function_name;

// function definition

endfuntion

or
virtual task task_name;
//task definition

endtask

Scope Resolution Operator:

This is indicated by "::"


It is used to refer an identifier within the scope of the class
Accessing methods from outside the class by using the extern keyword
A static member(module) of the class is accessed outside the class by using SRO ::
It can be used to access members of parent class from within child class

Syntax:

<class_name>::<class member>

Extern Method:

Extern method will provide a facility for class methods to define them outside the
class body
If the method definition is lenghty i.e., lines of code inside a method are more),
this extern method will provide you better releability
this extern keyword is used for method declaration and a class name with scope
resoultion operator is used for method definition

1. method defintion and declaration should have the same number of argument lines,
data types, argument names
2. for the extern funtion return type should be same if you are using

Typedef class:

It is a user_defined class
It is used to allow forward declaration of the class
in some cases, the class needs to be instantiated before the class declaration

syntax:

typedef class class_name;

Randomization:

$random is basically used in verilog => randomizing the object $random is not
sufficient, it is limited to 32-bit size

It is generating random values for variables by using rand and randc keywords.

keywords
1. rand => will give you random values for the variables values will repeat (i.e.,
2567132)
2. randc => will give you random values in random-cyclic, values will not
repeat(i.e., 2567135)

syntax:

rand bit[3:0] a;
randc bit[3:0] a;

Need for randomization:

=> for complex designs there are high chances of getting bugs in the design, to
verify dut we need to provide some stimulus by verification engineer,
there can be multiple cross comibinations of variables in real system, this is
not possible practically to write directed cases to verify every possible
combinatin,
that is the reason we are using randomization

Disable randomization:
=> the variable is declared withoud rand randc will not get random values on
randomization
=> to disable the randomization of a variable by using the method called
(rand_mode)

rand_mode method:

rand_mode(1) means randomization is enabled


rand_mode(0) means randomization is disabled

syntax:

<object_handle>,<variable_name>.rand_mode(enable = 1/disable = 0)

randomization methods:

these pre_randomize() and post_randomize() functions which are called before and
after the randomize call

1. pre_randomize => function call used to set pre-conditions before the object
randomization
2. post_randomize => function call used to check and perform post-conditions after
the object randomization

Constraint:

It is used to control the values which are getting randomized, this can be achieved
by constraints.
For ex: random variable, you can get specific value, and ranges by using
randomization
constraints blocks are enclosed within {}

Syntax:

contraint<constraint_block_name> {<condition/expression>; <condition/expression>;}

Constraint inside:

=> By using inside operator we can achieve random values for a specified
value/range
=> values within the inside block can be variable, constant, range
=> inside block is written followed by {}

constraint var1{a inside {2, [10:20]};}

Weighted Distribution Constraint:

In this we are using operator specificied by := and :/


value with more weight will be repeated number of times for a random variable

Syntax:

value := weight (or) value :/ weight

Ex:
:= the operator indicates specified weight of the value/item, if it is in range
then it specifies weight to every value in the range

a dist{2 := 6, 12 := 8, 15 := 7, 6: =7};

a == 2, weight 6
a == 12, weight 8
a == 15, weight 7
a == 6, weight 7

:/ the operator indicates specified weight to the value/item, if it is range then


it is specified weight/n to every value in the range, n is number of values in the
range

a dist{2 :/ 6, [14:16] :/ 7, }

a == 2, weight 6
a == 14, weight 7/3
a == 15, weight 7/3
a == 16, weight 7/3

Implication Constraint:

It is denoted by "->" symbol


this is used between conditional relations between two variables

syntax:

expression -> constraint

Disable Constraints:

constraints can be disabled using constraint_mode method call.

=> constraint_mode(1) - constraint block is enabled


=> constraint_mode(0) - constraint block is disabled

syntax:

<object_handle>.<constraint_block_name>.constraint_mode(enable = 1/diable = 0)

Static Constraints:

=> static constraints are similar to static class properties.


=> by defining static keyword before the constraint it makes the constraint block
static in nature
=> static constraint is shared across class instances

syntax:

static constraint constraint_name {... ;}

Inline Constraint:

Constraints will be written inside the class, inline constraints allow the user to
have an extra constraint to existing constraints will be written outside d the
class
i.e., by using "with" in module
syntax:

object.randomize() with {....};

Soft Constraints:

Constraints which are declared by using soft keyword is called soft constraints.
Any conflict which has arrived between class and inline constraints leads to
randomization faiure, It can say that it is not possible to override the class
constraint by inline constraint.
if you want to override then it is done only by soft keyword

syntax:

constraint_name {soft variable {condition}; }

Unique constraints:

=> Constraint which is defined by keyword unique are called as unique constraints.
=> when you are doing randomization, you need to get unique values for a set of
variables or elements by using unique constraints
=> generate unique elements in an array(fixed, dynamic, associative, queue)

Bidirectional constraints:

constraints are solved bidirectionally, which means constraints on all random


variables will be solved parallel

ex:

constraint_name {if(a==0) b==1;


else b==0;}

Solve Constraint:

this is like constraint property, where slove before is used inside the constraint
block to specify the order of constraint solving

Inter Process Communication:

This IPC is way of communication between two processes or testbench components.


SV provides three mechanisms for communication

1. Semaphores
2. Mailbox
3. Events

Semaphore:

=> It is a built-in class and used to access shared resources and for
synchronization.
=> It is like a bucket with number of keys, first person should procure a key from
the bucket, all the other persons should wait until a key is retured.

Syntax:

semaphore semphore_name;
Methods:

1. new(); //creating a semaphore for no. of keys


2. get(); //get the keys from bucket
3. put(); //return the keys to bucket
4. try_get(); //to get the keys and it is in blocking

get():

It is blocking method
get method is used to get keys from a semaphore
semaphore_name.get(no.of keys) -> semaphore_name.get();

put():

It is also a blocking method


to put the keys or return keys to semaphore
semaphore_name.put(no. of keys) -> semaphore_name.put();

try_get();

It is also a non-blocking method


semaphore_name.try_get(no. of keys) -> semaphore_name.try_get();

Mailbox:

It is a communication mechanism between two processes to exchange the information.


you can send and retrieve data.

In SV, we are using this mailbox inbetween generator and driver.

syntax:

mailbox mailbox_name;

Methods:

1. numw(); //no. of messages in mailbox


2. new(bound); //bounded no. of messages
3. put(); //blocking //to put the message in mailbox. if the
mailbox is full, need to wait(block) until you have space
4. get(); //blocking //it removes a message from mailbox. if
your mailbox is empty then the process blocks until a message is placed in mailbox
5. peek(); //non-blocking //copies a message from mailbox. it does
not remove the message from the mailbox
6. try_get(); //non-blocking //it removes a message from mailbox. it
unblocks the mailbox if mailbox is empty
7. try_peek(); //non-blocking //copies a message from mailbox without
blocking

Types of mailbox:

1. Generic mailbox(type-less)

=> single mailbox which can send and receive data of type
=> syntax: mailbox mailbox_name;
2. Parameterized mailbox(with particular type)

=> It is used to transfer data of particular type


=> syntax: mailbox#(type) mailbox_name;

BOUNDED and UNBOUNDED Mailbox:

Bounded mailbox:

=> If the size of the mailbox is specific then it is bounded


=> when mailbox is full, it cannot put the data into mailbox or get the data from
mailbox

Unbounded mailbox:

=> The is not specified. it has unlimited size

Events:

An event is static object handle to synchronize between two or more processess.


If one process is triggering an event, then another event should wait for the
event.

events can be triggered by using

" -> " operator or ->> " operator "


" -> " event to be triggered and other event should wait using " @ " wait operator
or " wait() " construct

1. Event triggering:

-> operator:

this is used to trigger an named event, by triggering this event it will unblocks
all processes which are currently waiting on that event

->> operator:

Non-blocking events can be triggered

2. waiting for event trigger:

@ operator:
to wait an event to be triggered by using @

if trigger an event (->) and wait for an event (@) these both are happened at same
time, race around condition will occur, this can be avoided by triggered property

wait operator:

if event triggering and waiting for event trigger with @ operator happens at same
time, then it will not detect proper event

wait(event_name.triggered);

wait_order():

it is a construct which is blocking the process until all specified events are
triggered
if the event is trigger without order will not unblock the process

wait_order(a,b,c); //followed from left to right

blocks the process until events a, b, c trigeer in order a->b->c.


If the event is trigger out of order then, a run-time error is generated

wait_order(a, b, c);
else
$display("events are out of order");

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