Topics for Seminar Talks

Digital System Integration and Programming

Barbara Gigerl, Stefan Mangard, Stefan Steinegger

October 6th, 2020
IAIK – Graz University of Technology
 Important information www.tugraz.at

• Step 1: Find a group

• Step 2: Find a seminar topic
• https://cloud.tugraz.at/index.php/s/jcPr8LJiEjbNJsw
• Deadline: 13.10., 23:59!

1 — IAIK – Graz University of Technology

 Important information www.tugraz.at

• Step 1: Find a group

• Step 2: Find a seminar topic
• https://cloud.tugraz.at/index.php/s/jcPr8LJiEjbNJsw
• Deadline: 13.10., 23:59!
• Select a topic from the catalogue or send us your ideas!

1 — IAIK – Graz University of Technology

 Important information www.tugraz.at

• Step 1: Find a group

• Step 2: Find a seminar topic
• https://cloud.tugraz.at/index.php/s/jcPr8LJiEjbNJsw
• Deadline: 13.10., 23:59!
• Select a topic from the catalogue or send us your ideas!
• Length of presentation: 20 min + 10 min if you are alone, 40 min + 10 min if you
are in a team of 2
• Please submit your slides until Monday evening - we will review your presentation
and send you feedback.

1 — IAIK – Graz University of Technology

 Topic #1 www.tugraz.at

Topic #1: Architecture of FPGAs (2)

FPGAs consist of configurable logic blocks (CLBs), connected by programmable
interconnects. Depending on the manufacturer, these CLBs can further be divided into
logic blocks.

• What is a CLB and what role do interconnects play?

• How and when are CLBs configured?
• What are IOBs (Input Output Blocks)?

2 — IAIK – Graz University of Technology

 Topic #2 www.tugraz.at

Topic #2: Embedded FPGAs (1)

Embedded FPGAs (eFPGAs) are IP blocks embedded into ASICs and SoCs,
representing FPGA cores. Depending on the use case, they have several advantages of
selecting an eFPGA over an FPGA.

• How are eFPGAs characterized?

• What are the use cases of eFPGAs?
• What are the advantages of eFPGAs?

3 — IAIK – Graz University of Technology

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Topic #3: SoC design process (1)

Designing SoC involves several steps and is an iterative process.

• Describe the SoC design process.

• What happens in every step?
• Who are the players process?

4 — IAIK – Graz University of Technology

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Topic #4: Alternative HDLs (1)

Today, most applications are still traditionally written in Verilog, System Verilog or
VHDL. However, there exist many more alternative HDLs, including Bluespec and
Chisel.

• What alternatives to traditional HDLs exist?

• Using code snippets, what are their characteristics?
• What are the major road blocks of replacing traditional HDLs?

5 — IAIK – Graz University of Technology

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Topic #5: SoC Bus Interconnection (2)

Communication using buses is a critical aspect of SoCs. Several architectures, for
example AMBA and AXI exist.

• Which types of bus technologies exist?

• What are the challenges when designing buses?
• Using the example of AXI, how could a bus protocol be designed?

6 — IAIK – Graz University of Technology

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Topic #6: Network-on-Chip (NoC) designs (1)

Network-on-Chip (NoC) can be seen as an alternative over traditional bus-based
architectures.

• How is the network-on-chip design paradigm characerized?

• What are the differences/advantages to bus-based architectures?
• How could a sketch of a NoC look like?

7 — IAIK – Graz University of Technology

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Topic #7: Rocket Chip Generator (1)

The RISC-V Rocket Chip Generator is an open-source SoC design generator. It can be
used to generate synthesizable RTL.

• What is the idea behind the generator?

• How can a core be configured and which HDL is used?
• For which RISC-V cores has the generator already been used?

8 — IAIK – Graz University of Technology

 Topic #8 www.tugraz.at

Topic #8: High Level Synthesis with Google XLS (1)

The XLS project by Google represents a high-level synthesis toolchain to generate
synthesizable designs from high-level specifications.

• What is high-level synthesis?

• Which toolchains exist for high-level synthesis of hardware?
• What is the idea behind the Google XLS project?

9 — IAIK – Graz University of Technology

 Topic #9 www.tugraz.at

Topic #9: Soft Cores and ARM/RISC-V Processors (2)

In a SoC, processors are often placed as a standalone unit, but can also be delivered as
a HDL design which is then synthesized and used as an FPGA configuration.

• What are soft cores and what is the difference to hard cores?
• Which ARM soft-cores exist?
• Which RISC-V soft-cores exist?

10 — IAIK – Graz University of Technology

 Topic #10 www.tugraz.at

Topic #10: FPGA Bitstream Encryption Basics (1)

Most FPGAs provide a mechanism to encrypt bitstreams. This feature protects designs
from being copied, altered or reverse engineered.

• Why is bitstream encryption needed on FPGAs?

• How does bitstream encryption work?

11 — IAIK – Graz University of Technology

 Topic #11 www.tugraz.at

Topic #11: FPGA Bitstream Encryption Vulnerabilities (1)

Bitstream encryption isn’t perfect. Research has shown that some can be broken in
various ways

• Which attacks on bitstream encryptions exist?

• How do the attacks work and why?

12 — IAIK – Graz University of Technology

 Topic #12 www.tugraz.at

Topic #12: Hardware Trojan Attacks in FPGAs (2)

Hardware trojans pose serious security concerns. In recent years, researchers showed
that FPGAs are vulnerable to such attacks.

• What is a hardware trojan and to what extent are they dangerous?

• Give examples of hardware Trojan attacks on FPGAs.
• Which countermeasures exist?

13 — IAIK – Graz University of Technology

 Topic #13 www.tugraz.at

Topic #13: FPGAs in Space (1)

FPGAs have been used in space for more than a decade. In order to be feasible for
space applications, FPGAs need to fulfill a row of requirements, including radio
tolerance.

• To which extent are FPGAs suitable for space?

• What are the main challenges when using FPGAs in space?
• Which manufacturers provide such technologies?

14 — IAIK – Graz University of Technology

 Topic #14 www.tugraz.at

Topic #14: Fault attacks on FPGAs (1)

FPGAs are vulnerable to fault attacks. In this attacks, incorrect system behavior is, for
example, triggered by voltage drops.

• Explain the basics of fault attacks.

• Which attack scenarios for fault attacks on FPGAs exist?
• What are possible countermeasures?

15 — IAIK – Graz University of Technology

 Topic #15 www.tugraz.at

Topic #15: EM Side-Channel Attacks on SoCs (1)

SoCs are vulnerable to ElectroMagnetic (EM) side-channels. In this attacks, incorrect
system behavior is, for example, triggered by voltage drops.

• Explain the basics of EM side-channel attacks.

• Explain the attack described in
https://www.iacr.org/archive/ches2015/92930599/92930599.pdf.
• What are possible countermeasures?

16 — IAIK – Graz University of Technology

 Topic #16 www.tugraz.at

Topic #16: Security Co-Processors (1)

Sometimes it’s necessary to keep things separate to get both security and performance.
Security co-processor can do that.

• When to use a security co-processor?

• How do they communicate?
• How do they perform in comparison?
• Which guarantees can they give?

17 — IAIK – Graz University of Technology

 Topic #17 www.tugraz.at

Topic #17: TEEs and Enclaves (2)

Trusted execution environments and enclaves allow for secure code execution without
separate hardware.

• Which commercial and academic approaches exist?

• How do they differ?
• Attackson/utilizing TEEs/Enclaves

18 — IAIK – Graz University of Technology

 Topic #18 www.tugraz.at

Topic #18: System-on-Chip simulation (1)

SoCs are often very complex systems, which is why pre-silicon verification has become
very important. Sophisticated simulation tools are needed in order to achieve these
goals.

• What are the application areas of SoC simulation?

• What are the advantages and disadvantages of SoC simulation?
• Which tools exist for this task?

19 — IAIK – Graz University of Technology

 Topic #19 www.tugraz.at

Topic #19: Open-Source Hardware Toolchains: SymbiYosys and Yosys (1)

Proprietary tools can be cumbersome and expensive. Open-source should run on
open-hardware built using open-source tools.

• What are the tools doing?

• How do they compare to their proprietary counterparts
• How to use them?

20 — IAIK – Graz University of Technology

 Topic #20 www.tugraz.at

Topic #20: Open-Source Hardware Toolchains: SymbiFlow (1)

Most FPGA Hardware toolchains are proprietary. SymbiFlow tries to fix that for a
number of chips.

• What is SymbiFlow?
• How to use it?
• Which devices are supporte?
• What are the limitations?

21 — IAIK – Graz University of Technology

 Topic #21 www.tugraz.at

Topic #21: Reverse Engineering: FPGAs vs ASIC (2)

FPGAs and ASICs tend to be proprietary black boxes. How to find out what going on.

• Which methods exist to reverse engineer?

• What are their limitations?
• What are manufacturers doing to prevent it?

22 — IAIK – Graz University of Technology

 Topic #22 www.tugraz.at

Topic #22: Design of Mixed-Signal SoCs (1)

Digital is fine, but the world is analogue. Applications like wireless communication
require both

• Which applications require mixed-signal SoCs?

• How is this done in SoC designs?
• How can this be realized with FPGAs?

23 — IAIK – Graz University of Technology

 Topic #23 www.tugraz.at

Topic #23: Booting Linux (2)

You press a button and suddenly there’s a shell. How did the device get there?

• How does Linux boot on ARM/RISC-V/x86?

• Which role plays the BIOS/UEFI?
• What is Secureboot and what can it do?
• What is a bootloader and why is there one called the Berkeley Bootloader (BBL)?

24 — IAIK – Graz University of Technology

 Topic #24 www.tugraz.at

Topic #24: Hardware Package Manager: FuseSoC/Bender (1)

Designs with a large number of modules can get messy really quick. Package
Managers can help

• How do they work?

• Which problems can they solve?
• What are the limitations?
• How do they resolve dependencies?
• Demonstration on how to use them.

25 — IAIK – Graz University of Technology

 Topic #25 www.tugraz.at

Topic #25: FPGAs and Neural Networks / ZynqNet (1)

FPGAs and SoCs are often used for neural computing, for example ZynqNet, which is
based on the Zynq SoC.

• Why are neural networks on FPGAs and SoCs so popular?

• What is the application area?
• Describe ZynqNet.

26 — IAIK – Graz University of Technology

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Topic #26: Hardware/Software Co-Verification (1)

Co-verification of SoCs addresses one of the most critical steps in the embedded
system design process, the integration of hardware and software.

• How is Hardware/Software Co-Verification defined?

• Why is Co-Verification necessary?
• Which Co-Verification methods exist?

27 — IAIK – Graz University of Technology