by Edit Model.

An Edit Model dialog box will appear in which Beta and Vto can be set LASTPROBLEMS
H1 HEAD 473
to 0.222 mA/V2 and ⴚ6 V, respectively. The value of Beta is determined using Eq. (6.17)
and the parameters of the network as follows:
IDSS 8 mA 8 mA
Beta = = = = 0.222 mA>V2
0 VP 0 2
0 -6 V 0 2
36 V2
Once the change is made, be sure to select Change Part Model before leaving the dialog
box. The JFET_N dialog box will appear again, but an OK, and the changes will be made.
The labels IDSS ⴝ 8 mA and Vp ⴝ ⴚ6 V are added using Place-Text. A blinking verti-
cal bar will appear marking the place where the label can be entered. Once entered, it can
easily be moved by simply clicking the area and dragging it to the desired position while
holding the clicker down.
Using the Indicator option on the first vertical toolbar displays the drain and source
voltages as shown in Fig. 7.74. In both cases the VOLTMETER_V option was chosen in
the Select a Component dialog box.
Selecting Simulate-Run or moving the switch to the 1 position results in the display of
Fig. 7.74. Note that VGS at -2.603 V is an exact match with the hand-calculated solution of
-2.6 V. Although the indicator is connected from source to ground, be aware that this is also
the gate-to-source voltage because the voltage drop across the 1-MÆ resistor is assumed to
be 0 V. The level of 11.405 V at the drain is very close to the hand-calculated solution of
11.42 V—in all, a complete verification of the results of Example 7.2.

PROBLEMS
●
*Note: Asterisks indicate more difficult problems.
7.2 Fixed-Bias Configuration
1. For the fixed-bias configuration of Fig. 7.75:
a. Sketch the transfer characteristics of the device.
b. Superimpose the network equation on the same graph.
c. Determine IDQ and VDSQ.
d. Using Shockley’s equation, solve for IDQ and then find VDSQ. Compare with the solutions of
part (c).

14 V

1.8 k⍀

FIG. 7.75
Problems 1 and 37.

2. For the fixed-bias configuration of Fig. 7.76, determine:

a. IDQ and VGSQ using a purely mathematical approach.
b. Repeat part (a) using a graphical approach and compare results.
c. Find VDS, VD, VG, and VS using the results of part (a).
3. Given the measured value of VD in Fig. 7.77, determine:
a. ID.
b. VDS.
c. VGG.
474 FET
SEMICONDUCTOR
BIASING
DIODES ⫺3 V

1.2 M⍀
IDSS = 8 mA
VD = 6 V VP = –4 V
+ VDS –
12 V 2.2 k⍀

ID

1 M⍀

–VGG

FIG. 7.76 FIG. 7.77

Problem 2. Problem 3.

4. Determine VD and VGS for the fixed-bias configuration of Fig. 7.78.

5. Determine VD and VGS for the fixed-bias configuration of Fig. 7.79.

FIG. 7.78 FIG. 7.79

Problem 4. Problem 5.

7.3 Self-Bias Configuration

6. For the self-bias configuration of Fig. 7.80:
a. Sketch the transfer curve for the device.
b. Superimpose the network equation on the same graph.
c. Determine IDQ and VGSQ.
d. Calculate VDS, VD, VG, and VS.
*7. Determine IDQ for the network of Fig. 7.80 using a purely mathematical approach. That is,
establish a quadratic equation for ID and choose the solution compatible with the network char-
acteristics. Compare to the solution obtained in Problem 6.
8. For the network of Fig. 7.81, determine:
a. VGSQ and IDQ.
b. VDS, VD, VG, and VS.
9. Given the measurement VS = 1.7 V for the network of Fig. 7.82, determine:
a. IDQ.
b. VGSQ.
c. IDSS.
d. VD.
e. VDS.
 LASTPROBLEMS
H1 HEAD 475

3V

FIG. 7.80 FIG. 7.81 FIG. 7.82

Problems 6, 7, and 38. Problem 8. Problem 9.

*10. For the network of Fig. 7.83, determine:

a. ID.
b. VDS.
c. VD.
d. VS.
*11. Find VS for the network of Fig. 7.84.

⫺4 V

FIG. 7.83 FIG. 7.84

Problem 10. Problem 11.

7.4 Voltage-Divider Biasing

12. For the network of Fig. 7.85, determine:
a. VG.
b. IDQ and VGSQ.
c. VD and VS.
d. VDSQ.
13. a. Repeat Problem 12 with RS = 0.51 k⍀ (about 50% of the value of that of Problem 12).
What is the effect of a smaller RS on IDQ and VGSQ?
b. What is the minimum possible value of RS for the network of Fig. 7.85?
14. For the network of Fig. 7.86, VD = 12 V. Determine:
a. ID.
b. VS and VDS.
c. VG and VGS.
d. VP.
476 FET
SEMICONDUCTOR
BIASING 18 V
DIODES
ID

2 kΩ

VD = 12 V
+
VG
12 V VDS IDSS = 8 mA
680 kΩ +
VGS VS
–
–
110 kΩ
0.68 kΩ

FIG. 7.85 FIG. 7.86

Problems 12 and 13. Problem 14.

15. Determine the value of RS for the network of Fig. 7.87 to establish VD = 10 V.

16 V

RD 2 k⍀
R1 36 k⍀
VD = 10 V
IDSS = 12 mA
VP = –8 V

R2 12 k⍀ RS

FIG. 7.87
Problem 15.
7.5 Common-Gate Configuration
*16. For the network of Fig. 7.88, determine:
a. IDQ and VGSQ.
b. VDS and VS.
*17. Given VDS = 4 V for the network of Fig. 7.89, determine:
a. ID.
20 V
b. VD and VS.
c. VGS.

1.2 kΩ

⫹2 V

FIG. 7.88 FIG. 7.89

Problems 16 and 39. Problem 17.
7.6 Special Case: VGSQ ⴝ 0 V LASTPROBLEMS
H1 HEAD 477
18. For the network of Fig. 7.90.
a. Find IDQ.
b. Determine VDQ and VDSQ.
c. Find the power supplied by the source and dissipated by the device.
19. Determine VD and VGS for the network of Fig. 7.91 using the provided information.

18 V

RD 1.8 kΩ

ID

+ VD 4V
I DSS = 4 mA
VDS
VP = –2 V 1.8 k⍀ 1 k⍀
– 16 V
–
VGS
+ IDSS = 4 mA
3.6 k⍀ VP = –6 V
1.2 kΩ
1.2 k⍀

FIG. 7.90 FIG. 7.91

Problem 18. Problem 19.

7.7 Depletion-Type MOSFETs

20. For the self-bias configuration of Fig. 7.92, determine:
a. IDQ and VGSQ.
b. VDS and VD.
*21. For the network of Fig. 7.93, determine:
a. IDQ and VGSQ.
b. VDS and VS.

FIG. 7.92 FIG. 7.93

Problem 20. Problem 21.

7.8 Enhancement-Type MOSFETs

22. For the network of Fig. 7.94, determine:
a. IDQ.
b. VGSQ and VDSQ.
c. VD and VS.
d. VDS.
23. For the voltage-divider configuration of Fig. 7.95, determine:
a. IDQ and VGSQ.
b. VD and VS.
478 FET
SEMICONDUCTOR
BIASING 24 V
DIODES

2.2 kΩ
10 MΩ
ID
Q

VGS(Th) = 3 V
I D(on) = 5 mA
+ VGS(on) = 6 V
VGS
Q
–
6.8 MΩ
0.75 kΩ

FIG. 7.94 FIG. 7.95

Problem 22. Problem 23.

7.10 Combination Networks

*24. For the network of Fig. 7.96, determine:
a. VG.
b. VGSQ and IDQ.
c. IE.
d. IB.
e. VD.
f. VC.
*25. For the combination network of Fig. 7.97, determine:
a. VB and VG.
b. VE.
c. IE, IC, and ID.
d. IB.
e. VC, VS, and VD.
f. VCE.
g. VDS.

VS ,VC

VG IB

VE

FIG. 7.96 FIG. 7.97

Problem 24. Problem 25.
7.11 Design LASTPROBLEMS
H1 HEAD 479
*26. Design a self-bias network using a JFET transistor with IDSS = 8 mA and VP = - 6 V to have
a Q-point at IDQ = 4 mA using a supply of 14 V. Assume that RD = 3RS and use standard
values.
*27. Design a voltage-divider bias network using a depletion-type MOSFET with IDSS = 10 mA
and VP = - 4 V to have a Q-point at IDQ = 2.5 mA using a supply of 24 V. In addition, set
VG = 4 V and use RD = 2.5RS with R1 = 22 M⍀. Use standard values.
28. Design a network such as appears in Fig. 7.39 using an enhancement-type MOSFET with
VGS(Th) = 4 V and k = 0.5 * 10-3 A>V2 to have a Q-point of IDQ = 6 mA. Use a supply of
16 V and standard values.
7.12 Troubleshooting
*29. What do the readings for each configuration of Fig. 7.98 suggest about the operation of the
network?

FIG. 7.98
Problem 29.

*30. Although the readings of Fig. 7.99 initially suggest that the network is behaving properly,
determine a possible cause for the undesirable state of the network.
*31. The network of Fig. 7.100 is not operating properly. What is the specific cause for its failure?

FIG. 7.99 FIG. 7.100

Problem 30. Problem 31.
480 FET
SEMICONDUCTOR
BIASING 7.13 p-Channel FETs
DIODES 32. For the network of Fig. 7.101, determine:
a. IDQ and VGSQ.
b. VDS.
c. VD.
33. For the network of Fig. 7.102, determine:
a. IDQ and VGSQ.
b. VDS.
c. VD.

FIG. 7.101 FIG. 7.102

Problem 32. Problem 33.

7.14 Universal JFET Bias Curve

34. Repeat Problem 1 using the universal JFET bias curve.
35. Repeat Problem 6 using the universal JFET bias curve.
36. Repeat Problem 12 using the universal JFET bias curve.
37. Repeat Problem 16 using the universal JFET bias curve.
7.15 Computer Analysis
38. Perform a PSpice Windows analysis of the network of Problem 1.
39. Perform a PSpice Windows analysis of the network of Problem 6.
40. Perform a Multisim analysis of the network of Problem 16.
41. Perform a Multisim analysis of the network of Problem 33.
 18 V PROBLEMS 543

3.3 kΩ

5.6 μF
Vo

IDSS = 5 mA
VP = − 4 V

Rsig 5.6 μF Vi Zo 4.7 kΩ

+ 0.5 kΩ
Vs 1.2 kΩ
Zi
–

FIG. 8.92
Problem 50.

e. Change Rsig to 0.1 k (with RL at 4.7 k) and calculate AvL and Avs. What was the effect of
changing Rsig on the voltage gains?
f. Change RL to 2.2 k and Rsig to 0.1 k and calculate Zi and Zo. What was the effect on both
parameters?
g. What general conclusions can you draw from the above calculations?

8.15 Cascade Configuration

51. For the JFET cascade amplifier in Fig. 8.93, calculate the dc bias conditions for the two identi-
cal stages, using JFETs with IDSS = 8 mA and VP = - 4.5 V.
52. For the JFET cascade amplifier of Fig. 8.93, using identical JFETs with IDSS = 8 mA and
VP = - 4.5 V, calculate the voltage gain of each stage, the overall gain of the amplifier, and
the output voltage Vo.
53. If both JFETs in the cascade amplifier of Fig. 8.93 are changed to those having specifications
IDSS = 12 mA and VP = - 3 V, calculate the resulting dc bias of each stage.
54. If both JFETs in the cascade amplifier of Fig. 8.93 are changed to those having the specifica-
tions IDSS = 12 mA, VP = - 3 V, and gos = 25 mS, calculate the resulting voltage gain for
each stage, the overall voltage gain, and the output voltage, Vo.

Vo

Vi
20 mV

FIG. 8.93
Problems 51 to 55, 65, and 66.
544 FET AMPLIFIERS 55. For the cascade amplifier of Fig. 8.93, using JFETs with specifications IDSS = 12 mA,
VP = - 3 V, and gos = 25 mS, calculate the circuit input impedance (Zi) and output imped-
ance (Zo).
56. For the cascade amplifier of Fig. 8.94, calculate the dc bias voltages currents of each stage.
57. For the amplifier circuit of Fig. 8.94, calculate the voltage gain of each stage and the overall
amplifier voltage gain.
58. Calculate the input impedance (Zi) and output impedance (Zo) for the amplifier circuit of
Fig. 8.94.

FIG. 8.94
Problems 56 to 58.

8.19 Computer Analysis

59. Using PSpice Windows, determine the voltage gain for the network of Fig. 8.73.
60. Using Multisim, determine the voltage gain for the network of Fig. 8.75.
61. Using PSpice Windows, determine the voltage gain for the network of Fig. 8.76.
62. Using Multisim, determine the voltage gain for the network of Fig. 8.77.
63. Using PSpice Windows, determine the voltage gain for the network of Fig. 8.82.
64. Using PSpice Windows, determine the voltage gain for the network of Fig. 8.85.
*65. Use the Design Center to draw a schematic circuit of the cascade JFET amplifier as in Fig.
8.93. Set the JFET parameters for IDSS  12 mA and VP = 3 V, and have the analysis deter-
mine the dc bias.
*66. Use the Design Center to draw a schematic circuit for a cascade JFET amplifier as shown
in Fig. 8.93. Set the analysis to calculate the ac output voltage Vo for IDSS  12 mA and
VP  3 V.