IEEE TRANSACTIONS ON VLSI SYSTEMS, 2004 1

Placement Constraints in Floorplan Design

Evangeline F.Y. Young, Chris C.N. Chu, and M.L. Ho

Abstract— In floorplan design, it is common that a designer handle range constraint in which some modules are restricted
will want to control the positions of some modules in the final to be placed within some rectangular ranges. The floorplanner
packing for various purposes like data path alignment and I/O in [10] can handle alignment constraint which may arise in
connection. There are several previous works [3], [5], [7], [8],
[10], [12]–[14] focusing on some particular kinds of placement bus-based routing. Different approaches are used to handle
constraints. In this paper, we will present a unified method to different kinds of constraints and there is no unified method
handle all of them simultaneously, including preplace constraint, that can handle all of them simultaneously.
range constraint, boundary constraint, alignment, abutment and In this paper, we will present a unified method that can
clustering, etc., in general non-slicing floorplans. We have used handle different kinds of placement constraints simultaneously,
incremental updates and an interesting idea of reduced graph to
improve the runtime of the method. We tested our method using including preplace constraint, range constraint, boundary con-
some benchmark data with about one eighth of the modules straint, alignment, abutment and clustering, etc., in general
having placement constraints and the results are very promising. non-slicing floorplans. Users can input a mixed set of con-
Good packings with all the constraints satisfied can be obtained straints and our floorplanner will be able to address all of
efficiently. them simultaneously. (It is reasonable to assume that the input
Index Terms— VLSI CAD, Physical design, Floorplanning, constraints are not contradictory to each other. However, we
Placement constraints, Optimization can also handle inconsistent user requirements by generating
a packing that satisfies the requirements as much as possible.)
I. I NTRODUCTION We make use of constraint graphs to handle the constraints and
can thus be used with any kind of floorplan representation
Floorplan design is an important step in physical design of
that computes the module positions by constraint graphs,
VLSI circuits to plan the positions of a set of circuit modules
e.g., sequence pair, BSG, O-Tree, CBL, Q-seq, TBS, etc..
on a chip in order to optimize the circuit performance. In this
In a constraint graph, every module is represented by a
floorplanning step, it is common that a designer will want to
vertex and the weighted directed edges represent the minimum
control the positions of some modules in the final packing
for various reasons. For example, a designer may want to
displacement between two modules. We can find the and

positions of a module by computing the longest path from
restrict the separation between two modules if there are many
a source to that module in the constraint graphs. In our
interconnections between them, or he may want to align them
approach, we modify the constraint graphs to enforce the
vertically in the middle of the chip for bus-based routing. This
required constraints in the resultant packing. This is done by
will also happen in design re-use in which a designer may want
augmenting the graphs with positive, negative or zero weighted
to keep the positions of some modules unchanged in the new
edges. These augmented edges will restrict the modules to be
floorplan. The analog designers will also be interested in a
placed correctly according to the requirements. This technique
particular kind of placement constraint called symmetry, and
of adding edges to constraint graphs has been used before for
some recent literature on this problem can be found from [1],
layout compaction [6] and packing of rectilinear blocks [4].
[2]. However, an effective method to control the absolute or
In this paper, we apply and generalize this method to handle
relative positions of the modules in floorplanning is non-trivial
different kinds of placement constraints in floorplan design. In
and this inadequacy has limited the application and usefulness
addition, we have devised an interesting idea of reduced graph
of many floorplanning algorithms in practice.
to improve the runtime of the algorithm. A direct implemen-
Several previous works have been done to handle some tation of the method is very expensive computationally and is
particular kinds of placement constraints. The floorplanners thus impractical. It will take 
time for each iteration of
in [3], [8], [12] can handle preplace constraint in which some
modules are fixed in position. The paper [5], [7], [14] work on

the annealing process where is the number of modules. We
improved this runtime by reducing the size of the constraint
boundary constraint in which some modules are constrained graphs and by updating the constraint graphs incrementally.
to be placed along one of the four sides of the chip for I/O
connection. The paper [13] generalizes the approach in [12] to
The time complexity of our algorithm is now   on
average for each iteration of the annealing process where
The work described in this paper was substantially supported by a grant is the number of modules having placement constraints.
from the Direct Grant for Research of the Chinese University of Hong Kong We tested our method with some MCNC benchmarks
(Project No. 2050219). (ami33, ami49 and playout) and a randomly generated data
Evangeline Young is with the Department of Computer Science and
Engineering, the Chinese University of Hong Kong, Shatin, N.T., Hong Kong set with 100 modules. Sequence pair representation [9] is
(email: [email protected]). used in our implementation. The results are promising and a
Chris Chu is with the Department of Electrical and Computer Engineering, tight packing with all the constraints satisfied can be obtained
Iowa State University, Ames, IA 50011 (email: [email protected]).
M.L. Ho is with ThizLinux Laboratory Limited, Kowloon Bay, Hong Kong efficiently. In the following sections, we will first describe
(email: [email protected]). the problem and have a brief review of the sequence pair
IEEE TRANSACTIONS ON VLSI SYSTEMS, 2004 2

representation and constraint graph. Section 4 will give a h(A,RR)

detailed explanation of our approach. Section 5 will explain
the techniques to reduce the size of the constraint graphs and to

v(A,TT)
update them incrementally. Experimental results will be shown
in Section 6. A

II. P ROBLEM D EFINITION

v(BB,A)
final packing
In floorplanning, we are given the information of a set of
modules, including their areas and interconnection and our
goal is to plan their positions on a chip to minimize the total h(LL,A)
chip area and interconnect cost. In this paper, we address this
Fig. 2. Notations &('*9:9;+.)</ , &('*),+>=?=@/ , 0A'*-,-B+>)</ and 0A'2)+CC</ .
floorplanning problem with placement constraint, i.e., besides
the module information, we are also given some constraints in
placement between the modules and our goal is to plan their Therefore notations 448
and
 5"5 
denote the hor- 
positions on a chip such that all the placement constraints can izontal distances of the lower left corner of
from the left
be satisfied and the area and interconnect cost are minimized. and the right boundary of the chip respectively. Similarly, we
We consider two general kinds of placement constraints, 
use  
7D7 and  6E

to denote the vertical distances
absolute and relative. For relative placement constraint, users of the lower left corner of
from the top and the bottom
can restrict the horizontal or vertical distance between two boundary of the chip respectively. Figure 2 illustrates these
modules to a certain value, or to a certain range of values. We

definitions. An absolute placement constraint of a module

use the notation 
 to denote the horizontal displacement can be written as:
from
’s lower left corner to  ’s. Note that this value is
positive if  ’s lower left corner is on the right hand side  44D
F G

of
’s and is negative otherwise. We use  
  to denote   
5H5 I G

the vertical displacement from
’s lower left corner to  ’s. 
 J
G
Similarly, this value is positive if  ’s lower left corner is
above
’s and is negative otherwise. Figure 1 illustrates
 
7D7 F G

these definitions. A relative placement constraint between two where KL and MN . If OP , we are restricting
modules
and  can be written as: the distance between the module and the boundary to a
 certain value and we will simply write it as 44D
"Q , 

  
 

 5H5 ,R ,  6E
! or 
7D7 SR respectively. 
 
   These two types of specifications are general enough to
express all common types of placement constraints. For ex-
where  and  . When  ! , we are restricting ample, if we want to restrict the placement of module
, 
the distance between the two modules to a single value and

we will write them simply as 
  "# or 
  $%  and T such that they all align horizontally, we can specify the
following relative placement constraints:
respectively.
 
  U


 J T U

A As another example, if we want to restrict the placement of

module
at the lower right corner of the chip, we can specify
the following absolute placement constraints:
-v(A,B)

y(A)
B  
 5H5 I VXW

final packing   E
U

y(B) h(A,B)
where V W is the width of
. We can now define our floorplan-
x(A) ning problem with placement constraint, FP/PC, as follows:
x(B)
h(A,B) = x(B) - x(A) Problem FP/PC: Given the information of a set of modules
v(A,B) = y(B) - y(A) including their areas and interconnection, a set YSZ of relative
Fig. 1. Notations &('*),+.-/ and 01'2)+3-,/ .
placement constraints and a set Y of absolute placement
constraints, the goal is to pack the modules in a rectangular

region such that all the given placement constraints are
Absolute placement constraint is specified similarly except satisfied and the area and interconnect costs are minimized.
that one of the two modules in the relationship is a boundary
of the chip. We use 44 , 5"5 , 6 and 787 to denote the We assume that the input set of placement constraints will
left, right, bottom and top boundary of the chip respectively. not be contradictory to each other, i.e., there exists a feasible
IEEE TRANSACTIONS ON VLSI SYSTEMS, 2004 3

Horizontal Vertical
The minimum area packing can thus be obtained by putting


constraint constraint
graph graph the -coordinate and -coordinate of a module 0 as the length
B C A of the longest path from a source to 0 in the horizontal and
A C vertical constraint graph respectively.
D
B A D B IV. H ANDLING P LACEMENT C ONSTRAINTS IN
(a) (b) C ONSTRAINT G RAPHS
Fig. 3. An example of sequence pair abcd, bacd
. There are two kinds of placement constraints, relative and
absolute. A relative placement constraint describes the rela-
tionship between two modules, while an absolute placement
packing in which all the constraints can be satisfied simul- constraint describes the relationship between a module and
taneously. However if the input requirements are inherently the chip. We will first discuss the approach to handle relative
inconsistent, our floorplanner will still generate a packing that placement constraint and will later discuss how this approach
satisfies the requirements as much as possible. can be used to handle absolute placement constraint by making
a simple modification to the constraint graphs.
III. P RELIMINARIES
A. Sequence-Pair [9] A. Relative Placement Constraint
We use sequence-pair in our implementation to represent In relative placement constraint, users can restrict the hor-
a general non-slicing floorplan. A sequence-pair of a set of izontal or vertical distance between two modules to a certain
modules is a pair of combinations of the module names. For range of values. For example, users can specify that
 , 
example, E      is a sequence-pair of the module G (or 
   G ) where    and   
set  AA . We can derive the relative positions between meaning that  is at a distance of  to  on the right hand
the modules from a sequence-pair  by the following rules: side of
( is at a distance of  to  above
). When  R ,


If $ 2 , then module  is on the we are restricting the distance to a certain value. Notice that
both  and  can be zero, positive, negative, 1"2 or 342 . (It is
right of module  .


If $  !2"# , then module  is below trivial to have  5342 and  61"2 , so we assume that this
will not happen.) In order to realize the required constraints in
module  .
the final packing, we will add a single edge or a pair of edges
Figure 3(a) shows a packing for the sequence pair
to the corresponding constraint graph $ as described below.
 :   .

We use V /7 to denote the weight of an edge 7 .
Case 1) If %8342 , insert an edge 7 E
into $ 
B. Constraint Graph
with V 7 93X . 
We can use a pair of constraint graphs to represent the hori- Case 2) If %:1"2 , insert an edge 7
 into $ 
zontal and vertical relationships between the module positions with V 7 R . 
imposed by a sequence pair. A horizontal (vertical) constraint Case 3) Otherwise, insert two edges 7ZX 
 and 7  
graph $% ( $"& ) for a set of 
modules is a directed graph  E

into $ s.t. V 7Z R and V 7 ,;3X .  

with vertices, and the vertices represent the modules and the The correctness of the above steps follows from Theorem 1
edges represent the horizontal (vertical) relationships between which is proved by making use of Lemma 1 and Lemma 2.
the module positions. We will have an edge from  to  labeled Lemma 1: If there is an edge from
to  labeled  in $ % ,
V(' in $% where V)' is the width of  if and only if module 
is on the right hand side of module  . Similarly, we will have
  B 

<1=  1"2  .
Proof: According to the definition of horizontal con-
an edge from  to  labeled *' in $"& where ' is the height straint graph, if there is an edge from
to  labeled  in the
of  if and only if module  is above module  . We can build graph, the lower left corner of  is at a distance of at least 
these graphs directly from a sequence-pair representation  as from that of
horizontally to the right, i.e.,  (>
?1@  
follows: which is equivalent to  X 

<1=  1"2  . 

Insert an edge from  to  in $ % labeled V ' if and only Lemma 2: The conditions   

1A  1"2 
 and

if $ )+*,2+*, . 
B 342  
 B3C  are equivalent.

Insert an edge from  to  in $& labeled - if and only Proof: The condition   

D1E 1"2  is 

if $ )+*,2,+ . equivalent to  >  

F1G . We can then write  > 
Figure 3(b) shows the constraint graphs without edge labels 
1H as 
K  
 I3J , which is equivalent to
for the sequence pair .       . 
B 342   B3C  .
We can compute the minimum area packing corresponding Theorem 1: The relative placement constraint
  
to a sequence pair efficiently by using the constraint graphs. 
G (or 
 # G ) can be achieved in the final pack-
In a horizontal constraint graph, a weight  on an edge /:   ing by inserting edges into the horizontal (vertical) constraint
means that “  should be at least  units to the right of  ”. graph as described in the above cases if the packing is feasible.
Similarly, in a vertical constraint graph, a weight  on an Proof: Without loss of generality, we only prove the

edge    means that “  should be at least  units above  ”. correctness for the horizontal direction. The proof for the
IEEE TRANSACTIONS ON VLSI SYSTEMS, 2004 4

vertical direction follows similarly. To prove the correctness In the following, we use  and  to denote the two
of these steps, we need to show that if the packing is feasible additional nodes in the horizontal constraint graph:  repre-

after inserting these edges, the constraint 
  ,#  will sents the left boundary and  represents the right boundary.
be satisfied in the packing. In the following, $ % denotes the Similarly, we use  and  - to denote the two additional nodes

horizontal constraint graph and 
denotes the -coordinate in the vertical constraint graph:  represents the top boundary
of the lower left corner of module
. Assume that the packing and  - represents the bottom boundary. After adding these
is feasible, i.e., both constraint graphs have no positive cycles nodes, we can handle absolute placement constraint easily
(a positive cycle in a weighted directed graph is a directed as described below. Notice that there is no such cases as
cycle in the graph with positive total weight) and the position 
 44  
, 5H56
,  
6 or  7D7D
in the following 
of each module can be found by computing the longest path and  and  are non-negative numbers because we will not
from a source to its corresponding vertex in the two constraint consider packing modules outside the boundary of the chip:
graphs. 
 G :

44D

Consider the three different cases for the constraint 
 
– If  1"2 , insert an edge 7ZX   
in $% with 
G :
 
 
V /7AZ ,! ;
Case 1)  9342 , i.e., we want  to lie in 342 
1 – else, insert edges 7Z   
and 7 

  in
 
G . According to Lemma 2, this condition is equiva-   
 
$ % with V 7 Z ,R and V 7 53X .
lent to 
"  3 ,1"2  , which, by Lemma 
 
5H5  G :


1, can be achieved by inserting an edge from  to
– If  1"2 , insert an edge 7ZX 
  in $% with
 

labeled 3X .
Case 2)  1"2 , i.e., we want  
to lie in 
1 1"2  . V /7AZ ,! ;
 
According to Lemma 1, this can be achieved by – else, insert edges 7 Z

$ % with V 7 Z ,R

 and 7
and V 7 53X .

in
  
inserting an edge from
to  labeled  .
Case 3) 342


FI


1"2 , i.e., we want  to 
  6E
B  :

 
lie in the range 
1! 
1RG . Notice that – If  1"2 , insert an edge 7ZX  - 
in $"& with 
 
the range 
1 
B1 G is equivalent to the  V /7 Z ,! ;

range 
1 1"2  342R
1G . The first  – else, insert edges 7 Z  - 
and 7  
 - in
 
condition can be achieved by inserting an edge from 
$ & with V /7 Z ,! and V 7 ,;3X .  

to  labeled  . The second condition    

342  
1!G is equivalent to
 
 )3   
7D7 

– If 
G :

1"2 , insert an edge 7 Z
  in $ & with 

,1"2  according to Lemma 2 and can be achieved
 V /7 Z ,! ;
by inserting an edge from  to
labeled 3X .
– else, insert edges 7 Z
  and 7   
in
 
Therefore we need to insert a pair of edges, one from

to  labeled  and the other one from  to


$ & with V /7 Z ,! and V 7 ,;3X .  
labeled 3X . The proof of correctness of these steps for absolute placement
constraint follows directly from that for relative placement
constraint and we will not repeat it here.

B. Absolute Placement Constraint

C. Examples of some Commonly Used Placement Constraint
Absolute placement constraint restricts the absolute place-
ment of a module with respect to the whole chip. Users can Using the above specifications for absolute and relative
restrict the placement of a module such that its distance from placement constraint, we can describe many different kinds
the boundary of the chip is within a certain range of values. We of placement constraints. In this section, we will pick a few
can handle these kinds of constraints using a method similar commonly used ones and show how each can be specified
to that for relative placement constraints, i.e., by inserting a using a combination of the relative and absolute placement
single edge or a pair of edges to the constraint graphs. To constraints. In the following, we use 
and
to denote 

achieve this, we augment the horizontal and vertical constraint

the and coordinates of the lower left corner of module A
graphs each with two extra nodes. For the horizontal constraint respectively and we use W and V W to denote the height and
graph, we add two nodes: one is a source with zero weighted width of A respectively.
out-going edges to all the other nodes, and the other one is 1) Alignment: To align module
,  , T and horizontally
a sink with zero weighted in-coming edges from all the other (Figure 4), we can impose the following constraints:


nodes. The source represents the left boundary and the sink
represents the right boundary of the final packing. Similarly, 
  U

we add two nodes to the vertical constraint graph: one is a  J T  U

source with zero weighted out-going edges to all the other   T" U
nodes and one is a sink with zero weighted in-coming edges
from all the other nodes. The source represents the bottom We restrict the vertical distances between these modules to be
boundary and the sink represents the top boundary of the final zero, they will thus all align horizontally. Six additional edges
packing. will be inserted into the vertical constraint graph.
IEEE TRANSACTIONS ON VLSI SYSTEMS, 2004 5

A C D B

A
p
q
v(A,B) = 0 v(B,C) = 0 v(C,D) = 0
h(LL,A)=p v(BB,A)=q
Fig. 4. Examples of alignment constraint.

Fig. 6. Examples of preplace constraint.

2) Abutment: To abut module
,  and T horizontally

(Figure 5), we can impose the following constraints:
In this formulation, we restrict 
to be Z to units  
 
  U from the left boundary and
to be (Z to

units from


 the bottom boundary, so A will lie in the required rectangular





 E T U
region    Z 

 I V W
  Z    . Two additional
edges will be inserted into each constraint graph.
 E T I

V

where VXW and V
are the widths of module
and 

respectively. In this formulation, the vertical distances between range
these modules are zero, so they will align horizontally. On the
other hand,  is restricted to be on the right hand side of

by V W units and T on the right hand side of  by V units,
A
so they will be abutting with each other horizontally. Four y2
additional edges will be inserted into each constraint graph.
x1
y1
x2

h(LL,A)=[x1, x2 ] v(BB,A)=[y1, y2 ]
7
8 Fig. 7. Examples of range constraint.
B 10
A C 5) Boundary Constraint: To place module
at the upper
right corner of the final packing, and place  along the top
boundary (Figure 8), we can impose the following constraints:
h(A,B)=8 h(B,C)=7 v(A,B)=0 v(B,C)=0

 5"5 I VXW

Fig. 5. Examples of abutment constraint. 

 
7D7 F W

3) Preplace Constraint: To preplace module
with its


 J7D7 F


lower left corner at ? (Figure 6), we can impose the In this formulation, we restrict the horizontal distance between
following constraints:
and the right boundary to be the width of
and the vertical
 448
I  distance between
and the top boundary to be the height

 6E

of
, so module
will be placed at the upper right corner
in the final packing. Besides,  is restricted to be units

We restrict 
to be  units from the left boundary and 

 from the top boundary, so  will abut with the top boundary
to be  units from the bottom boundary, so
will be preplaced as required. We need to insert two edges into the horizontal
with its lower left corner at ; in the final packing. Two  constraint graph and four edges into the vertical constraint
additional edges will be inserted into each constraint graph. graph.
4) Range Constraint: To restrict the position of
to within 6) Clustering: To cluster module
,  and T around at


the range    Z6   Z   (Figure 7), we



 a distance of at most  units away vertically or horizontally
can impose the following constraints: (Figure 9), we can impose the following constraints:

 448
F Z 
   
I 3 ;1  


 6E


 Z     I 3 ;1  
IEEE TRANSACTIONS ON VLSI SYSTEMS, 2004 6

Range in which the

lower left corners
6 A of B and C can lie.
B 9
15

20
7 B A
C

20
20 20

v(B,C) = 0
v(A,B) = [-20,20] v(A,C) = [-20,20]
h(A,RR)=15 v(A,TT)=6 v(B,TT)=9
h(A,B) = [-20,20] h(A,C) = [-20,20]
Fig. 8. Examples of boundary constraint.
Fig. 10. An example of an arbitrarily set of mixed constraints.

  T 3 ; 1  
V. A LGORITHM AND I MPLEMENTATION
  
3 ; 1  
We use simulated annealing with sequence pair repre-
   3 ; 1   sentation. In each step of the annealing process, we will
   T 3 ; 1   generate a new packing and compute its area and interconnect
cost. We use the vertical and horizontal constraint graphs to
In this formulation, we restrict the horizontal and vertical
to be at most  units in
compute the position of each module. In order to satisfy the
distances of
,  and T from
given placement constraints, we will augment the graphs with
both directions, so they will cluster around at a distance
of at most  units away. Six additional edges will be inserted
edges as described in the above section. We call these edges
constraining edges. If the packing is feasible after adding
into each constraint graph.
these edges, i.e., no positive cycle exists in the constraint
graphs, we will compute the position of each module as
usual and all the constrained modules will be placed at the
correct positions. However it is possible that some constraints
cannot be satisfied after adding those constraining edges,
5 5
the packing is then infeasible (note that a packing can be
B infeasible because the input set of placement constraints are
D Range in which the
5

lower left corners of inherently contradictory to each other or the relative positions
A, B and C can lie. implied by the sequence pair are contradictory to the input
A C
5

set of constraints). Feasibility of a packing can be checked

by detecting positive cycles in the constraint graphs. If a
h(D,A)=[-5,5] h(D,B)=[-5,5] h(D,C)=[-5,5] packing is infeasible, we will pack the modules as if there is
v(D,A)=[-5,5] v(D,B)=[-5,5] v(D,C)=[-5,5] no placement constraint and compute a penalty term in the cost
function to penalize the violations. This strategy ensures that
Fig. 9. Examples of clustering constraint.
all feasible solutions are reachable, and can drive the packing
solution to one that satisfies the constraints as much as possible
7) General Placement Constraint: We can use combina-
in case the user requirements are inherently inconsistent. We
tions of the above relative and absolute placement constraints
observed a stable convergence in the annealing process using
to specify different kinds of mixed constraints in general. For
this scheme and all the placement constraints can be satisfied
example, to restrict the placement such that module  and T
at the end of the annealing process in all our experiments.
align with each other horizontally and they cluster around

We will describe the algorithm in details in the following sub-
at a distance of at most 20 units away (Figure 10), we can
sections.
impose the following constraints:
 J T  U A. Detecting Positive Cycles by Reduced Graphs
 
   3
1U 1 1U1 After augmenting those constraint graphs with constraining
 
 T  3
1U 11U1 edges, we need to test their feasibility by detecting positive
 
  3
1U 11U1 cycles in them. A direct implementation of some classical
 
 T 3
1U 11U1
algorithm (e.g., the modified Floyd-Warshall algorithm [11])
to check positive cycles will take   
time where is the 
The first constraint aligns  and T horizontally and the next total number of modules. In order to improve the runtime, we
four cluster  and T around
to within a distance of 20 units will reduce the size of the constraint graphs before checking
away. We need to add four additional edges to the horizontal for cycles. This is possible because of the following lemma
constraint graph and six to the vertical constraint graph. 
and theorem. We use $ %  % and $ &  & to denote
IEEE TRANSACTIONS ON VLSI SYSTEMS, 2004 7

the original horizontal and vertical constraint graphs obtained

 
is obtained from % by inserting the constraining edges.
from a sequence pair respectively. $ %  % and $ &  &
  

%
Therefore, every path  from  *to  Z .-2/ * 0
on the cycle T .-)/ * 9 10
 ;+  <+
.-)/ * 0 .-)/ *9 10 
are obtained from $ % and $ & respectively by adding the in $ % where 0<  (   F3 will correspond to an edge from
constraining edges. to  in % and the weight of the edge is not less
*
 Z
 
Lemma 3: Any cycle in $ % ( $ & ) must contain some edges than the total weight of the path  . We can conclude that a

in  % 3  % (  & 3  & ).
Proof: The original constraint graphs $!% and $& ob-

positive cycle must also exist in % .
Constructing % and & takes

1    
time where 
tained from a sequence pair representation must be acyclic. is the total number of constraining edges and is number of


Therefore, any cycle in $ % and $ & must contain at least one  modules with placement constraints. Notice that the number
constraining edge. of constraining edges  is usually much smaller than  ,  
From this lemma, we can infer that any cycle in $ %
so the construction time for % and & is . The   

($ & ) must contain at least two modules which have place- construction can be done by performing a single-source-
ment constraints. Therefore, instead of detecting positive cy-

longest-path algorithm in $% and $"& once for each  where
E   
   
%  A  %
   
cles in $ % and $ & , we will construct two reduced graphs
and &   & from $ % and $ & respectively
. Checking cycles in % and & by the modified Floyd-
   
where   is the set of all modules with placement con-
Warshall algorithm [11] takes 1 time because 1"
is an upper bound on the number of edges in % and & .

 
straints,  % is the set of all edges .7 0   0 
        This time complexity can be further reduced in practice by
   $ %  and  & is the set of all edges
   
    
 H0  performing incremental updates as described in the following.
7 0   0  O    0  $ &  . For any
   
edge 7 0  B  % , V 7 6 "!$#   "!$#   0  where 0  denotes

the longest path from 0 to in $!% , and, similarly, for any edge
B. Moves and Incremental Updates
7 0     
 "!&%  ' "!&%  '
 & , V 7 6H 0  where 0  denotes the In every iteration of the annealing process, we will modify
    
longest path from 0 to in $& . The constraining edges will the sequence pair by one of the following three kinds of moves:

be inserted into % and & to give % and & respectively.
We will then check for positive cycles in % and & and this
 [M1] Change the width and height of a module.
 
is equivalent to checking cycles in $ % and $ & according to
[M2] Exchange two modules in both sequences.
[M3] Exchange two modules in the first sequence.
the following theorem.  
Theorem 2: A positive cycle exists in % ( & ) if and only The constraint graphs will not change much after each move,
 
if a positive cycle exists in $ % ($ & ). so we do not need to reconstruct them once in every iteration.
Proof: Without loss of generality, we will only prove We can take advantage of this incremental updates in two
for the horizontal constraint graph. The proof for the vertical  
different places: the construction of $!% and $"& , and the
constraint graph follows similarly.
“If” condition: If there exists a positive cycle T in % , the
 construction of % and & .
1) Incremental Updates of $% and $& : In move M1, a

edges in T must either be a constraining edge or an edge in
% . However every edge 7 0    
in % actually corresponds to
module
is picked and changed in its width and height, so the
structures of the constraint graphs will remain the same except
a sequence of edges in $% (the longest path from 0 to in $!% ).  that all the out-going edges from
will have their weights

Since $ % is obtained from $% by inserting the constraining changed. In our implementation, the weights on the edges are
edges, a positive cycle must also exist in $ % . stored at the source vertices because all the edges out-going
“Only if” condition: If there exists a positive cycle T from the same vertex will have the same weight. Therefore,
 Z 

   ( 
 Z in $ % where the   for 0< )* ,+    are vertices in we only need to update the weight of vertex
in both $!% and
$ % , at least two of these vertices must correspond to modules $"& after M1 and this will take constant time. In move M2, two
with placement constraint according to Lemma 3. Denote these modules
and  are picked and switched in position in both
vertices corresponding to modules with placement constraint sequences. The structure of the constraint graphs will again
by  Z  .-)/ 10 .-2/  0 .-2/43 0
   where  5  and 0 6 

6  0B1 remain the same except that the vertices corresponding to

+ for all 0 7+ 8 ,+
    3 . Note that  Z  -)/ 10 .-2/  0 .-2/43 0
   and  will be switched in position. This will affect the weights
also exist in % because they correspond to modules with of the out-going edges from these two vertices. Therefore we
placement constraints. Consider the path  along T from  * -)/ * 0 only need to update the weights in these two vertices in both
to  .-)/ *9 :0 where G0 +

 . This path will either be a single $% and $& and this will again take constant time. In move M3,
*
Z
constraining edge or a sequence of edges from $,% . If  is a
 two modules
and  are picked and switched in position in
 
single constraining edge, this edge will also exist in % since the first sequence. The structure of the constraint graphs will
% is obtained from % by inserting the constraining edges. change after this move. However, only those modules lying
*
If  is a sequence of edges from $!% , there must also be an
 .-)/ * 0 .-)/ *9 :0 
between
and  in the first sequence will be affected and
edge 7  
in % such that V 7 is not less than =
there are of them on average. Besides, each update can be
*
 Z
the total weight of the path  . It is because the weight of the  
 .-2/ * 0 .-)/ * 9 10 
done very efficiently (either an edge 7 0  in $& is deleted
edge 7  in % is computed as the longest path and a new edge 7 0   '
is inserted into $ % , or an edge 7 0   '
.-2/ * 0 .-2/ * 9 :0
 Z
from  to  in $ % and it must be at least as long as in $ % is deleted and a new edge 7 0  is inserted into $ & .  
* .-2/ * 0 .-)/ *9 :0
Z
the path  which runs from  to  
along the cycle T Therefore, $ % and $ & can be updated very efficiently in 
 -)/ 0 .-)/ *9 :0
*
Z
in $ % . This edge 7   Z will also exist in % since time.
IEEE TRANSACTIONS ON VLSI SYSTEMS, 2004 8

2) Incremental Updates of % and & : % and & are

    desired position. This penalty term will be discussed in more
obtained from $ % and $ & by keeping only those vertices with
 '  details in the following paragraph.

placement constraints. The weight of an edge 7 0  in %
( & ) is the longest path from 0 to in $ % ($ & ). After move  E. Handling Infeasible Packings
 % and

M1, M2 or M3 of the annealing process, the edge weights in
& may change because the longest path between two If a packing is infeasible, i.e., positive cycles exist in the
vertices in $% and $& will have changed. Fortunately this will
only affect a fraction of the edges in % and & .
  constraint graphs, we will pack the modules as if there is no
constraint and compute a penalty term . For example, if an
In move M1, a module
is selected and changed in width
  edge 7R 
 labeled  is inserted into the horizontal
and height. The weight of an edge 7 0  in % or & will be  ' constraint graph because of a given placement constraint,
affected if 0 can reach
in the constraint graphs $!% or $"& . the penalty term due to this edge in case of an infeasible
packing will be     . This gives a
(
This happens if 0 is lying before
in the second sequence   (3 
(3U

GZ good estimation of how far the modules are from their desired
and there are

of them on average. We need to perform
once the single-source-longest-path algorithm in $ % or $ & for positions. Notice that we need to accept infeasible intermediate
 
each of them and update the weights of all the edges 7 0  in  ' solutions in the annealing process because it may happen in
% or & for all    
. In M2 and M3, two modules
and some cases that a good feasible solution can only be reached
 are selected and switched in position in the sequence pair.
Similarly, an edge 7 0   
in % or & will be affected if 0
  from an initial starting point with some infeasible intermediate
solutions in between during the searching process. (If the
can reach
or  in $% or $& before or after the move. This input set of placement constraints are inherently contradictory
to each other, there will always be positive cycles in the
 ( 
happens if 0 is lying before
or  in the second sequence
constraint graphs. The floorplanner will then pack the modules
and there are about

of them on the average. Similarly, we
need to perform once the single-source-longest-path algorithm as if there is no constraints and the penalty term will drive the
for each of these affected modules and update the weights of
  result towards one that satisfies the requirements as much as
 % and & takes

the corresponding edges in % and & . Therefore updating
time on average.   
possible.) The convergence of the annealing process is very
stable using this scheme and all the placement constraints can
be satisfied at the end of the process in all our experiments.
C. Time Complexity
VI. E XPERIMENTAL R ESULTS
In each iteration of the annealing process, we modify the
sequence pair by performing move M1, M2 or M3. After the   We tested our floorplanner on a set of MCNC benchmark
move, we need to update $ % , $ & , % and & . Updating $ %
and $ & takes 
as explained above. Updating % and &
  data (ami33, ami49 and playout) and a randomly generated
data set with 100 modules1 . Ami33, ami49 and playout were
takes   
time on average. After updating these graphs,   chosen because they are the largest (with 33, 49 and 62

we need to check for positive cycles in % and & which
are obtained from % and & respectively by inserting the
 modules respectively) among all the MCNC benchmarks. For
+ +
each experiment, the temperature is set to ?  U initially
constraining edges. The cycle checking step takes 1    and is lowered at a constant rate of 0.95 to 0.98 until it is
time. Therefore the total time taken per iteration is 1   + +
below  U GZ . The number of iterations at one temperature
1  1   
on average, i.e., , since the number    step is 80.  in the cost function is set such that the costs
of constraining edges  is usually much smaller than .  of the wirelength and total area are approximately equal. is
set at a high value (30 to 40) to ensure that all the placement
D. Annealing Schedule and Cost Function constraints can be satisfied at the end. All the experiments
were carried out on a 400 MHz Sun Ultra IIi.
The temperature schedule of the annealing process is of the
form 7 $ 
 7 D3 for all >  +
. At each temperature + We tested our floorplanner using the benchmark data and
a randomly generated data set (random100) by imposing dif-
step, enough number of moves are attempted 
until the

total
ferent combinations of placement constraints to the modules.
number of moves exceeds a certain number where is a
The results are shown in Table I. The result reported in
user defined constant. The temperature is initialized to a large
each row is an average obtained by running the experiment
value at the beginning and the annealing process terminates
six times using three different sets of placement constraints.
when the temperature is low enough. The best solution found
Notice that the number of constraints refers to the number of
will then be used to go through a “final baking” process in
constraining edges in the graphs. We can see from the table
which only better solutions will be accepted.
that the algorithm is very efficient. The percentage deadspace
The cost function is defined as
,1 1 where
is the
ranges from 5.9% to 8.4% and all the placement constraints
total area of the packing. In our current implementation,  is
can be satisfied in all the experiments. Besides, we can see
the half perimeter estimation of the interconnect cost but this
that the changes in deadspace area and total wirelength in
term can be replaced by other more sophisticated interconnect
order to handle the placement constraints are very small.
cost estimations. is a penalty term which is zero when all
Figure 11, 12, 13, 14 and 15 show five resultant packings
the placement constraints are satisfied, and is otherwise the
sum of the squares of each violation, where a violation is 1 The data sets are available in http://www.cse.cuhk.edu.hk/
measured by the distance the constrained module is from its ˜fyyoung/data.
IEEE TRANSACTIONS ON VLSI SYSTEMS, 2004 9


for ami33, ami49 and playout. (Notice that the origin U  U is
at the upper right corner in all these packings.)
21
We have also compared our results with [13] that focuses 19 22
1 Width: 104.13
on handling range constraint in slicing floorplan. We repeated 3
26
the same experiments on range constraint using our new 28
Height: 116.624

unified method and the results are shown in Table II. The 30 Area: 12144
result reported in each row is an average obtained by running 16 24
Mini. Area: 11563.3
27 0
the experiment five times using the benchmark data, ami33, 25 Iterations: 66243
ami49 and playout. The scaled runtimes in the fourth column 14 DeadSpace: 4.78183%
were obtained by dividing the original runtimes from [13] 20 29
User Time: 28.79 sec
by a factor of 2.46, the ratio between the speeds of floating 23 12
17 2 Volate No: 0/14
point computation of the two machines used. We can see 4 18
that the performance of the two methods are very similar in 6
both runtime and deadspace. The floorplanner in [13] was a 5 32
11
little bit faster because it considered slicing floorplans only. 10 31
Our floorplanner could give smaller deadspace although the
floorplanner in [13] have actually allowed the modules to 8 9 7 15 13
be very flexible in shape (with aspect ratio in the range of

U   U1 ), while we considered a discrete number of shapes

for each module only in our experiments. However, the most Fig. 11. Modules 4, 5, 6, 7, 8, 9 and 10 cluster at the lower left corner of
important difference is that unlike the method in [13] which the chip.
focuses on only one particular kind of placement constraint,
our method is more general and can handle different kinds
of placement constraints simultaneously. We have also tried
another data set from the paper [14], which can handle
boundary constraint in slicing floorplan. A resultant packing is 16 5 20 19
shown in Figure 16. The amount of deadspace obtained in [14] 0 3 Width: 131.963

is smaller because optimal shaping was done in their slicing 21 4

24
Height: 93
13 26
floorplanner. Area: 12272.6
29
In order to demonstrate the effects of an input set of 15 14
17 22
2 27 Mini. Area: 11563.3

infeasible constraints, we performed an experiment in which Iterations: 66243

the required set of constraints were contradictory to each other. 10 18
7 6 DeadSpace: 5.77934%
12
11 8
The resultant packing is shown in Figure 17. In this example, 9
User Time: 18.14 sec
we require module 5 to be packed along the left boundary, Volate No: 0/12
31 1 32
and on the right hand side of module 4 at the same time. 25 30 23 28

These contradictory requirements will always lead to positive

cycles in the constraint graphs. The floorplanner will then pack
Fig. 12. Modules 6, 7, 8, 9, 10, 11 and 12 align horizontally.
the modules as if there is no constraints and the penalty term
will drive the result towards one that satisfies the requirements
as much as possible, as we can see from the example in
Figure 17. Figure 18 shows the growth in runtime with respect
to the number of placement constraints and we can see that
45
the relationship is almost linear. 23 6
2 Width: 208.303
12 1
37 Height: 177.802
VII. C ONCLUSION 34 32
27 15 Area: 37036.6
44
In this paper, we presented a method to handle different 9
38
Mini. Area: 35443
47
13
kinds of placement constraints in floorplanning simultane- 31
11 14 Iterations: 66243
ously. In this method, placement constraints are handled by 46
42
DeadSpace: 4.30288%
augmenting the constraint graphs with edges of positive, neg- 20
0
40
35 10
3
User Time: 41.09 sec
ative or zero weights. We have used incremental updates and 26
5 33 22
an interesting idea of reduced graph to improve the runtime 41 39 21 29 Volate No: 0/20

of the algorithm. Several benchmark data are used for testing 19

18 25
30
and the results are very promising. Good packings with all the 4
36 7
48
17
constraints satisfied can be obtained efficiently. 8 24 16 28 43

R EFERENCES Fig. 13. Modules 10, 12, 13, 14 and 15 cluster around module 11.
[1] F. Balasa and K. Lampert. Symmetry within the Sequence-Pair Rep-
resentation in the Context of Placement for Analog Design. IEEE
IEEE TRANSACTIONS ON VLSI SYSTEMS, 2004 10

[13] (300MHz Pentium II) Our Method

Data Set Deadspace(%) Original time (sec) Scaled time (sec) Deadspace(%) Time (sec)
ami33 1.56 53.85 21.89 2.95 43.62
ami49 3.14 118.02 47.98 2.92 65.41
playout 3.00 230.85 93.84 2.76 109.46

TABLE II
C OMPARISONS WITH THE R ESULTS IN [13].

No. of Time Deadspace Wirelength

 No. of 34 15 36 41 33 46
30 45
Placement (sec) % 
Constraints 0 29
48
16 38 Width: 228.672
Constraints Violated 17 12
39
47
13 Height: 167.411
ami33 (#module = 33; #net = 123) 5 40
4
7 Area: 38282.3
0 15.19 7.20 0.0251 0 9 6
21 37 35 42 27 8

4 18.05 6.57 0.0248 0 14

Mini. Area: 35443
31 19 44
8 20.04 6.60 0.0252 0 22 25 23 Iterations: 66243
28
12 19.89 7.56 0.0252 0 20
43
DeadSpace: 7.41676%
24 18
14 25.63 7.26 0.0252 0 3
User Time: 37.98 sec
16 24.05 6.99 0.0252 0 11
1 Volate No: 0/16
ami49 (#module = 49; #net = 408) 2
0 32.45 6.15 1.932 0 10
32 26
4 34.69 6.29 1.934 0
8 36.90 7.37 1.957 0
12 38.63 7.75 1.962 0 Fig. 14. Modules 4, 5, 6, 7, 8 and 9 almost align horizontally. Modules 10,
16 39.53 7.48 1.957 0 11, 12 and 13 align vertically.
20 42.37 6.08 1.931 0
6
playout (#module = 62; #net = 1611) 5
50 47
4 31.33 7.21 0.0191 0 Width: 99.5175
10 36.18 6.61 0.0190 0 28
3844 37 32 35 49 12 Height: 96.4336
16 41.77 7.27 0.0191 0
51 39 25 40 4 24 33 31 46 Area: 9596.83
20 41.77 7.96 0.0193 0
58
24 45.95 8.35 0.0194 0 26 52 60 Mini. Area: 8855

random100 (#module = 100; #net = 1611) 59 43 34 16

Iterations: 66243

0 279.12 8.26 1.469 0 3 57

17 DeadSpace: 7.72993%
9
4 289.03 8.06 1.465 0 User Time: 43.69 sec
10 310.61 8.06 1.431 0 55 0 45 41
Volate No: 0/16
1 10
16 325.51 7.41 1.466 0 15 30
21 54 13
22 357.39 7.98 1.467 0 11
2 14
42

28 374.71 6.92 1.448 0 36 19

20
48
TABLE I 18 23
29 7 27
8 56
R ESULTS FOR AMI 33, AMI 49, PLAYOUT AND RANDOM 100. 22
61
53

Fig. 15. Module 24 is placed at  and modules 24, 25, 31, 33, 39,
40, 46 and 51 align horizontally.
Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(7):712–731, 2000.
[2] F. Balasa, S. C. Maruvada, and K. Krishnamoorthy. Efficient Solution
Space Exploration Based on Segment Trees in Analog Placement with Based on Corner Block List. IEEE Asia and South Pacific Design
Symmetry Constraints. Proceedings of the International Conference on Automation Conference, pages 509–514, 2001.
Computer-Aided Design, pages 497–502, 2002. [8] H. Murata, K. Fujiyoushi, and M. Kaneko. VLSI/PCB Placement
[3] Y. C. Chang, Y. W. Chang, G. M. Wu, and S. W. Wu. B*-Trees: A with Obstacles Based on Sequence-Pair. International Symposium on
New Representation for Non-Slicing Floorplans. Proceedings of the Physical Design, pages 26–31, 1997.
37th ACM/IEEE Design Automation Conference, 2000. [9] H. Murata, K. Fujiyoushi, S. Nakatake, and Y. Kajitani. Rectangle-
[4] K. Fujiyoshi and H. Murata. Arbitrary Convex and Concave Rectilinear Packing-Based Module Placement. Proceedings IEEE International
Block Packing Using Sequence-Pair. International Symposium on Conference on Computer-Aided Design, pages 472–479, 1995.
Physical Design, pages 103–110, 1999. [10] Xiaoping Tang and D. F. Wong. Floorplanning with Alignment and
[5] Jianbang Lai, Ming-Shiun Lin, Ting-Chi Wong, and Li-C. Wang. Performance Constraints. Proceedings of the 39th ACM/IEEE Design
Module Placement with Boundary Constraints Using the Sequence- Automation Conference, pages 848–853, 2002.
Pair Representation. IEEE Asia and South Pacific Design Automation [11] Thomas H. Cormen and Charles E. Leiserson and Ronald L. Rivest.
Conference, pages 515–520, 2001. Introduction to Algorithms. McGraw Hill, eighth edition, 1992.
[6] Y-Z. Liao and C. K. Wong. An Algorithm to Compact a VLSI Symbolic [12] F. Y. Young and D. F. Wong. Slicing Floorplans with Pre-placed
Layout with Mixed Constraints. IEEE Transactions on Computer-Aided Modules. Proceedings IEEE International Conference on Computer-
Design of Integrated Circuits and Systems, 2(2):62–69, 1983. Aided Design, pages 252–258, 1998.
[7] Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan [13] F. Y. Young and D. F. Wong. Slicing Floorplans with Range Constraints.
Cheng, and Jun Gu. VLSI Floorplanning with Boundary Constraints International Symposium on Physical Design, pages 97–102, 1999.
IEEE TRANSACTIONS ON VLSI SYSTEMS, 2004 11

5 26 46 Runtime (sec)
8 47
4 0 Width: 192.188
ami33
15 36 400
43 ami49
14 28 Height: 196.244
24 playout
40 380
Area: 37715.7 random100
39 48 360
23 41 27 37
Mini. Area: 35443
340
Iterations: 66243 320
1 11 32 42 7 38
DeadSpace: 6.02585% 300
6
25 User Time: 48.1 sec 280
12 260
31 Volate No: 0/16
29 13 45 240
16 3
22 220
33 44 19
17 200
18
34 180
2 160
20 21 35
10 30 9
140
120

Fig. 16. A resultant packing of the data set ami49-bc1 from [14] in which 100
module 6, 18, 20 and 23 are required to be on the left, module 17, 36, 45 80
and 48 on the right, module 0, 4, 8 and 47 at the top, and module 2, 9, 10 60
and 30 at the bottom. The deadspace obtained in [14] was 1.51%.
40
20
21 26
22 32 9 0
16 No. of
Width: 125.586 Constraints
Height: 102.638
0 5 10 15 20 25 30
15
25 13 10
20 8 Area: 12889.9
Fig. 18. The relationship between runtime and the number of placement
Mini. Area: 11563.3 constraints.
14 19
23 12 11
Iterations: 66242
24
17 Deadspace: 10.2917%
4 18 7 6 27 User Time: 14.6 sec Chris Chu received the B.S. degree in computer
28
5
30 Violate No: 1/2
science from the University of Hong Kong, Hong
29 Kong, in 1993. He received the M.S. degree and
the Ph.D. degree in computer science from the
PLACE University of Texas at Austin in 1994 and 1999,
0 1 31 2 3
PHOTO respectively.
HERE Dr. Chu is currently an Assistant Professor in the
Electrical and Computer Engineering Department at
Iowa State University. His research interests include
Fig. 17. An input set of infeasible constraints that requires module 5 to be
design and analysis of algorithms, CAD of VLSI
placed along the left boundary, and on the right hand side module 4 at the
physical design, and performance-driven intercon-
same time.
nect optimization. He received the IEEE TCAD best paper award at 1999 for
his work in performance-driven interconnect optimization. He also received
the Bert Kay Best Dissertation Award for 1998-1999 from the Department of
[14] F. Y. Young, D. F. Wong, and Hannah H. Yang. Slicing Floorplans with Computer Sciences in the University of Texas at Austin.
Boundary Constraints. IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, 18(9):1385–1389, 1999. Also appeared
in ASP-DAC 1999.

M.L. Ho received his B.Sc. and M.Phil. degree from

Evangeline Young received her B.Sc. degree and the Computer Science and Engineering Department
M.Phil. degree in Computer Science from the Chi- in the Chinese University of Hong Kong in 2001
nese University of Hong Kong (CUHK). She re- and 2003, respectively. He is currently working in
ceived her Ph.D. degree from the University of Texas PLACE ThizLinux Laboratory Limited.
PLACE at Austin in 1999. Currently, she is an Assistant PHOTO
PHOTO Professor in the Department of Computer Science HERE
HERE and Engineering in CUHK. Her research interests
include algorithms and CAD of VLSI circuits. She
is now working actively on floorplan design opti-
mization, circuit partitioning, circuit retiming and
packing representation.