10/17/19

Memories & More

•Overview of Memories
•Memories on the FPGA
•Memories in Verilog
•External Memories
•Flash
•DRAM

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CRC and FEC

Nice little routing line

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Pipelining Thing:

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Closer Look

12ns

4ns

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Closer Look

~4ns

~8ns

4ns

• Bottom is a SumàComparisonàSelect/Assign
• deltax stuff is SumàComparisonàSelect/Assign
• I’d expect them to both be ~4 ns since it says the original
blob stuff was 4ns

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One Possible Solution

~4ns

12ns

Some module

deltax,y
comb comb
register
tpd~4ns tpd~12

clk

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Another Possible Solution

~4ns

~12ns

Some module

comb deltax,y comb pixel

tpd~4ns register tpd~12 register

clk clk

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Another Possible Solution

~4ns

~4ns

~8ns

Some module

comb x,ysquared comb

tpd~12ns register tpd~4ns

clk

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Another Possible Solution

~4ns

~8ns

~4ns

Some module

x,ysquared
comb comb pixel
register
tpd~12ns tpd~4ns register

clk clk

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Why add two registers to module

when one will do?
• The less output combinational logic you have the more
reliable your modules will play together (tclk~15ns

Some module Some other module

comb comb comb comb

register register
tpd=9 tpd=7 tpd=11 tpd=6

• ”Legal” on their own…but what happens when they

have to work together?
• Back-to-back propagation delays that will violate our
setup/hold contract
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Where to add extra registers?

• If you used
two
registers for
round puck:

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Memory

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Memories: a practical primer

• The good news: huge selection of technologies
• Small & faster vs. large & slower
• Every year capacities go up and prices go down
• Almost cost competitive with hard disks: high density, fast flash
memories
• Non-volatile, read/write, no moving parts! (robust, efficient)
• The bad news: perennial system bottleneck
• Latencies (access time) haven’t kept pace with cycle times
• Often a separate technology from logic, so must communicate
between silicon, so physical limitations (# of pins, R’s and C’s and
L’s) limit bandwidths
• New hopes: capacitive interconnect, 3D IC’s, FRAMs, etc…
• Likely one of the limiting factor in cost & performance of many
digital systems: designers spend a lot of time figuring out how to
keep memories running at peak bandwidth

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How do we Electrically Remember

Things?
• We can convey/transfer information with voltages
that change over time
• How can we store information in an electrically
accessible manner?
• Same exact deal as with energy…
• Store in either:
• Electric Field
• Magnetic Field

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Mostly focus on rewritable

• Punched Cards have
existed as
electromechanical
program storage since
~1800s
• We’re mostly
concerned with
rewritable storage
mechanisms today
Computer program in punched card format
(cards were true
ROMs) https://en.wikipedia.org/wiki/Computer_programming_in_the_
punched_card_era

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Electronic Memories in History

http://www.computerhistory.org/timeline/memory-storage/

• Drum Memory:
• Information stored magnetically on large rotating
metallic cylinder
• Could read/write to it
• Did not require periodic refresh

• Non-volatile (last after power cycles off)

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Delay Line Memory

• Early form of FIFO memory (talk
about later)
• Generate a wave pattern which
exists for a few milliseconds in
mercury
• Recover on the other end and
either reload or use
• Requires refresh circuitry
• Volatile (info lost soon after
power cut)
https://matsuuratomoya.com/en/works/post-past_sotsuten/
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William’s Tube
• Take advantage of non-negligible decay
time of phosphors on CRT to store data
• Project data image
• Little bit later (milliseconds) recover it .
• Either use it or re-project it for later use
• Requires periodic refresh

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Core Memory
• MIT!
• Store 1’s and 0’s in the
magnetic field of small
torroids (magnetic cores)
• Where the term “core
dump” comes from.
• Used up until mid 70’s https://en.wikipedia.org/wiki/Magnetic-
core_memory#/media/File:KL_Kernspeicher_
• Few on display in fourth Makro_1.jpg
floor of 38
• Non volatile!
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Memory Classification & Metrics

Read-Write
Memory Non-Volatile
Read-Only
Random Read-Write
Sequential Memory
Access Memory
Access

EPROM Mask-
SRAM
FIFO E2PROM Programmed
DRAM
FLASH ROM

Key Design Metrics:

1. Memory Density (number of bits/mm2) and Size
2. Access Time (time to read or write) and Throughput
3. Power Dissipation

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Nexys4 DDR Memory

• Regular registers in logic blocks
• Operates at system clock speed, expensive (CLB utilization)
• Configuration set by Verilog design (eg FIFO, single/dual port, etc)

• FPGA Distributed memory

Inside • Operates at system clock speed
the • Uses LUTs (64 bits) for implementation, expensive (CLB utilization)
FPGA • Requires significant routing for implementation
• Configured using IP
• Theoretical maximum: ~1Mbit
• FPGA Block RAM:
• 4,860K bits total (in 135/270 chunks)

• DDR2 SDRAM
• 128MiB (Megabytes)
Outside • Requires MIG (Memory Interface Generator) Wizard

the • Flash memory

FPGA • 16MiB
• Slow read access, even slower write access time!
• microSD port
• Tested with 2GB (Windows 7, FPGA)

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Memory ON the FPGA

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FPGA Memory: Two Types

• The FPGA has two (technically three) dedicated sets
of resources for storing information. Both are
comprised of SRAM (Static Random-Access
Memory)

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Static RAM (SRAM) Cell (The 6-T Cell)

!" !"

Write: Set BL, BL to (0,VDD ) or (VDD,0)

then enable WL (= VDD)

Read: Disconnect drivers from BL and BL, then

enable WL (=VDD). Sense a small change in BL or
BL
§ State held by cross-coupled inverters (M1-M4)
§ Retains state as long as power supply turned on
§ Feedback must be overdriven to write into the memory

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FPGA Memory: Two Types

• The SRAM in our FPGA (Xilinx 7A100T) is organized
into two types (meant for using as memory
explicitely):
• Block RAM (BRAM):
• Large continuous chunks of SRAM
• 36 kbits a piece
• 135 of these on our particular FPGA
• Distributed RAM:
• Of the ~15,000 Logic Slices on the FPGA, about 5000
have 256 bits of SRAM in them
• Can use this spread-out RAM as well (to squeeze
another ~150 KBytes out of chip…but this takes away
resources from your logic so you should use as last
resort!

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Block Memories (BRAMs) There’s 135 of these 36Kx1 bit

SRAM arrays

• Our FPGA has 135

dual-port SRAM
modules
• Can write-to and
lookup values using
these two ports as
needed

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BRAM Timing

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BRAM Operation Similar to what we did earlier with SRAM (BRAM

is just a Block of SRAM on the FPGA)
Data_in Data_out
BRAM
Address
Single-port
WE Config.
CLK

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Distributed RAM: Each Logic Cell is

made of Four Six-Input Lookup Tables
with inputs that can be set
• Can synthesize any six-input SRAM
63
lookup-table/function/Karnaugh
Map

…
Out
• Can alternatively use this SRAM SRAM
1
for other purposes!
0
SRAM

I0
I1
I2
I3
I4
I5

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Working with SRAM

• In order to use these two resources (BRAM and
Distributed RAM), need to understand how Verilog
and Vivado figure out what to do
• It is not simple.
• Usage in Verilog can guide Vivado in terms of what
resources to use
• IP/primitives can guide the software more so we
use resources we want

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FPGA Memories Declare or

Instantiate?
• Verilog/Vivado can infer memory resource
utilization depending on syntax and use cases
• For more explicit control, you can also create
instances of primitives included with Xilinx-core IP
that give you additional control
• Details here:
• https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug953-vivado-
7series-libraries.pdf

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Memories in Verilog
• logic bit; // a single register
• logic [31:0] word; // a 32-bit register
• logic [31:0] array[15:0]; // 16 32-bit

• logic [31:0] array_2d[31:0][15:0];

// 2 dimensional 32-bit array

• logic [31:0] read_data,write_data;

logic [3:0] index;
// combinational (async) read
assign read_data = array[index];
// clocked (synchronous) write
always_ff @(posedge clock)
array[index] <= write_data;

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Multi-port Memories (aka register files)

logic [31:0] regfile[30:0]; // 31 32-bit words

// Beta register file: 2 read ports, 1 write

logic [4:0] ra1,ra2,wa;
logic [31:0] rd1,rd2,wd;

assign ra1 = inst[20:16];

assign ra2 = ra2sel ? inst[25:21] : inst[15:11];
assign wa = wasel ? 5'd30 : inst[25:21];

// read ports
assign rd1 = (ra1 == 5’d31) ? 32’d0 : regfile[ra1];
assign rd2 = (ra2 == 5’d31) ? 32’d0 : regfile[ra2];
// write port
always_ff @(posedge clk)
if (werf) regfile[wa] <= wd;

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Let’s make a RAM

• I want something where I can store and randomly
access data
• Let’s use BRAM!

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Using BRAMs (example: a 64Kx8 RAM)

• From menus: IP Catalog à Block Memory Generator

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BRAM Example
Each entry is 8 bits

I want 64000 entries

Uncheck for one less latency cycle

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BRAM Example
• If making a
ROM or if we
want RAM to
start with
something can
load init file

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.coe file format

memory_initialization_radix=2;
memory_initialization_vector=

00000000,
00111110,
01100011, Memory contents with location 0 first, then location
00000011, 1, etc. You can specify input radix, in this example
00000011, we’re using binary. MSB is on the left, LSB on the
right. Unspecified locations (if memory has more
00011110, locations than given in .coe file) are set to 0.
00000011,
00000011,
01100011,
00111110,
00000000,
00000000,
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BRAM Example
• How much will this thing
use?
• To store 64Kbits, we’d
need 2 36K BRAMs
• To store 64KBytes, we’d
need 8 times as many
• So 16 36K BRAMs!

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Using result in your Verilog

• To call this module in our Verilog just do this:

Write enable

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There’s the Usage!

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RAM Uses
• Store Audio (Lab 5a)
• Set up a Dual port BRAM and use this as a frame
buffer for video:
• Write pixels in as they come in/read them out as you
need them
• Store anything you want! (exciting)

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FIFO (First-In-First-Out)
• Basically a Queue like you see in Python or
something, but we can’t dynamically allocate storage
space ahead of time at our low level!

FIFO DOUT
DIN SRAM

• Data is not randomly accessed, but instead is

accessed in the order it was provided
• Can generate either using Dist RAM or BRAM
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FIFO Implemented with BRAM:

• Remember structure of
BRAM:
• Dual Port allows us to
simultaneously read and
write to different SRAM
cells
• Add some logic around it
to store and
autoincrement the
memory addresses and
you’ve got a FIFO

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FIFO
• From menus: IP Catalog à FIFO Generator

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FIFO

• This FIFO can store can store up to 1024 18 bit values

in order!

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Where to Use FIFOs?

• Anytime you have two modules sharing data (one
providing data to another) and they may be
producing/consuming in differing patterns

FIFO
DIN SRAM DOUT
Some Some
module module

Generates data in 100 sample

bursts at 100 MHz once every Consumes data one sample at a
second time at 10 MHz
FIFO needs to be big
enough to hold all that
could pile up!
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More Reading
• Resource utilization on an FPGA is not easy nor simple (but is really
cool). Some resources:
• Series 7 Memory Resources:
• https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf

• Series 7 Configurable Logic Blocks Resources:

• https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf

• Series 7 Libraries Docs (How to build almost anything):

• https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug953-vivado-7series-libraries.pdf

• Good paper on What Gets Inferred from Verilog:

• https://www.xilinx.com/support/documentation/white_papers/wp231.pdf

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Memory OFF the FPGA

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Memory Array’s (Inspiration in Switches)

• If you have 16 switches,
you can convey that
using 16 independent
wires (one-hot encoding)
• Alternatively if you
assemble in an
array/matrix, you can do With correct interfacing you can still
with 8 wires (if you add think of this as a 16X1 array of
switches!!! Even though it isn’t
some interfacing
circuitry)
• Same situation in memory

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Memory Array Architecture

(SRAM, Flash, DRAM)
2LxM memory Small cells ® small mosfets ® small dV on bit line

L-K Bit Line

2
Storage Cell

Row Decode
AK
A K+1 Word Line 2L-K row
by
Mx2K column
A L-1 cell array

M*2K

Sense Amps/Driver Amplify swing to

rail-to-rail amplitude

A0
Column Decode
A K-1 Selects appropriate word
(i.e., multiplexer)
Input-Output
(M bits)

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Two-ish Major Options

• Flash/EEPROM:
• Many different form factors, very slow to read/write, but
non-volatile, meaning it will last beyond power cycles
• Dynamic Random Access Memory (DRAM):
• Potentially very high read-write rates
• Needs to be constantly refreshed (dynamic)
• Volatile…~100 ms after poweroff, memory lost

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EPROM Families
• Includes EPROM, EEPROM, Flash
memory, (and SSDs)
• Utilize Floating Gates
• Different from SRAM!
• Instead of ~6 transistors per bit,
you can do about 1!
• Acts sorta like SRAM from
outside but Non-Volatile and
writes are much slower than An early EPROM.
reads You’d program electrically and
then shine UV onto it to erase
• Invented by Dov Frohman while it…don’t use these anymore
at Intel ~1970ish
10/16/19 6.111 Fall 2019 53

Quick Review on MOSFETs

In sub-threshold mode:
!# -
!#$
(#$ = * !"$ − !, !#$ −
2
!" %&' Above Threshold (saturation)
(#$ = * !"$ − !, -

!$

• Basically:
• If VG is > VT you conduct (are ”on”)
• If VG is < VT you do not conduct (are ”off”)
• Traditionally VT is a function of doping,
transistor dimensions, etc…
• BUT!....
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Floating GATE
Floating Gate MOSFETs GATE

!#

!" %&'

!$
Drain 10 nm Flash Gate Source
Presence or absence of carriers on floating gate affects the threshold
voltage of MOSFET
• Default (“binary 1”)…Threshold voltage is lower VTL
• (no electrons trapped in gate)
• Programmed bit (”binary 0”)…threshold voltage is higher VTH
• (electrons trapped in gate)
https://www.electronicsweekly.com/news/research-news/device-rd/iedm-hybrid-floating-gate-scales-flash-to-10nm-2012-12/
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Hot Carrier Injection/Tunneling to

Program/Reprogram
• To add or remove electrons to the floating gate you use
a quantum tunneling phenomenon
• High voltage (~12V over 100’s of Angstroms) is used to
force electrons to tunnel into floating gate… the term
“hot” refers to high energies on electrons.
• A similar process is used in reverse to tunnel them out
again
• This is a potentially destructive process and will
eventually destroy the device. Flash therefore has
limits of ~ several 100,000’s of program/erase cycles
• Mitigate issues by wear-leveling (try to spread out
usage across all of device…like rotating tires on a car)
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1 on the select bits means voltage:

NOR Flash • greater than VTL (low threshold from no trapped carriers)
• less than VTH (high threshold from trapped carriers)

Bit Line

S0 S1 S2 S3

Like a NOR gate since

when all bits are 1,
S0 S1 S2 S3 Out bit line goes low if
any input is turned
0 0 0 0 1 high…hence called
NOR Flash
1 0 0 0 0 if B0==1, 1 if B0==0

0 1 0 0 0 if B1==1, 1 if B1==0

0 0 1 0 0 if B2==1, 1 if B2==0

0 0 0 1 0 if B3==1, 1 if B3==0

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NAND Flash Like a NAND gate since

when all bits are 1, bit line
goes low if tested input is
Bit Line
also 1…hence called
NAND Flash
S0
S0 S1 S2 S3 Out

>VTH >VTH >VTH >VTH 0

S1
VTL<V<VTH >VTH >VTH >VTH 0 if B0==1, 1 if B0==0

>VTH VTL<V<VTH >VTH >VTH 0 if B1==1, 1 if B1==0

S2
>VTH >VTH VTL<V<VTH >VTH 0 if B2==1, 1 if B2==0

>VTH >VTH >VTH VTL<V<VTH 0 if B3==1, 1 if B3==0

S3

Turn word_select HI to enable whole word

word_select

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NAND vs. NOR Flash?

• Have Pros cons related to r/w time, size, etc.

https://www.semanticscholar.org/paper/White-Paper-Two-Flash-Technologies-Compared-%3A-NOR-
Tal/52f7d974a7be1911b33cb64c26ba4d7f5b337d9e/figure/0
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Interacting with Flash and (E)EPROM

• Reading from flash or (E)EPROM is the same as reading from SRAM
• Vpp: input for programming voltage (12V)
• EPROM: Vpp is supplied by programming machine
• Modern flash/EEPROM devices generate 12V using an on-chip charge pump
• EPROM lacks a write enable (unless you work for missile defense, you’ll not interact with
EPROM)
• Not in-system programmable (must use a special programming machine)
• For flash and EEPROM, write sequence is controlled by an internal FSM
• Writes to device are used to send signals to the FSM
• Although the same signals are used, one can’t write to flash/EEPROM in the same manner as SRAM
Flash/EEPROM block diagram Vcc (5V)

Address Data
Charge
Chip Enable pump
EPROM omits
Output Enable Programming FSM, charge
voltage (12V)
FSM pump, and write
Write Enable
enable

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Using Flash with Nexys 4 DDR Board

• You can use the 16MBits of Quad-SPI Flash to
permanently “program” the board
• About 75% is unused with full binary so you could
use this for permanent storage (I never had, but it
is doable)
• Can also interface directly to a 2 GB SD card (which
is itself Flash)

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Floating Gates
• Some neat recent work using floating gates and
their adjustable threshold capabilities
• Result is ability to adjust/teach a single transistor
when to fire based on input signals!

Floating Gate neural-like implementations,

2017
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DRAM
• Dynamic Random Access Memory!
• Single transistor and capacitor per bit (capacitor
does the storage)
• Capacitors decay rather quickly (especially since
DRAM capacitors are about 10 femtoFarads) so
need to be refreshed
• Can be made extremely dense and therefore
economical
• Are fast-ish:
• SRAM will have access time of down to 10ns or less
• DRAM will have access time from 50-150ns
• EEPROM/Flash way slower (esp for writes)

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Dynamic RAM (DRAM) Cell

WL BL Write "1" Read "1"
WL DRAM uses
Special
M1 CS X Capacitor
GND
Structures
VDD
BL
VDD/2 VDD /2
CBL sensing
Cell Plate Si
[Rabaey03]
Capacitor Insulator
Refilling Poly
To Write: set Bit Line (BL) to 0 or VDD Storage Node Poly
& enable Word Line (WL) (i.e., set to VDD ) Si Substrate
2nd Field Oxide
To Read: set Bit Line (BL) to VDD /2
& enable Word Line (i.e., set it to VDD )

§ DRAM relies on charge stored in a capacitor to hold state

§ Found in all high density memories (one bit/transistor)
§ Must be “refreshed” or state will be lost – high overhead
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DRAM Memory and Controller

• Reading is destructive!
• Data stored on small capacitor
• To read it we must bleed the
capacitor off
• Therefore need to refresh
• Need to refresh even when not
reading (every 100 ms)

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Asynchronous DRAM

1. Column lines start charged

to mid-voltage (RAS=1)

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Asynchronous DRAM

1. Connect to sense amplifiers

2. Select Row
3. Discharge caps onto column
lines
4. Sense voltage dips or rises for
1’s and 0’s
5. Use positive feedback to charge
bit lines up to true 1 or 0
6. Cache remembered 1’s and 0’s

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Asynchronous DRAM

1. Read/Write by adjusting some

input/output selector
(associated with MUX signal)

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Asynchronous DRAM

1. Select which Column to route

out

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Asynchronous DRAM

1. Route out desired biats

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Asynchronous DRAM

1. Back to beginning (just about).

Need to recharge lines

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DRAM Cells are Staggered

Physically
• The sense amplifiers
use two parallel bit
lines (one active and
one for reference) to
detect the slight
perturbation when
you discharge the
capacitor

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Asynchronous DRAM Operation

Address Row Col

RAS

CAS

(Tristate)
Data Q (data from RAM)

WE set high/low before

asserting CAS

RAS-before-CAS CAS-before-RAS
for a read or write for a refresh
(Row and column addresses taken on
falling edges of RAS and CAS)

• Clever manipulation of RAS and CAS after reads/writes provide more efficient modes: early-
write, read-write, hidden-refresh, etc.
(See datasheets for details)

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READ PATTERN WRITE PATTERN

Even though we can run DRAM very fast, because of all the maintenance involved
in it (we have to clean up after ourselves every time we do something), there’s a
lot of downtime on the data bus. Compare that to the SRAM from earlier!

https://pubweb.eng.utah.edu/~cs7810/pres/dram-cs7810-protocolx2.pdf
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Many Flavors of DRAM

• DRAM (Asynchronous)
• SDRAM (Synchronous DRAM)
• (one clock cycle per operation)
• Single Data Rate SDRAM (SDR SDRAM):
• One R/W per clock Cycle
• Double-Data Rate SDRAM (DDR SDRAM)
• Two R/W per clock cycle (called double pumping)
• Faster Double-Data Rate SDRAM (DDR2 SDRAM)
• And DDR3 and DDR4

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Using DDR2 on Nexys 4 DDR

• There’s a “easy” way that Digilent (maker of the
board provides), but the data read/write time is
something awful like 200 ns
• The Memory Interface Generator (MIG) should
allow us to control it more reliably…Gim and I are
working on this now hopefully…but data rates
closer to 100 MHz should be obtainable using this
approach

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 10/17/19

Memory Devices: Helpful Knowledge

• SRAM vs. DRAM
• SRAM holds state as long as power supply is turned on. DRAM
must be “refreshed” – results in more complicated control
• DRAM has much higher density, but requires special capacitor
technology so usually separate chip since separate fab needed
• FPGA usually implemented in a standard digital process
technology and uses SRAM technology
• Non-Volatile Memory
• Fast Read, but very slow write (EPROM must be removed from the
system for programming!)
• Holds state even if the power supply is turned off
• Flash memory is slow, microsecond read, much longer writes
• Memory Internals
• Has quite a bit of analog circuits internally -- pay particular
attention to noise and PCB board integration
• Device details
• Don’t worry about them, wait until 6.012 or 6.374

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