Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers ECSE 434

PRELAB NOTES This lab is divided into two parts: the first part involves the design of an integrated differential pair, and the layout of the differential amplifier and output stage. The output stage does not need to be designed in the layout phase. However, it must be laid out with the differential amplifier, as it will later be designed to meet given specifications after the chip is fabricated. In the first part, the output stage will be tested with provided sample component values. The second part will include the completion of the output stage design, buffer stage, and the testing of the fabricated chip.

NOTES Get your equipment and components from the parts-master in the Trottier building. Ensure that the components you design for are available from the parts-master. It is suggested to assemble some of the circuit components prior to entering the laboratory to save time. Do not rely on the signal generator amplitude readouts, measure your inputs manually with the oscilloscope. When writing the report, make sure to include the following where possible: o hand calculations o simulation results Comparing both and an explanation of your observations in the discussion will help validate your experimental findings. Comment on plots you include.

Plagiarism will NOT be tolerated.

Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers Some post chip fabrication tips You will be forced to use very small input voltages in this experiment, because of the high gain of the differential amplifier. The following are suggestions to improve the quality of your results: If required, use a resistive voltage divider of known value between the signal generator and your Circuit Under Test (CUT), when very small input signals are needed. Otherwise you may find that the signal amplitude control of your signal generator is too coarse. This procedure will generate high noise levels so use it only if absolutely necessary. If the signal you are trying to measure is comparable in size to the external interference and to the internal noise of the oscilloscope (indicated by the thickness of the trace on the scope when set to its maximum sensitivity range), insert an op amp-based amplifier of known gain between the source and the oscilloscope. To reduce noise in the circuit, you may need to insert a lowpass LC pi-filter (Sedra and Smith section 12.5) between each power supply and the CUT. Do this only if it produces a noticeable improvement in the signal-to-noise ratio (SNR). Keep the connection between the output of the filter and the CUT as short as possible. Although potentiometers may be used to trim the operating conditions, for final testing they should be replaced by fixed resistors. This will eliminate many parasitic effects associated with potentiometers.

It is very important to compare your experimental results with your predictions (simulated and calculated) both in the lab and in your report. Plausible explanations must be given for the discrepancies and, where possible, should be supported by calculations and/or simulations.

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Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers 1 INTRODUCTION

Integration of analog circuitry is a crucial component in many cutting edge circuit designs nowadays. The small size of integrated circuits makes them a necessity in all portable applications. This experiment is aimed at the creation of an integrated analog amplifier. An input amplifying stage, a buffer interface stage and an output stage will be designed and interfaced in a feedback configuration to create a unity gain amplifier. The main objectives of this lab are hence to design and test some important building blocks used in analog IC amplifiers, and to become familiar with modern analog IC design techniques. You will design these circuits with the help of the CAD tool Electric, using the Gennum GA911 (1.5 micron) BJT technology, which is a transistor/resistor array. Your design will be fabricated and the resulting chip will be returned to you, packaged in a 20 pin DIP casing for testing. In particular, the circuit in Figure 2.1 is intended to study some important properties of differential amplifiers, current mirrors, passive and active loads, and to understand the relationship between bias and signal conditions. The circuit in Figure 3.1 investigates a Class AB output stage (details to be discussed later). These two circuits may be linked together via a simple interface circuit, resulting in a simple operational amplifier (op-amp) as shown on Figure 1.1. This may require the use of frequency compensation techniques to perform in a stable manner.
Differential gain stage Vin+ VinBuffer stage Ouput stage RLoad

Figure 1.1-Operational amplifier block diagram 2 DIFFERENTIAL AMPLIFIER

The circuit shown in Figure 2.1 is a modular differential amplifier to be implemented using a bipolar IC technology. In an op-amp, this is known as the main gain stage. The purpose of this circuit is to provide the bulk of the gain of the amplifier. Two interconnection schemes can be used once the chip is fabricated. If the off-chip interconnect scheme labeled alpha in Figure 2.1 is used, the structure is loaded with an active load, Q1 and Q2. On the other hand, if the off-chip interconnect beta scheme is used, the structure will be loaded with passive loads, Rpa and Rpb. Both loading schemes will be designed, and their advantages and disadvantages will be studied.

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Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers

Q1 Rpa VaDOff-chip interconnect beta Off-chip interconnect alpha

Q2 Rpb
Off-chip interconnect alpha

VaD+
Off-chip interconnect beta

VoutDQ3

VoutD+ Q4

VinD+

VinD-

R4 R1 VBias Q5 Q6

R5

VID

R2

R3

VEE

Represents one pin of the chip Figure 2.1- Differential amplifier with active/passive loads
...

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Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers Figure 2.2 shows both possible circuit configurations that can be achieved with the different possible wiring schemes.
VCC VCC

Q1 VaDVoutDVinD+ Q3 VoutD+

Q2 VaD+

Rpa VaDVoutDVoutD+

Rpb VaD+

Q4

VinD-

VinD+

Q3

Q4

VinD-

R4 R1 VBias Q5 Q6

R5 R1 VID VBias Q5

R4

R5

VID Q6

R2

R3

R2

R3

VEE

VEE

(a) (b) Figure 2.2- Two different possible amplifier configurations (a) with an active load (b) with a resistive load Table 2.1- Resistor components used Component Location Value R1 Off-chip R2 On-chip 2k R3 On-chip 2k R4 On-chip R5 On-chip Rpa Off-chip Rpb Off-chip

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Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers 2.1 2.1.1 2.1.2 2.1.3 2.1.4 PREPARATION Get familiar with Chapter 7 in Sedra and Smith (5th Edition). Considering this circuit will be used as a voltage gain stage in an operational amplifier, what are the main characteristics that it must have? What is the purpose of R2 and R3? Using VEE = -5V and VCC=5V 1 , design the current source of the differential pair so that it sinks a current of 0.25mA. Determine the required value of R1. Use the models provided on the course website for the GA911 technology. At the output, take into account the loading caused by the oscilloscope, which has a load resistance of 1M. Considering the current source only, plot the sources output current versus the output voltage and comment on the results. Design the circuit of Figure 2.2(a) in order to obtain a gain of 250V/V 10%. Determine the values of R4 and R5. Discuss. Design the circuit of Figure 2.2(b) in order to obtain a single ended gain of 12V/V 10%. Determine the values of Rpa and Rpb keeping the values of R4 and R5 unchanged. At the output (double-ended in this case), take into account the loading caused by the oscilloscope, which has a load resistance of 1M. Plot the voltage transfer characteristics of both circuits, and accompany both curves with the corresponding time domain waveform plot. Discuss the curve and maximal output swing. For both circuit setups, determine, if any, the input DC offset required to maximize the output swing. Document the maximum output swing. Discuss.

2.1.5 2.1.6 2.1.7

2.1.8

2.1.9

2.1.10 For both circuit setups, plot the differential mode frequency response and determine the 3-dB points. Ensure that each pin of the chip is modeled as a 5pF parasitic capacitor to ground. Also, take into account the parasitic resistor and capacitor values of the oscilloscope (1 M resistor in parallel considered before in parallel with a 20 pF capacitor). Discuss. 2.1.11 For both circuit setups, plot the common mode frequency response. Ensure that each pin of the chip is modeled as a 5pF parasitic capacitor to ground. Also, take into account the parasitic resistor and capacitor values of the oscilloscope (1 M resistor in parallel with a 20 pF capacitor). Discuss. 2.1.12 Find the input and output resistances of the two circuits. Discuss.
1

These power supply values will be used throughout the experiment.

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Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers 2.1.13 In summary, what are the advantages and limitations of both circuit setups? 2.1.14 Review the GA911 device layout of the standard 1x2 die (chip) supplied (check courses web page). Note the major features on the die. Locate the resistors, capacitors, diodes, NPN, PNP, and LNPN BJTs as well as the cross-unders and pads. Please study carefully the relation between the location of the different devices, and your required circuit layout (using a single layer of metallization). For example, layout symmetry between both halves of a differential amplifier should be carefully enforced in order to preserve a high degree of balance in that stage. Note the location of the substrate connections and observe device current and voltage ratings. The relation between the metal route width and its current carrying capacity should be noted and respected. This is especially important for traces where the currents will be higher, e.g. VCC, VEE and VoutAB. Failure to do so could result in a burnt out chip. 2.1.15 Layout the circuit using Electric. Make sure you are aware of which resistors are on-chip (hence part of the layout) or off-chip (to be connected later). Make sure to respect the design rules and specifications of the process. Remember to document your layout for discussion in the report. Validate the layout by comparing the extracted schematic 2 with your original schematic (with no parasitics), and making sure that the transient and frequency responses are identical.

Obtained using Electric schematic extraction.

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Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers 2.2 EXPERIMENT 3,4

For each of the differential setups perform the following in succession: 2.2.1 2.2.2 Connect your chip according to the setup you have determined when laying it out. Measure all DC voltages and infer the DC currents, where possible. As for all results in this experiment, compare with expected (simulations and calculations) values. Plot the voltage transfer characteristic of the circuit, and plot the output and input signals. Determine the optimal input DC offset that results in a maximum output swing. Measure the maximal output swing achieved. You may trim the bias current slightly if you deem it necessary. Plot the differential mode frequency response and find the 3-dB points. Use the 10X probe. Plot the common mode frequency response. Use the 10X probe. Determine the CMRR. Measure the differential input resistance and the output resistance. What must you be careful about when doing the input resistance measurements, compared to what was done in experiment 1? Can you suggest a practical method of measuring the common mode input resistance of the circuit?

2.2.3 2.2.4

2.2.5 2.2.6 2.2.7 2.2.8

2.2.9

3 4

To be started after the return of the fabricated chip. Ensure that you complete the experiment for both circuit topologies discussed in the preparation.

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Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers 3 CLASS AB OUTPUT STAGE

Note: For the initial chip submission, all you need to do is to include on-chip all the connections for the output stage (excluding all the resistors, which are off-chip). By the time the chips come back, you will be familiar with the design of this stage, and you will be required to show your own design and analysis. By that time, you will be able to follow the remaining part of this section. Therefore, complete parts 3.1.1 to 3.1.3, and then work on the remaining parts of this section when the chip returns from fabrication.
VCC

R6

VcAB RA VbAB RB VeAB Q7

Q9 Q11 LNPN VoutAB

Q10 Q12 LNPN

VinAB

Q8

VrAB R7

VEE

Figure 3.1-Class AB Output Stage The circuit shown in Figure 3.1 is a quasi-complementary (uses a compound PNP-NPN) Class AB output stage, which is designed to provide high currents to a small output load, while remaining linear for large input signals. It also features a built in gain that is provided by transistor Q8, and uses a VBE multiplier circuit to bias the output transistor pairs correctly.

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Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers Table 3.1- Resistor components used Component Location Value 5 R6 Off-chip R7 Off-chip RA Off-chip RB Off-chip If the VBE multiplier is shorted, the circuit becomes a Class B output stage, as shown in Figure 3.2.
VCC VCC

R6

Q9 Q11 LNPN

Q8 Q10 R7 Q12 LNPN

VEE

VEE

Figure 3.2-Modified (Class B) Output Stage

Designed for after chip fabrication.

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Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers VCC

Rbias1 Vin 1F Rbias2 Vout

VEE Figure 3.3-Input biasing network used for standalone output stage testing Figure 3.3 shows the biasing circuit you will need to use when testing the output stage as a standalone circuit. Other biasing approach will be used later when the circuit will be incorporated with the differential amplifier. 3.1 PREPARATION

Sections 3.1.1and 3.1.2 are necessary to test the circuit in Figure 3.1 and provide a validation for your layout before your final design. To do this, use the resistor values provided in Table 3.2. Remember that when the circuit is tested alone, the biasing stage in Figure 3.3 needs to be used. Make sure that this configuration provides a gain of 10V/V and can provide a 6Vp-p output to a 330 load. Do not use these values for the final design when the chip is fabricated. 3.1.1 Plot the frequency response of the circuit. Do not include parasitics.

3.1.2 Plot the voltage transfer characteristic, and then perform a transient analysis. Table 3.2- Sample resistor components to test output stage layout Component Value R6 R7 RA RB Rbias1 Rbias2 10k 820 32k 18k 100k 12.82k

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Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers 3.1.3 Layout the circuit shown in Figure 3.1 using Electric. Make sure all resistors are off-chip (to be connected later). Respect the design rules and specifications of the process. Remember to document your layout for discussion in the report. Validate the layout by comparing the transient and frequency responses of both the extracted schematic and the original schematic. Make sure that they are identical.

The following sections are to be completed after the appropriate material on output stages is covered/reviewed in class: 3.1.4 3.1.5 3.1.6 Get familiar with chapter 14 in Sedra and Smith (5th Edition). Considering this circuit will be used as an output stage in an operational amplifier, what are the main characteristics that it must have? Design the Class AB output stage circuit in Figure 3.1. Check that the following specifications are met: the quiescent current (zero input signal) is 0.5mA, and that the output stage is capable of supplying 6Vp-p to a 330 load without significant distortion, and the output stage provides a unloaded (disconnected load) gain of 10V/V. Remember that when the circuit is tested alone, the biasing stage in Figure 3.3 needs to be used. Similarly to 3.1.6, design the Class B output stage in Figure 3.2 to fulfill the following specifications: the output stage is capable of supplying 6Vp-p to a 330 load, and the output stage provides an unloaded gain of 10V/V. Use the same biasing arrangement as that of the Class AB setup. Determine the input resistance of both circuits. Comment on how it is different to a small-signal amplifier. Plot the frequency response of both circuits and comment. Remember to include 5pF parasitic capacitors to ground for each pin, and account for the parasitics of the oscilloscope.

3.1.7

3.1.8 3.1.9

3.1.10 Plot the voltage transfer characteristic of both circuits, and then perform a transient analysis of both designed circuits. Document the maximal output range. 3.1.11 Determine the projected size of the dead band zone of the Class B stage, and compare it to simulation results by looking at the voltage transfer characteristic plot. 3.1.12 In summary, what are the advantages and limitations of both circuit setups investigated? 3.1.13 What is the purpose of transistor Q12?

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Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers 3.1.14 What are the advantages and disadvantages of having an internal gain to the Class AB output stage, compared to having the bulk of the gain provided only by the differential pair? 3.2 EXPERIMENT

Note: To avoid damage, observe the maximum power ratings of the transistors and set the current limits on the DC supply accordingly. The load of any circuit must have the capacity to dissipate the maximum expected output power. Most resistors in the labs are rated at 250mW at 25C. You may have to combine several resistors in parallel to meet the power dissipation specifications for the load. You may observe high frequency oscillations in the output signal due to capacitive loading. These may be suppressed by inserting a small inductance in series with the load. For each of the Class B and Class AB output stage circuits, perform the following in succession with a 330 load: 3.2.1 3.2.2 Connect your chip according to the setup you have determined when laying it out. For the Class AB stage only, make note of the output DC offset with no input signal, and trim the resistors in the VBE multiplier to make the offset be as close to 0V as possible (within 10mV). Make sure to comment on the reasons of the discrepancy and why this correction is important both on the local output stage level, and then on the operational amplifier level. Measure all DC voltages and infer the DC currents where possible. As for all results in this experiment, compare with expected (simulations and calculations) values. Plot the transient response for a 6Vp-p output. Comment on the output and maximum output range. Plot the voltage transfer characteristic of the circuit. Plot the frequency response and find the 3-dB points. Use the 10X probe. Measure the input resistance of the circuit.

3.2.3

3.2.4 3.2.5 3.2.6 3.2.7

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Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers 4 BUFFER STAGE6

As shown in Figure 1.1, both circuits designed need to be interfaced for correct operation by some kind of an interface circuit, or buffer circuit. The purpose of this circuit is to ensure minimal loading of the gain stage and proper DC biasing of both stages. The latter is particularly important as the DC level of the gain stages output and the output stages input must be kept the same as when they were tested individually. In this section, you must design an off-chip transistor based circuit which will accomplish this function. Notice that, thanks to this circuit, the output stage will not require the input biasing circuit of Figure 3.3. Note: The active load amplifier and Class AB output stage will be used for the combination throughout the rest of the experiment.

To be completed after chip fabrication.

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Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers 4.1 4.1.1 PREPARATION Determine the design specifications of the circuit which you believe are required for proper operation of the operational amplifier. Be sure to have a logical reasoning as to why each specification you decide upon is required. Some common design specifications are: Bandwidth, gain, input resistance, output resistance, input DC insensitivity, input maximal swing, and output maximal swing. Based on the design specifications you have decided upon, create a circuit capable of meeting these specs and, if necessary, modify the specifications slightly if you deem them ultimately unattainable. Determine the component values and explain the functioning of your interface circuit. Provide a schematic of the design. Determine the input and output resistances of the circuit. Plot the time domain output of the circuit to an input which is comparable to the maximum expected differential amplifier output. Plot the frequency response of the circuit. Ensure that the parasitic capacitors are accounted for. Plot the voltage transfer curve of the circuit. Document the maximal output and input ranges. Comment of the advantages and disadvantages of your design. EXPERIMENT

4.1.2

4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.2

For this section, you can use a biasing network similar to Figure 3.3 to test the circuit standalone. 4.2.1 Measure all DC voltages and infer the DC currents where possible. As for all results in this experiment, compare with expected (simulations and calculations) values. Plot the time domain output of the circuit to an input which is comparable to the maximum expected differential amplifier output. Plot the voltage transfer characteristic of the circuit. Document the maximal output and input ranges. Plot the frequency response and find the 3-dB points. Use the 10X probe. Measure the output and input resistances of your circuit.

4.2.2 4.2.3 4.2.4 4.2.5

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Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers 5 OPERATIONAL AMPLIFIER7

In this section, the active load differential amplifier, the buffer stage and the Class AB output stage will be combined as shown in Figure 1.1 in order to yield an operational amplifier with an open-loop gain of around 2500V/V. Also, the amplifiers stability will be investigated, compensation will be performed if needed, and finally, the circuit will be used in a closed-loop feedback configuration. 5.1 5.1.1 5.1.2 PREPARATION Get familiar with Chapter 8 in Sedra and Smith (5th Edition). Combine the active load differential amplifier, buffer stage, and Class AB output stage together and load them with a 330 resistor. Ensure that the combination of the circuits yields the expected results from Spice simulations. Document the frequency response, gain, voltage transfer characteristic, and maximal input and output ranges. Make sure that the DC point at the output is 0V. Why is that critical in the context of feedback? Ensure that the parasitic capacitors are still accounted for. Determine the phase margin of the circuit. By examining the circuit diagram, determine where a compensating capacitor could be added to increase the phase margin of the circuit. You may use which ever compensating method you deem reasonable. Hint: Remember that, in its simplest form, compensating is equivalent to slowing down a circuits frequency response to increase its phase margin. If needed, compensate the circuit to yield a minimum phase margin of 25. Place the circuit in a unity gain feedback topology, as shown on Figure 5.1. Make sure you have correctly labeled the positive and negative ports of your circuit to ensure negative feedback is applied.

5.1.3 5.1.4

5.1.5 5.1.6

Vout Vin +

RLoad

Figure 5.1-Unity gain feedback amplifier

To be completed after chip fabrication.

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Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers 5.1.7 Load the circuit with a 330 resistor. Document the frequency response, voltage transfer characteristic, time response, and maximal input and output ranges. Hint: You may decouple the load with a capacitor if you have problems. Design a non-inverting feedback amplifier which provides a gain of 150V/V. Do not assume the open-loop gain to be infinite in this case, but use your measured open loop gain value. Provide a schematic of the design. Plot the frequency response, time response, and voltage transfer characteristic of this design. Comment on the effect of the feedback loop on the characteristics of the amplifier. Mainly, comment on the bandwidth, gain, and input resistance.

5.1.8

5.1.9

5.1.10 What are the advantages and disadvantages of feedback in this case? 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 EXPERIMENT Combine the circuits together and plot the frequency response using the 10X probe and find the 3-dB points. Plot a time response of the input and output. Plot the circuits voltage transfer characteristic. Measure the maximal input and output ranges of the circuit. Measure the input resistance of the circuit. Connect the circuit in unity gain configuration and repeat steps 5.2.1 to 5.2.5. Implement your non-inverting amplifier design and plot the time domain output corresponding to an input of your choosing. Plot the frequency response and voltage transfer characteristic of this circuit. Based on experimental results, comment on the performance of the circuit compared to the open-loop amplifier.

5.2.8

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