PCA9536

SCPS125H – APRIL 2006 – REVISED MARCH 2022

PCA9536 Remote 4-Bit I2C and SMBus I/O Expander with Configuration Registers

1 Features 3 Description
• Available in the Texas Instruments NanoFree™ This 4-bit I/O expander for the two-line bidirectional
Package bus (I2C) is designed for 2.3-V to 5.5-V VCC operation.
• Low standby current consumption of 1 μA Max It provides general-purpose remote I/O expansion for
• I2C to parallel port expander most microcontroller families through the I2C interface
• Operating power-supply voltage range of 2.3 V to [serial clock (SCL), serial data (SDA)].
5.5 V
The PCA9536 features 4-bit Configuration (input or
• 5-V Tolerant I/O ports
output selection), Input Port, Output Port, and Polarity
• 400-kHz fast I2C bus
Inversion (active high or active low) registers. At
• Input and output configuration register
power on, the I/Os are configured as inputs with a
• Polarity inversion register
weak pullup to VCC. However, the system controller
• Internal power-on reset
can enable the I/Os as either inputs or outputs by
• No glitch on power up
writing to the I/O configuration bits. If no signals are
• Power-up with all channels configured as inputs
applied externally to the PCA9536, the voltage level
• Noise filter on SCL/SDA inputs
is 1, or high, because of the internal pullup resistors.
• Latched outputs with high-current drive maximum
The data for each input or output is stored in the
capability for directly driving LEDs
corresponding Input Port or Output Port register. The
• Latch-up performance exceeds 100 mA per JESD
polarity of the Input Port register can be inverted
78, class II
with the Polarity Inversion register and the system
• ESD Protection exceeds JESD 22
controller reads all registers.
– 2000-V Human-body model (A114-A)
– 200-V Machine model (A115-A) The system controller resets the PCA9536 in the
– 1000-V Charged-device model (C101) event of a timeout or other improper operation by
utilizing the power-on reset feature, which puts the
2 Applications registers in their default state and initializes the I2C/
• Personal electronics SMBus state machine.
– Wearables The device outputs (latched) have high-current drive
– Mobile phones capability for directly driving LEDs, but has low current
– Gaming consoles consumption.
• Servers
• Routers Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
SOIC (8) 4.90 mm × 3.91 mm
PCA9536
VSSOP (8) 3.00 mm × 3.00 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

VCC Peripheral Devices

SDA P0
RESET, ENABLE, or
SCL P1 control inputs
I2C or SMBus Controller
INT or status outputs
(e.g. Processor) PCA9536 P2 LEDs
GND P3 Buttons

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.5 Programming............................................................ 13
2 Applications..................................................................... 1 8.6 Register Maps...........................................................15
3 Description.......................................................................1 9 Application Information Disclaimer............................. 19
4 Revision History.............................................................. 2 9.1 Application Information............................................. 19
5 Pin Configuration and Functions...................................3 9.2 Typical Application.................................................... 19
6 Specifications.................................................................. 4 10 Power Supply Recommendations..............................22
6.1 Absolute Maximum Ratings........................................ 4 10.1 Power-On Reset Errata...........................................22
6.2 ESD Ratings............................................................... 4 10.2 System Impact........................................................ 22
6.3 Recommended Operating Conditions.........................4 11 Layout........................................................................... 23
6.4 Thermal Information....................................................4 11.1 Layout Guidelines................................................... 23
6.5 Electrical Characteristics.............................................5 11.2 Layout Example...................................................... 23
6.6 I2C Interface Timing Requirements.............................6 12 Device and Documentation Support..........................24
6.7 Switching Characteristics............................................6 12.1 Documentation Support.......................................... 24
6.8 Typical Characteristics................................................ 7 12.2 Receiving Notification of Documentation Updates..24
7 Parameter Measurement Information.......................... 10 12.3 Support Resources................................................. 24
8 Detailed Description......................................................12 12.4 Trademarks............................................................. 24
8.1 Overview................................................................... 12 12.5 Electrostatic Discharge Caution..............................24
8.2 Functional Block Diagram......................................... 12 12.6 Glossary..................................................................24
8.3 Feature Description...................................................13 13 Mechanical, Packaging, and Orderable
8.4 Device Functional Modes..........................................13 Information.................................................................... 24

4 Revision History
Changes from Revision G (June 2014) to Revision H (March 2022) Page
• Changed all instances of legacy terminology to controller and target where I2C is mentioned..........................1
• Deleted the DSBGA (YZP) package information................................................................................................ 1
• Added the Simplified Schematic to the front page..............................................................................................1
• Removed packaging information from the Absolute Maximum Ratings table.................................................... 4
• Added Tstg to the Absolute Maximum Ratings table........................................................................................... 4
• Added the Thermal Information table................................................................................................................. 4
• Deleted VPOR from the Electrical Characteristics ...............................................................................................5
• Added VPORR and VPORF to the Electrical Characteristics ................................................................................. 5
• Changed the ICC stand by mode current max values for 5.5 V from 1 to 1.8 μA; 3.6 V from 0.9 to 1.2 μA; and
2.7 V from 0.8 to 1 μA in the Electrical Characteristics ......................................................................................5
• Changed the tvd(data) and tvd(ack) MAX values from: 1 μs to: 3.45 μs in the Standard Mode timing....................6
• Changed the ticr, tocf, and tocf MIN values in the Fast Mode timing.....................................................................6
• Added the Overview section............................................................................................................................. 12
• Added the Device Functional Modes section....................................................................................................13
• Added Detailed Design Procedure section....................................................................................................... 20
• Added Application Curves section.................................................................................................................... 21
• Added the Layout section................................................................................................................................. 23

Changes from Revision F (September 2008) to Revision G (June 2014) Page

• Added Power-On Reset Errata section.............................................................................................................22

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5 Pin Configuration and Functions

P0 1 8 VCC
P0 1 8 VCC
P1 2 7 SDA
P1 2 7 SDA
P2 3 6 SCL
P2 3 6 SCL
GND 4 5 P3
GND 4 5 P3
Not to scale

Figure 5-2. DGK Package, 8-Pin VSSOP,

Not to scale Top View
Figure 5-1. D Package, 8-Pin SOIC
(Top View)

Table 5-1. Pin Functions

PIN
I/O DESCRIPTION
NO. NAME
1 P0 I/O P-port input-output. Push-pull design structure
2 P1 I/O P-port input-output. Push-pull design structure
3 P2 I/O P-port input-output. Push-pull design structure
4 GND — Ground
5 P3 I/O P-port input-output. Push-pull design structure
6 SCL I/O Serial clock bus. Connect to VCC through a pullup resistor
7 SDA I/O Serial data bus. Connect to VCC through a pullup resistor
8 VCC — Supply voltage

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) See (1)
MIN MAX UNIT
VCC Supply voltage –0.5 6 V
VI Input voltage (2) –0.5 6 V
VO Output voltage (2) –0.5 6 V
IIK Input clamp current VI < 0 –20 mA
IOK Output clamp current VO < 0 –20 mA
IIOK Input/output clamp current VO < 0 or VO > VCC ±20 mA
IOL Continuous output low current VO = 0 to VCC 50 mA
IOH Continuous output high current VO = 0 to VCC –50 mA
Continuous current through GND –200
ICC mA
Continuous current through VCC 160
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

MIN MAX UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 0 2000
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all V
0 1000
pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage 2.3 5.5 V
SCL, SDA 0.7 × VCC 5.5
VIH High-level input voltage V
P3–P0 2 5.5
SCL, SDA –0.5 0.3 × VCC
VIL Low-level input voltage V
P3–P0 –0.5 0.8
IOH High-level output current P3–P0 –10 mA
IOL Low-level output current P3–P0 25 mA
TA Operating free-air temperature –40 85 °C

6.4 Thermal Information

D (SOIC) DGK (VSSOP)
THERMAL METRIC(1) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 141.9 183.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 82.6 76.9 °C/W
RθJB Junction-to-board thermal resistance 85.3 104.9 °C/W
ψJT Junction-to-top characterization parameter 32.3 18.7 °C/W
ψJB Junction-to-board characterization parameter 84.6 103.4 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT

VIK Input diode clamp voltage II = –18 mA 2.3 V to 5.5 V –1.2 0 V

VPORR Power-on reset voltage, VCC rising VI = VCC or GND, IO = 0 1.2 1.6 V
VPORF Power-on reset voltage, VCC falling VI = VCC or GND, IO = 0 0.75 1 V
2.3 V 1.8
3V 2.6
IOH = –8 mA
4.5 V 4.1

P-port high-level 4.75 V 4.1

VOH V
output voltage(2) 2.3 V 1.7
3V 2.5
IOH = –10 mA
4.5 V 4
4.75 V 4
SDA VOL = 0.4 V 2.3 V to 5.5 V 3 10
2.3 V 8 10
3V 8 14
VOL = 0.5 V
4.5 V 8 17
IOL 4.75 V 8 32 mA
P-port(3)
2.3 V 10 13
3V 10 19
VOL = 0.7 V
4.5 V 10 24
4.75 V 10 44
II SCL, SDA VI = VCC or GND 2.3 V to 5.5 V ±1 μA
IIH P-port VI = VCC 2.3 V to 5.5 V 1 μA
IIL P-port VI = GND 2.3 V to 5.5 V –100 μA
5.5 V 73 150
VI = VCC, IO = 0,
3.6 V 9 50
I/O = inputs, fscl = 400 kHz
2.7 V 7 30
Operating mode
5.5 V 14 25
VI = VCC, IO = 0,
3.6 V 9 20
I/O = inputs, fscl = 100 kHz
2.7 V 6 15
ICC μA
5.5 V 225 350
VI = GND, IO = 0,
3.6 V 175 250
I/O = inputs, fscl = 0 kHz
2.7 V 125 200
Standby mode
5.5 V 0.25 1.8
VI = VCC, IO = 0,
3.6 V 0.2 1.2
I/O = inputs, fscl = 0 kHz
2.7 V 0.1 1
One input at VCC – 0.6 V,
2.3 V to 5.5 V 0.35
Additional current in Other inputs at VCC or GND
ΔICC mA
standby mode Every LED I/O at VI = 4.3 V,
5.5 V 0.4
fscl = 0 kHz
Ci SCL VI = VCC or GND 2.3 V to 5.5 V 4 5 pF
SDA 5 6.5
Cio VIO = VCC or GND 2.3 V to 5.5 V pF
P-port 7.5 9.5

(1) All typical values are at nominal supply voltage (2.5-, 3.3-, or 5-V VCC) and TA = 25°C.
(2) The total current sourced by all I/Os must be limited to 85 mA.
(3) Each I/O must be limited externally to a maximum of 25 mA, and the P-port (P3–P0) must be limited to a maximum current of 100 mA.

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6.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
MIN MAX UNIT
Standard Mode
fscl I2C clock frequency 0 100 kHz
tsch I2C clock high time 4 μs
tscl I2C clock low time 4.7 μs
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 250 ns
tsdh I2C serial-data hold time 0 ns
ticr I2C input rise time 1000 ns
ticf I2C input fall time 300 ns
tocf I2C output fall time, 10-pF to 400-pF bus 300 ns
tbuf I2C bus free time between Stop and Start 4.7 μs
tsts I2C Start or repeated Start condition setup time 4.7 μs
tsth I2C Start or repeated Start condition hold time 4 μs
tsps I2C Stop condition setup time 4 μs
tvd(data) Valid data time, SCL low to SDA output valid 3.45 μs
tvd(ack) Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low 3.45 μs
Cb I2C bus capacitive load 400 pF
Fast Mode
fscl I2C clock frequency 0 400 kHz
tsch I2C clock high time 0.6 μs
tscl I2C clock low time 1.3 μs
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 100 ns
tsdh I2C serial-data hold time 0 ns
ticr I2C input rise time 20(1) 300 ns
20x(Vdd/5.5V)
ticf I2C input fall time (1) 300 ns

20x(Vdd/5.5V)
tocf I2C output fall time, 10-pF to 400-pF bus (1) 300 ns

tbuf I2C bus free time between Stop and Start 1.3 μs
tsts I2C Start or repeated Start condition setup time 0.6 μs
tsth I2C Start or repeated Start condition hold time 0.6 μs
tsps I2C Stop condition setup time 0.6 μs
tvd(data) Valid data time, SCL low to SDA output valid 0.9 μs
tvd(ack) Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low 0.9 μs
Cb I2C bus capacitive load 400 pF

(1) Cb = Total capacitive load of one bus in pF

6.7 Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-2)
FROM TO
PARAMETER MIN MAX UNIT
(INPUT) (OUTPUT)
STANDARD MODE and FAST MODE
tpv Output data valid SCL P3–P0 200 ns
tps Input data setup time P-port SCL 100 ns
tph Input data hold time P-port SCL 1 μs

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6.8 Typical Characteristics

TA = 25°C (unless otherwise noted)

55 300

50 VCC = 5 V
VCC = 5 V 250
45

ICC – Supply Current – nA

ICC – Supply Current – µA

40
f SCL = 400 kHz 200
35 VCC = 3.3 V
I/Os unloaded
30
150
25
VCC = 3.3 V
20 VCC = 2.5 V
100
15
VCC = 2.5 V
10 50
5 SCL = VCC
0 0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100

TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C

Figure 6-1. Supply Current vs Temperature Figure 6-2. Quiescent Supply Current vs Temperature

70 300
f SCL = 400 kHz VCC = 5 V
275
I/Os unloaded
60 250
ICC – Supply Current – µA 225
ICC – Supply Current – µA

50
200
TA = –40°C
175
40
150
TA = 25°C
30 125
100
20 75 TA = 85°C

50
10
25
0
0 0 1 2 3 4
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
Number of I/Os Held Low
VCC – Supply Voltage – V

Figure 6-4. Supply Current vs Number of I/Os Held Low

Figure 6-3. Supply Current vs Supply Voltage

300 300
VCC = 2.5 V, ISINK = 10 mA
275 275
VCC = 2.5 V, IOL = 10 mA
(V CC – V OH ) – Output High Voltage – mV

250 250
VOL – Output Low Voltage – mV

225 225
200 200
175 175
VCC = 5 V, ISINK = 10 mA
150 150
VCC = 5 V, IOL = 10 mA
125 125
100 100
75 VCC = 2.5 V, ISINK = 1 mA 75
50 VCC = 5 V, ISINK = 1 mA 50
25 25
0 0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C

Figure 6-5. I/O Output Low Voltage vs Temperature Figure 6-6. I/O Output High Voltage vs Temperature

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6.8 Typical Characteristics (continued)

TA = 25°C (unless otherwise noted)

30 40
VCC = 2.5 V VCC = 3.3 V
35
25
TA = –40°C
TA = –40°C
ISINK – I/O Sink Current – mA

ISINK – I/O Sink Current – mA

30
20 TA = 25°C
25
TA = 25°C
15 20

TA = 85°C 15
10
TA = 85°C
10
5
5

0 0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VOL – Output Low Voltage – V VOL – Output Low Voltage – V

Figure 6-7. I/O Sink Current vs Output Low Voltage Figure 6-8. I/O Sink Current vs Output Low Voltage

60 30
55 VCC = 5 V
VCC = 2.5 V
25
ISOURCE – I/O Source Current – mA
50
TA = –40°C
ISINK – I/O Sink Current – mA

45
TA = –40°C
40 20

35 TA = 25°C
TA = 25°C
30 15

25
TA = 85°C
20 10
TA = 85°C
15
10 5

5
0 0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

VOL – Output Low Voltage – V (VCC – VOH) – Output High Voltage – V

Figure 6-9. I/O Sink Current vs Output Low Voltage Figure 6-10. I/O Source Current vs Output High Voltage

45 70
VCC = 3.3 V 65 VCC = 5 V
40
TA = –40°C 60
ISOURCE – I/O Source Current – mA
ISOURCE – I/O Source Current – mA

35 55
50
30 45 TA = –40°C
TA = 25°C
25 40
35 TA = 25°C
20 30
25
15
20 TA = 85°C
10 15
TA = 85°C
10
5
5
0 0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

(VCC – VOH) – Output High Voltage – V (VCC – VOH) – Output High Voltage – V

Figure 6-11. I/O Source Current vs Output High Voltage Figure 6-12. I/O Source Current vs Output High Voltage

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6.8 Typical Characteristics (continued)

TA = 25°C (unless otherwise noted)

TA = 25°C
5

VOH – Output High Voltage – V

4

IOH = –8 mA
3

2 IOH = –10 mA

0
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

VCC – Supply Voltage – V

Figure 6-13. Output High Voltage vs Supply Voltage

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7 Parameter Measurement Information

VCC

RL = 1 NŸ

SDA
DUT

CL = 50 pF
(see Note A)

SDA LOAD CONFIGURATION

Three Bytes for Complete

Device Programming

Stop Start Address R/W Data Data Stop

Address Address ACK
Condition Condition Bit 7 Bit 0 Bit 7 Bit 0 Condition
Bit 6 Bit 1 (A)
(P) (S) (MSB) (LSB) (MSB) (LSB) (P)

tscl tsch

0.7 x VCC
SCL
0.3 x VCC

ticr tPHL tsts

tbuf ticf
tsp tPLH
0.7 x VCC
SDA
0.3 x VCC

tsdh
ticf tsds tsps

Start or Repeat
Repeat Start Stop
Start Condition Condition
Condition
VOLTAGE WAVEFORMS

A. CL include probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.

Figure 7-1. I2C Interface Load Circuit and Voltage Waveforms

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Pn 500

DUT 2 x VCC

CL = 50 pF
500
(see Note A)

P-PORT LOAD CONFIGURATION

0.7 x VCC
SCL
P0 A P3
0.3 x VCC

Target
ACK

SDA

tpv
(see Note B)

Last Stable Bit

Unstable Data

WRITE MODE (R/W = 0)

0.7 x VCC
SCL P0 A P3
0.3 x VCC
tph
tps
0.7 x VCC
Pn 0.3 x VCC

READ MODE (R/W = 1)

A. CL include probe and jig capacitance.

B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

Figure 7-2. P-Port Load Circuit and Voltage Waveforms

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8 Detailed Description
8.1 Overview
The PCA9536 device is a 4-bit I/O expander for the I2C bus and is designed for 1.65-V to 5.5-V VCC operation. It
provides general-purpose remote I/O expansion for most microcontroller families through the I2C interface.
The PCA9536 consists of a configuration (input or output selection), Input Port, Output Port, and Polarity
Inversion (active-high or active-low operation) registers. At power-on, the I/Os are configured as inputs. The
system controller enables the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The
data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port
register can be inverted with the Polarity Inversion register and the system controller reads all registers.
The device outputs (latched) have high-current drive capability for directly driving LEDs.
8.2 Functional Block Diagram

6
SCL
Input I2C Bus Shift 4 Bits I/O P3-P0
7 Filter Control Register Port
SDA

Write Pulse

Read Pulse
8 Power-On
VCC
Reset

4
GND

Figure 8-1. Logic Diagram

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Data From Output Port

Shift Register Register Data
Configuration
Register VCC
Data From Q1
Shift Register D Q
FF
100 NŸ
Write Configuration D Q
CK Q
Pulse FF
Write Pulse P0 to P3
CK Q
Q2 ESD Protection
Output Port Diode
Register
Input Port GND
Register
D Q Input Port
Register Data
FF
Read Pulse CK Q

Data From Shift Polarity

D Q Register Data
Register
FF
Write Polarity CK Q
Pulse
Polarity Inversion
Register

Figure 8-2. Simplified Schematic Of P0 To P3

8.3 Feature Description

8.3.1 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 (in Figure 8-2) are off, creating a high-impedance input
with a weak pullup (100 kΩ typical) to VCC. The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register.
In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
8.4 Device Functional Modes
8.4.1 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9536 in a reset condition until
VCC has reached VPOR. At that time, the reset condition is released and the PCA9536 registers and I2C/SMBus
state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to
the operating voltage for a power-reset cycle.
Refer to the Section 10.1 section.
8.4.2 Powered-Up
When power has been applied to VCC above VPORR, and the POR has taken place, the device is in a functioning
mode. In this state, the device is ready to accept any incoming I2C requests and monitors for changes on the
input ports.
8.5 Programming
8.5.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a controller sending a Start condition, which is a high-to-low
transition on the SDA input and output while the SCL input is high (see Figure 8-3). After the Start condition, the
device address byte is sent, most-significant bit (MSB) first, including the data direction bit (R/ W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input
and output during the high of the ACK-related clock pulse.
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On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 8-4).
A Stop condition, a low-to-high transition on the SDA input and output while the SCL input is high, is sent by the
controller (see Figure 8-3).
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure
8-5). When a target receiver is addressed, it must generate an ACK after each byte is received. Similarly, the
controller must generate an ACK after each byte that it receives from the target transmitter. Setup and hold times
must be met to ensure proper operation.
A controller receiver signals an end of data to the target transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the target. This is done by the controller receiver, by holding the SDA
line high. In this event, the transmitter must release the data line to enable the controller to generate a Stop
condition.
SDA

SCL
S P
Start Condition Stop Condition

Figure 8-3. Definition of Start and Stop Conditions

SDA

SCL

Data Line Change

Stable; Of Data
Data Valid Allowed

Figure 8-4. Bit Transfer

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Data Output
By Transmitter

NACK
Data Output
By Receiver

ACK

SCL From
Controller
1 2 8 9

S Clock Pulse for

Acknowledgment
Start
Condition

Figure 8-5. Acknowledgment on the I2C Bus

8.6 Register Maps

Table 8-1 shows the PCA9536 interface definition.
Table 8-1. Interface Definition
BIT
BYTE
7 (MSB) 6 5 4 3 2 1 0 (LSB)
I2C target address H L L L L L H R/ W
Does not affect operation of the PCA9536
Px I/O data bus P3 P2 P1 P0
P7 P6 P5 P4

8.6.1 Device Address

Figure 8-6 shows the address byte of the PCA9536.
Target Address

1 0 0 0 0 0 1 1

Fixed

Figure 8-6. PCA9536 Address

The target address equates to 65 (decimal) and 41 (hexadecimal).

The last bit of the target address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
8.6.2 Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus controller sends a command byte that is
stored in the control register in the PCA9536. Two bits of this data byte state the operation (read or write) and
the internal register (Input, Output, Polarity Inversion, or Configuration) that will be affected. This register can be
written or read through the I2C bus. The command byte is sent only during a write transmission.

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Once a command byte has been sent, the addressed register is continuosly accessed by reads until a new
command byte is sent.
Figure 8-7 shows the PCA9536 control register bits and Table 8-2 shows the command byte.

0 0 0 0 0 0 B1 B0

Figure 8-7. Control Register Bits

Table 8-2. Command Byte

CONTROL REGISTER BITS COMMAND BYTE POWER-UP
REGISTER PROTOCOL
B1 B0 (HEX) DEFAULT

0 0 0×00 Input Port Read byte 1111 XXXX

0 1 0×01 Output Port Read/write byte 1111 1111
1 0 0×02 Polarity Inversion Read/write byte 0000 0000
1 1 0×03 Configuration Read/write byte 1111 1111

8.6.3 Register Descriptions

The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin
is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level. See Table 8-3.
Before a read operation, a write transmission is sent with the command byte to instruct the I2C device that the
Input Port register will be accessed next.
Table 8-3. Register 0 (Input Port Register)
I7 I6 I5 I4
BIT I3 I2 I1 I0
Not Used
DEFAULT 1 1 1 1 X X X X

The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. The bit values in this register have no effect on pins defined as inputs. In turn, reads from
this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. See
Table 8-4.
Table 8-4. Register 1 (Output Port Register)
O7 O6 O5 O4
BIT O3 O2 O1 O0
Not Used
DEFAULT 1 1 1 1 1 1 1 1

The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin's original polarity is retained. See Table 8-5.
Table 8-5. Register 2 (Polarity Inversion Register)
N7 N6 N5 N4
BIT N3 N2 N1 N0
Not Used
DEFAULT 0 0 0 0 0 0 0 0

The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to
1, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output. See Table 8-6.

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Table 8-6. Register 3 (Configuration Register)

C7 C6 C5 C4
BIT C3 C2 C1 C0
Not Used
DEFAULT 1 1 1 1 1 1 1 1

8.6.4 Bus Transactions

Data is exchanged between the controller and PCA9536 through write and read commands.
8.6.4.1 Writes
Data is transmitted to the PCA9536 by sending the device address and setting the least-significant bit (LSB) to a
logic 0 (see Figure 8-6 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte. There is no limitation on the number of data bytes sent
in one write transmission (see Figure 8-8 and Figure 8-9).

SCL 1 2 3 4 6 7 8 9
Target Address Command Byte Data to Register

SDA S 1 0 0 0 0 0 1 0 A 0 0 0 0 0 0 1 1 A Data 1 A P

Start Condition R/W ACK From Target ACK From Target ACK From Target

Write to
Port

Data Out
From Port Data 1 Valid

tpv

Figure 8-8. Write to Output Port Register

<br/>

SCL 1 2 3 4 6 7 8 9
Target Address Command Byte Data to Register

SDA S 1 0 0 0 0 0 1 0 A () 0 0 0 0 0 1 1 A Data A P

Start Condition R/W ACK From Target ACK From Target ACK From Target

Data to
Register

Figure 8-9. Write to Configuration or Polarity Inversion Registers

8.6.4.2 Reads
The bus controller first must send the PCA9536 address with the LSB set to a logic 0 (see Figure 8-6 for
device address). The command byte is sent after the address and determines which register is accessed. After a
restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined
by the command byte then is sent by the PCA9536 (see Figure 8-10 and Figure 8-11). After a restart, the value
of the register defined by the command byte matches the register being accessed when the restart occurred.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus controller must not
acknowledge the data.

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Target Target Target Target Target Controller

At this time, the controller-transmitter

becomes controller-receiver and
target-receiver becomes target-transmitter

Controller

Figure 8-10. Read From Register

<br/>

SCL 1 2 3 4 5 6 7 8 9
Target Address Data From Port Data From Port

SDA S 1 0 0 0 0 0 1 1 A Data 1 A Data 4 NA P

Start R/W ACK From ACK From NACK From Stop

Condition Target Controller Controller Condition
Read From
Port

Data Into
Data 2 Data 3 Data 4 Data 5
Port
t ph t ps

INT

t iv t ir

A. This figure assumes that the command byte previously has been programmed with 00h.
B. Transfer of data can be stopped at any moment by a Stop condition.
C. This figure eliminates the command byte transfer, a restart, and the target address call between the initial target address call and actual
data transfer from the P-port (see Figure 8-10).

Figure 8-11. Read Input Port Register

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9 Application Information Disclaimer

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

9.2 Typical Application
Figure 9-1 shows an application in which the PCA9536 can be used.
VCC

VCC 10 kΩ 10 kΩ 2 kΩ
VCC Subsystem 1
(e.g., temperature
SCL SCL
sensor)
P0
I2C
SDA SDA P1 INT
Controller
P2

PCA9536 P3 RESET
GND

Subsystem 2
(e.g., counter)

A
GND

ENABLE

A. Device address is 10000001.

B. P0, P2, and P3 are configured as outputs.
C. P1 is configured as an input.

Figure 9-1. Typical Application

9.2.1 Design Requirements

9.2.1.1 Minimizing ICC When I/Os Control LEDs
When the I/Os are used to control LEDs, they are normally connected to VCC through a resistor as shown
in Figure 9-1. The LED acts as a diode so, when the LED is off, the I/O VIN is about 1.2 V less than VCC.
The supply current, ICC, increases as VIN becomes lower than VCC and is specified as ΔICC in Electrical
Characteristics.
Designs needing to minimize current consumption, such as battery power applications, should consider
maintaining the I/O pins greater than or equal to VCC when the LED is off. Figure 9-2 shows a high-value
resistor in parallel with the LED. Figure 9-3 shows VCC less than the LED supply voltage by at least 1.2 V. Both
of these methods maintain the I/O VIN at or above VCC and prevent additional supply-current consumption when
the LED is off.

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VCC

LED
100 NŸ
VCC

Pn

Figure 9-2. High-Value Resistor in Parallel with the LED

3.3 V 5V

VCC LED

Pn

Figure 9-3. Device Supplied by a Lower Voltage

9.2.2 Detailed Design Procedure

The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into
consideration the total capacitance of all targets on the I2C bus. The minimum pull-up resistance is a function of
VCC, VOL,(max), and IOL as shown in Equation 1:

VCC - VOL(max)
Rp(min) =
IOL (1)

The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL
= 400 kHz) and bus capacitance, Cb as shown in Equation 2:

tr
Rp(max) =
0.8473 ´ Cb (2)

The maximum bus capacitance for an I2C bus must not exceed 400 pF for standard-mode or fast-mode
operation. The bus capacitance can be approximated by adding the capacitance of the PCA9536, Ci for SCL
or Cio for SDA, the capacitance of wires,connections or traces, and the capacitance of additional targets on the
bus.

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9.2.3 Application Curves

25 1.8
Standard-Mode VDPUX > 2 V
Fast-Mode 1.6 VDUPX </= 2
Maximum Pull-Up Resistance (k:)

Minimum Pull-Up Resistance (k:)

20 1.4

1.2
15
1

0.8
10
0.6

0.4
5
0.2

0 0
0 50 100 150 200 250 300 350 400 450 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Bus Capacitance (pF) Pull-Up Reference Voltage (V) D009
D008

Standard-mode: fSCL = 100 kHz, tr = 1 µs VOL = 0.2 × VCC, IOL = 2 mA when VCC ≤ 2 V
Fast-mode: fSCL = 400 kHz, tr = 300 ns VOL = 0.4 V, IOL = 3 mA when VCC > 2 V

Figure 9-4. Maximum Pull-Up Resistance (Rp(max)) Figure 9-5. Minimum Pull-Up Resistance (Rp(min))
vs Bus Capacitance (Cb) vs Pull-up Reference Voltage (VCC)

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10 Power Supply Recommendations

10.1 Power-On Reset Errata
A power-on reset condition can be missed if the VCC ramps are outside specification listed in Figure 10-1.

Figure 10-1. Power-On Reset Cycle

10.2 System Impact

If ramp conditions are outside timing allowances above, POR condition can be missed, causing the device to
lock up.

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11 Layout
11.1 Layout Guidelines
For printed circuit board (PCB) layout of the PCA9536, common PCB layout practices must be followed but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs are
not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power
in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These
capacitors must be placed as close to the PCA9536 as possible.
For the layout example provided, it would be possible to fabricate a PCB with only 2 layers by using the top layer
for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND). However, a 4-layer
board is preferable for boards with higher density signal routing. On a 4-layer PCB, it is common to route signals
on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal layer
to a power plane. In a board layout using planes or split planes for power and ground, vias are placed directly
next to the surface mount component pad which needs to attach to VCC or GND and the via is connected
electrically to the internal layer or the other side of the board. Vias are also used when a signal trace needs to be
routed to the opposite side of the board, but this technique is not demonstrated.
11.2 Layout Example
GND

CAP

P0 VCC

P1 SDA

PCA9536

P2 SCL

GND P3

Figure 11-1. Layout Example (DGK)

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12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• I2C Bus Pull-Up Resistor Calculation
• Maximum Clock Frequency of I2C Bus Using Repeaters
• Introduction to Logic
• Understanding the I2C Bus
• Choosing the Correct I2C Device for New Designs
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
NanoFree™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 22-Jul-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

PCA9536D OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 85 PD536

PCA9536DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (7CF, 7CL) Samples

PCA9536DGKRG4 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (7CF, 7CL) Samples

PCA9536DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PD536 Samples

PCA9536DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PD536 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 22-Jul-2023

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 22-Jul-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCA9536DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PCA9536DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 22-Jul-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCA9536DGKR VSSOP DGK 8 2500 366.0 364.0 50.0
PCA9536DR SOIC D 8 2500 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DGK0008A SCALE 4.000
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
TYP
A 4.75
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A
0.25
GAGE PLANE

1.1 MAX

0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20

TYPICAL

4214862/A 04/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

www.ti.com
 EXAMPLE BOARD LAYOUT
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

SYMM
8X (1.4) (R0.05) TYP

8X (0.45) 1 8

SYMM

6X (0.65)
5
4

SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214862/A 04/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

SYMM

8X (1.4) (R0.05) TYP

8X (0.45) 1 8

SYMM

6X (0.65)
5
4

(4.4)

SOLDER PASTE EXAMPLE

SCALE: 15X

4214862/A 04/2023
NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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