RTL8812AU-CG

SINGLE-CHIP IEEE 802.11ac 2T2R WLAN

CONTROLLER WITH USB 2.0/3.0
INTERFACE

DATASHEET
(CONFIDENTIAL: Development Partners Only)

Rev. 0.2
24,May, 2011
Track ID: JATR-2265-11

Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
 RTL8812AU
Datasheet

COPYRIGHT
© 2012 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements and/or
changes in this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.

TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.

USING THIS DOCUMENT

This document is intended for the software engineer‟s reference and provides detailed programming
information.

Though every effort has been made to ensure that this document is current and accurate, more information may
have become available subsequent to the production of this guide.

REVISION HISTORY
Revision Release Date Summary
0.2 24, May, 2012 Preliminary release.

Single-Chip IEEE 802.11a/b/g/n/ac 2T2R WLAN ii Track ID: JATR-2265-11 Rev. 0.2
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Table of Contents
1. GENERAL DESCRIPTION .............................................................................................................................................. 1

2. FEATURES ......................................................................................................................................................................... 3

3. APPLICATION DIAGRAMS ........................................................................................................................................... 5

3.1. 11AC DUAL-BAND 2X2 RF APPLICATION ..................................................................................................................... 5
4. PIN ASSIGNMENTS ......................................................................................................................................................... 6
4.1. PACKAGE IDENTIFICATION ............................................................................................................................................ 7
5. PIN DESCRIPTIONS ........................................................................................................................................................ 7
5.1. USB EXPRESS TRANSCEIVER INTERFACE ...................................................................................................................... 7
5.2. POWER PINS ................................................................................................................................................................. 8
5.3. RF INTERFACE.............................................................................................................................................................. 8
5.4. LED INTERFACE ........................................................................................................................................................... 9
5.5. CLOCK AND OTHER PINS .............................................................................................................................................. 9
6. ELECTRICAL AND THERMAL CHARACTERISTICS ........................................................................................... 11
6.1. TEMPERATURE LIMIT RATINGS ................................................................................................................................... 11
6.2. DC CHARACTERISTICS................................................................................................................................................ 11
7. MECHANICAL DIMENSIONS...................................................................................................................................... 12
7.1. MECHANICAL DIMENSIONS NOTES.............................................................................................................................. 13
8. ORDERING INFORMATION ........................................................................................................................................ 14

Single-Chip IEEE 802.11a/b/g/n/ac 2T2R WLAN iii Track ID: JATR-2265-11 Rev. 0.2
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List of Tables
TABLE 1. USB TRANSCEIVER INTERFACE ....................................................................................................................................... 7
TABLE 2. POWER PINS .................................................................................................................................................................... 8
TABLE 3. RF INTERFACE ................................................................................................................................................................ 8
TABLE 4. LED INTERFACE ............................................................................................................................................................. 9
TABLE 5. CLOCK AND OTHER PINS ................................................................................................................................................. 9
TABLE 6. TEMPERATURE LIMIT RATINGS ...................................................................................................................................... 11
TABLE 7. DC CHARACTERISTICS .................................................................................................................................................. 11
TABLE 8. ORDERING INFORMATION .............................................................................................................................................. 14

List of Figures
FIGURE 1. DUAL-BAND MIMO 2X2 SOLUTION－RTL8812AU-CG (11AC 2X2 MAC/BB/RF + PA) ............................................ 5
FIGURE 2. PIN ASSIGNMENTS ......................................................................................................................................................... 6

Single-Chip IEEE 802.11a/b/g/n/ac 2T2R WLAN iv Track ID: JATR-2265-11 Rev. 0.2
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1. General Description
The Realtek RTL8812AU-CG is a highly integrated single-chip MIMO (Multiple In, Multiple Out) Wireless
LAN (WLAN) USB 2.0/3.0 network interface controller complying with the wireless very high throughput
IEEE 802.11ac Draft 2.0 and 802.11n specifications. The RTL8812AU-CG provides a complete solution for a
high-performance wireless client and also supports WiFi Direct feature that can easily build a WiFi P2P PAN
network.

The RTL8812AU-CG baseband implements Multiple Input, Multiple Output (MIMO) Orthogonal Frequency
Division Multiplexing (OFDM) with two transmit and two receive paths (2T2R). Features include two spatial
stream transmissions, short Guard Interval (GI) of 400ns, spatial spreading, and support for both 20MHz,
40MHz and 80MHz channel bandwidth. Moreover, RTL8812AU provides one spatial stream space-time block
code (STBC) , Transmit Beamforming (TxBF) and Low Density Parity Check (LDPC) to extend the range of
transmission. At the receiver, extended range and good minimum sensitivity is achieved by having receiver
diversity up to 2 antennas. As the recipient, the RTL8812AU also supports explicit sounding packet feedback
that helps senders with beamforming capability. With 2 independent RF blocks, the RTL8812AU can perform
fast roaming without link interruption.

For legacy compatibility, Direct Sequence Spread Spectrum (DSSS), Complementary Code Keying (CCK) and
OFDM baseband processing are included to support all IEEE 802.11b, 802.11g and 802.11a data rates.
Differential phase shift keying modulation schemes, DBPSK and DQPSK with data scrambling capability are
available, and CCK provides support for legacy data rates, with long or short preamble. The high speed
FFT/IFFT paths, combined with BPSK, QPSK, 16QAM, 64QAM and 256QAM modulation of the individual
subcarriers, and rate compatible coding rate of 1/2, 2/3, 3/4, and 5/6, provide up to 866.7Mbps for IEEE
802.11ac MIMO OFDM.

The RTL8812AU-CG builds in an enhanced signal detector, an adaptive frequency domain equalizer, and a
soft-decision Viterbi decoder to alleviate severe multi-path effects and mutual interference in the reception of
multiple streams. For better detection quality, receive diversity with Maximal-Ratio-Combine (MRC) applying
up to two receive paths is implemented. Robust interference detection and suppression are provided to protect
against Bluetooth, cordless phone, and microwave oven interference.

Receive vector diversity for multi-stream application is implemented for efficient utilization of the MIMO
channel. Efficient IQ-imbalance, DC offset, phase noise, frequency offset, and timing offset compensations are
provided for the radio frequency front-end. Selectable digital transmit and receive FIR filters are provided to
meet transmit spectrum mask requirements and to reject adjacent channel interference, respectively.

Single-Chip IEEE 802.11a/b/g/n/ac 2T2R WLAN 1 Track ID: JATR-2265-11 Rev. 0.2
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 RTL8812AU
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The RTL8812AU-CG supports fast receiver Automatic Gain Control (AGC) with synchronous and
asynchronous control loops among antennas, antenna diversity functions, and adaptive transmit power control
functions to obtain better performance in the analog portions of the transceiver.

The RTL8812AU-CG MAC supports 802.11e for multimedia applications, 802.11i and WAPI (Wireless
Authentication Privacy Infrastructure) for security, and 802.11n/802.11ac Draft 2.0 for enhanced MAC
protocol efficiency. Using packet aggregation techniques such as A-MPDU with BA and A-MSDU, protocol
efficiency is significantly improved. Power saving mechanisms such as Legacy Power Save, U-APSD, and
MIMO power saving reduce the power wasted during idle time, and compensate for the extra power required to
transmit MIMO OFDM. The RTL8812AU-CG provides simple legacy, 20MHz/40MHz/80MHz co-existence
mechanisms to ensure backward and network compatibility.

Single-Chip IEEE 802.11a/b/g/n/ac 2T2R WLAN 2 Track ID: JATR-2265-11 Rev. 0.2
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2. Features
General  WAPI (Wireless Authentication Privacy
Infrastructure) certified.
 QFN76 9x9mm package
 Cisco Compatible Extensions (CCX) for
 CMOS MAC, Baseband PHY and RF in a WLAN devices
single chip for IEEE 802.11a/b/g/n/ac Draft
2.0 compatible WLAN MAC Features

 802.11ac MIMO solution for 5G band  Frame aggregation for increased MAC
efficiency (A-MSDU, A-MPDU)
 Complete 802.11n MIMO solution for
2.4GHz and 5Ghz band  Low latency immediate High-Throughput
Block Acknowledgement (HT-BA)
 2x2 MIMO technology for extended reception
robustness and exceptional throughput  Long NAV for media reservation with CF-End
for NAV release
 Maximum PHY data rate up to 173.3 Mbps
using 20MHz bandwidth, 400Mbps using  PHY-level spoofing to enhance legacy
40MHz bandwidth, and 866.7Mbps using compatibility
80MHz bandwidth.
 MIMO power saving mechanism
 Backward compatible with 802.11a/b/g
devices while operating at 802.11n data rates  Channel management and co-existence

 Backward compatible with 802.11a/n devices  Multiple BSSID feature allows the
while operating at 802.11ac data rates. RTL8812AU-CG to assume multiple MAC
identities when used as a wireless bridge
Host Interface
 Transmit Opportunity (TXOP) Short
 Complies with USB Specification Revision 3.0 Inter-Frame Space (SIFS) bursting for higher
Standards Supported multimedia bandwidth

 IEEE 802.11a/b/g/n/ac Draft 2.0 compatible  WiFi Direct supports wireless peer to peer
WLAN applications.
Other Features
 IEEE 802.11e QoS Enhancement (WMM)
 Supports Wake-On-WLAN via Magic Packet
 IEEE 802.11i (WPA, WPA2). Open, shared and Wake-up frame
key, and pair-wise key authentication services
 Transmit Beamforming
 IEEE 802.11h TPC, Spectrum Measurement
 CCA on secondary through RTS/CTS
 IEEE 802.11k Radio Resource Measurement handshake.

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 Support TCP/UDP/IP checksum offload  OFDM with BPSK, QPSK, 16QAM, 64QAM
and 256QAM modulation. Convolutional
Peripheral Interfaces Coding Rate: 1/2, 2/3, 3/4, and 5/6
 Up to 12 General Purpose Input/Output pins  Maximum data rate 54Mbps in 802.11g,
300Mbps in 802.11n and 866.7Mbps in
 Three configurable LED pins (mux with GPIO
802.11ac.
pins)
 OFDM receive diversity with MRC using up to
 Configurable Bluetooth Coexistence Interface
2 receive paths. Switch diversity used for
(mux with GPIO pins)
DSSS/CCK
 Generates 40MHz clock for peripheral chip.
 Support STBC
 Single external power source 3.3V only
 Support LDPC
PHY Features
 Hardware antenna diversity
 IEEE 802.11ac MIMO OFDM
 Selectable digital transmit and receiver FIR
 IEEE 802.11n MIMO OFDM filters

 Two Transmit and Two Receive paths  Programmable scaling in transmitter and
receiver to trade quantization noise against
 5MHz / 10MHz / 20MHz / 40MHz / 80MHz increased probability of clipping
bandwidth transmission
 Fast receiver Automatic Gain Control (AGC)
 Support 2.4Ghz and 5Ghz band channels
 On-chip ADC and DAC
 Short Guard Interval (400ns)
 Build-in both 2.4GHz and 5GHz PA
 Sounding packet.
 Build-in both 2.4GHz and 5GHz LNA
 DSSS with DBPSK and DQPSK, CCK
modulation with long and short preamble

Single-Chip IEEE 802.11a/b/g/n/ac 2T2R WLAN 4 Track ID: JATR-2265-11 Rev. 0.2
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3. Application Diagrams
3.1. 11ac Dual-Band 2x2 RF Application

RTL 8812AU
2.4 / 5GHz
PA RX I / Q
MCU NV Memory

A D C
2.4G / 5G 2.4G / 5G
Antenna B FE Transceiver

LNA

MAC USB Interface

2.4 / 5GHz Configuration
PA Control and
2.4G / 5G Memory
2.4G / 5G
Antenna A FE Transceiver

D A C
LNA
TX I / Q

SPS / LDO Baseband

External 3.3V
40 MHz 40MHz LED / GPIO Pins / BT co-existence
Powe Source
Clock Interface
Crystal
(Option)

Figure 1. Dual-Band MIMO 2x2 Solution－RTL8812AU-CG (11ac 2x2 MAC/BB/RF + PA)

Single-Chip IEEE 802.11a/b/g/n/ac 2T2R WLAN 5 Track ID: JATR-2265-11 Rev. 0.2
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4. Pin Assignments

LX_SPS0

LX_SPS0
VDSPS33

GPIO[3]

GPIO[2]
VDDRX

VD12S
VDDTX

VD33S

HSDM
HSON
HSOP

HSDP
RREF
HSIN
HSIP
GND

GND

GND
57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
FB_SPS 58 38 GPIO[1]
VD33D 59
37 GPIO[0] / BT_Suspend
VD12D 60 36 GPIO[11] / PDn

TRSWB_S1 61 35 LED0 / GPIO[10]

TRSW_S1 62 34 LED1 / GPIO[9]

PAPE_5G_S1 63 33 LED2 / GPIO[8]

PAPE_2G_S1 64 32 GPIO[7] / BT_PRI

LNAON_S1 65 31 GPIO[6] / BT_STATE

V12_BB_S1 66 30 GPIO[5]/BT_FREQ/BT_EN
RF2IN_S1 67 29 GPIO[4] / WL_ACT
RF2IP_S1 68 28 VD33D
V33_PAD2G_S1 69 27 VD12D
RF2ON_S1 70 RTL 8812AU 26 ANTSWB
RF2OP_S1 71 25 ANTSW
V33_PAD5G_S1 72
LLLLLLL TXXXV 24 CK_BT
RF5OP_S1 73 23 XO
VD33PA5G_S1 74 22 XI
77 GND ( Exposed Pad )
RF5IP_S1 75 21 VD33A

RF5IN_S1 76 20 VD12A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
RF2IN_S0

LNAON_S0
V12_S0

RF2IP_S0
V12_SYN

RF2ON_S0

RF2OP_S0
V33_SYN

RF5IN_S0
RF5IP_S0
RF5OP_S0

V12_BB_S0

TRSW_S0

TRSWB_S0
V33_PAD2G_S0

VD33PA5G_S0
V33_PAD5G_S0

PAPE_2G_S0

PAPE_5G_S0

Figure 2. Pin Assignments

Single-Chip IEEE 802.11a/b/g/n/ac 2T2R WLAN 6 Track ID: JATR-2265-11 Rev. 0.2
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4.1. Package Identification

Green package is indicated by a „G‟ in the location marked „T‟ in Figure 2.

5. Pin Descriptions
The following signal type codes are used in the tables:

I: Input O: Output

T/S: Tri-State bi-directional input/output pin S/T/S: Sustained Tri-State

O/D: Open Drain P: Power pin

5.1. USB Express Transceiver Interface

Table 1. USB Transceiver Interface
Symbol Type Pin No Description
HSDP/HSDM I/O 41, 42 High speed USB Differential Pair
HSON/USOP O 48, 49 Super speed USB tx differential pair
HSIN/HSIP I 51, 52 Super speed USB rx differential pair.

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5.2. Power Pins

Table 2. Power Pins
Symbol Type Pin No Description
V33_SYN P 1 3.3V for analog circuits
V12_SYN P 2 1.2V for analog circuits
V12_S0 P 3 1.2V for analog circuits
V33_PAD2G_S0 P 6 3.3V for analog circuits
V33_PAD5G_S0 P 9 3.3V for analog circuits
VD33PA5G_S0 P 11 3.3V for analog circuits
V12_BB_S0 P 14 1.2V for analog circuits
VD12A P 20 1.2V for analog circuits
VD33A P 21 3.3V for analog circuits
VD12S P 44 1.2V for analog circuits
VD33S P 45 3.3V for analog circuits
RREF P 46 Reference current source
Connect 6.2k ohm(1%) precision resistor to ground.
VDDTX P 47 1.2V for analog circuits
VDDRX P 53 1.2V for analog circuits
LX P 56, 55 Switching Regulator Output
VDSPS33 P 57 3.3V for analog circuits
FB_SPS P 58 Switching regulator feedback path. connect with LX.
VD33D P 59, 28 VDD3.3V for Digital
VD12D P 60, 27 Digital 1.2V Regulator Output
V12_BB_S1 P 66 1.2V for analog circuits
V33_PAD2G_S1 P 69 3.3V for analog circuits
V33_PAD5G_S1 P 72 3.3V for analog circuits
VD33PA5G_S1 P 74 3.3V for analog circuits
GND P 54, 50, 41 Ground

5.3. RF Interface
Table 3. RF Interface
Symbol Type Pin No Description
RF2IN_S0 I 4 RF 2.4G Rx0 negative signal
RF2IP_S0 I 5 RF 2.4G Rx0 positive signal
RF2ON_S0 O 7 RF 2.4G Tx0 negative signal
RF2OP_S0 O 8 RF 2.4G Tx0 positive signal
RF5OP_S0 O 10 RF 5G Tx0 positive signal
RF5IP_S0 I 12 RF 5G Rx0 positive signal
RF5IN_S0 I 13 RF 5G Rx0 negative signal

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Symbol Type Pin No Description
LNAON_S0 O 15 External LNA_0 enable
PAPE_2G_S0 O 16 2.4GHz Tx power amplifier 0 enable
PAPE_5G_S0 O 17 5 GHz Tx power amplifier 0 enable
TRSW_S0 O 18 Transmit/Receive Path Select 0
TRSWB_S0 O 19 Transmit/Receive Path Select 0
ANTSW O 25 Antenna select control signal
ANTSWB O 26 Antenna select control signal
TRSWB_S1 O 61 Transmit/Receive Path Select 1
TRSW_S1 O 62 Transmit/Receive Path Select 1
PAPE_5G_S1 O 63 5GHz Tx power amplifier 1 enable
PAPE_2G_S1 O 64 2.4 GHz Tx power amplifier 1 enable
LNAON_S1 O 65 External LNA_1 enable
RF2IN_S1 I 67 RF 2.4G Rx1 negative signal
RF2IP_S1 I 68 RF 2.4G Rx1 positive signal
RF2ON_S1 O 70 RF 2.4G Tx1 negative signal
RF2OP_S1 O 71 RF 2.4G Tx1 positive signal
RF5OP_S1 O 73 RF 5G Tx1 positive signal
RF5IP_S1 I 75 RF 5G Rx1 positive signal
RF5IN_S1 I 76 RF 5G Rx1 negative signal

5.4. LED Interface

Table 4. LED Interface
Symbol Type Pin No Description
LED2 / GPIO[8] O 33 LED pins (Active Low)
The pin is also shared with GPIO9 and can be selected by control register
LED1 / GPIO[9] O 34 LED pins (Active Low)
The pin is also shared with GPIO10 and can be selected by control register
LED0 / GPIO[10] O 35 LED pins (Active Low)
The pin is also shared with GPIO8 and can be selected by control register

5.5. Clock and Other Pins

Table 5. Clock and Other Pins
Symbol Type Pin No Description
XI I 22 40MHz OSC Input.
Input of 40MHz Crystal clock reference
XO O 23 Output of 40MHz Crystal Clock Reference
CK_BT O 24 buffered 40MHz clock outputs for other peripheral IC

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 RTL8812AU
Datasheet
Symbol Type Pin No Description
GPIO[4] / WL_ACT IO 29 General Purpose Input/Output Pin or Bluetooth Coexistence WLAN_ACT
Pin.
The WLAN_ACT signal indicates when WLAN is either transmitting or
receiving in the 2.4GHz ISM band.
GPIO[5] / BT_FREQ / IO 30 General Purpose Input/Output Pin or Bluetooth Coexistence WLAN_RX
BT_EN Pin.
WLAN_RX is an indicator for wireless LAN RX activity.
GPIO[6] / BT_STATE IO 31 General Purpose Input/Output Pin or Bluetooth Coexistence BT_STAT Pin.
The BTSTAT signal indicates when normal Bluetooth packets are being
transmitted or received.
GPIO[7] / BT_PRI IO 32 General Purpose Input/Output Pin or Bluetooth Coexistence BT_PRI Pin.
The BT_PRI signal indicates when a high priority Bluetooth packet is being
transmitted or received.
PDn / GPIO[11] I 36 This Pin can externally shutdown the RTL8812AU (no requirement for an
extra power switch) or turn the WLAN radio off through the host interface
according to internal the setting of internal non-volatile memory.
This pin is also shared with GPIO11.
GPIO[0] / BT_Suspend IO 37 General Purpose Input/Output Pin or Bluetooth enable/disable inform input
pin.
GPIO[1] IO 38 General Purpose Input/Output Pin
GPIO[2] IO 39 General Purpose Input/Output Pin
GPIO[3] IO 40 General Purpose Input/Output Pin

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6. Electrical and Thermal Characteristics

6.1. Temperature Limit Ratings
Table 6. Temperature Limit Ratings
Parameter Minimum Maximum Units
Storage Temperature -55 +125 C
Ambient Operating Temperature 0 70 C
Junction Temperature 0 125 C

6.2. DC Characteristics
Table 7. DC Characteristics
Symbol Parameter Minimum Typical Maximum Units
DVDD33 3.3V I/O Supply Voltage 3.0 3.3 3.6 V
DVDD12 1.2V Core Supply Voltage 1.10 1.2 1.32 V

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7. Mechanical Dimensions

Single-Chip IEEE 802.11a/b/g/n/ac 2T2R WLAN 12 Track ID: JATR-2265-11 Rev. 0.2
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 RTL8812AU
Datasheet

7.1. Mechanical Dimensions Notes

Dimension in mm Dimension in inch
Symbol
Min Nom Max Min Nom Max
A 0.75 0.85 1.00 0.030 0.034 0.039
A1 0.00 0.02 0.05 0.000 0.001 0.002
A2 0.55 0.65 0.80 0.022 0.026 0.032
A3 0.20 REF 0.008 REF
b 0.15 0.20 0.25 0.006 0.008 0.010
D/E 9.00BSC 0.354BSC
D1/E1 8.75BSC 0.344BSC
D2 5.56 5.81 6.06 0.219 0.229 0.239
E2 6.06 6.31 6.56 0.239 0.249 0.259
e 0.40BSC 0.016BSC
L 0.30 0.40 0.50 0.012 0.016 0.020
Notes：
1. CONTROLLING DIMENSION：MILLIMETER(mm).
2. REFERENCE DOCUMENTL：JEDEC MO-220.

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 RTL8812AU
Datasheet

8. Ordering Information
Table 8. Ordering Information
Part Number Package Status
RTL8812AU-CG QFN-76, „Green‟ Package Engineering sample

Realtek Semiconductor Corp.

Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com

Single-Chip IEEE 802.11a/b/g/n/ac 2T2R WLAN 14 Track ID: JATR-2265-11 Rev. 0.2
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