Scratching Cases Principles of VLSI Design

Design Margin
Design Margin, Reliability and Scaling CMPE 413

Design Margin requried as there are three sources of variation- two enviornmental and one
manufacturing:
„ Supply Voltage
„ Operating temperature
 Rolling Indenter „ Process variation
 Line Scratches Aim is to design the circuit that will reliably operate over all extremes of these three vari-
– Copper Only ables.

– Copper & ILD Variations can be modeled as uniform or normal (Gaussian) statistical distributions.
Normal (Gaussian) Uniform 1
 Chatter Scratches All parts lie within
the half range
 Uncovery of Pores 120 microns (1σ − 31.7%)

(2σ − 4.6%)
(3σ − 0.26%)
-3 -2 -1 0 1 2 3 -1 0 1
1

Principles of VLSI Design Design Margin, Reliability and Scaling CMPE 413 Principles of VLSI Design Design Margin, Reliability and Scaling CMPE 413

Design Margin Design Margin

Supply Voltage Process Variation

Supply voltage may vary due to tolerance of voltage regulators, IR drop along the sup- Devices have variations in film thicknesses, lateral dimensions, doping concentrations etc.
ply rail and di/dt noise.
The parameters of individual transistors vary from:
Typically the supply is specified as +/- 10% around nominal (uniform distribution) „ Lot to lot (interprocess variation)
„ Wafer to wafer (interprocess variation)
Speed is roughly proportional to VDD, also noise budgets are affected. „ Die to die (intraprocess variation)

Temperature Design Corners

Parts must operate over a range of temperatures. From the designer's point of view, the collective effects of process and environmental
variations can be lumped into their effect on transistors:
Standard Minimum Maximum „ typical (nominal)
Commercial 0oC 70oC „ fast
Industrial „ slow
-40oC 85oC
Military o
-55 C 125oC Speed of each type of transistors, interconnect speed variations and environmental varia-
tions are used to define design or process corners.

2 3
Principles of VLSI Design Design Margin, Reliability and Scaling CMPE 413 Principles of VLSI Design Design Margin, Reliability and Scaling CMPE 413

Design Margin Design Margin

Design Corners (contd.) Design corner checks

FF
SF Corner
Fast Purpose
NMOS PMOS Wire VDD Temp
PMOS TT T T T S S timing specifications (binned parts)
T S S S S timing specifications (conservative)
F F F F F DC power dissipation, race conditions, hold time
Slow SS FS constraints, pulse collapse, noise
F F F F S subthreshold leakage noise, overall noise analysis
Slow NMOS Fast
S S F S S races of gates against wires
Environmental corners (1.8V process) F F S F F races of wires against gates
Corner Voltage Temperature S F T F F pseudo-NMOS & ratioed circuits noise margins,
memory read/write, race of PMOS against NMOS
Fast (F) 1.98 0oC F S T F F ratioed circuits, memory read/write, race of NMOS
Typical (T) 1.8 70oC against PMOS
Slow (S) 1.62 125oC

4 5

Principles of VLSI Design Design Margin, Reliability and Scaling CMPE 413 Principles of VLSI Design Design Margin, Reliability and Scaling CMPE 413

Reliability Reliability

Reliability problems cause integrated circuits to fail permanently, including: Most systems exhibit the bathtub curve.
„ Electromigration
Infant Useful
„ Self-heating Mortality Operating Wearout
„ Hot Carriers Life
„ Latchup Failure
„ Overvoltage failure Rate

Mean Time Between Failures (MTBF)

# devices * hours of operation / # failures
Time
Failures in Time (FIT)
Important to age systems past infant mortality (burn-in) before shipping products
The number of failures that would occur every thousand hours per million devices.
e.g. 1000 FIT is one failure in 106
hours = 114 years. (good for a single chip !!!) Electromigration
System with 100 chips each rated at 1000 FIT and you have 10 systems,
failure rate is 100*1000*10 = 106 FIT, or one failure every 1000 hours (42 days). Causes wearout of metal interconnect through the formation of voids
High current densities lead to an 'electron wind' that causes metal atoms to migrate
Need to target 100 FIT !!! over time.

6 7
Principles of VLSI Design Design Margin, Reliability and Scaling CMPE 413 Principles of VLSI Design Design Margin, Reliability and Scaling CMPE 413

Reliability Reliability

Electromigration (contd.) Hot Carriers

Depends on the current density J. Current limits are usually expressed as a maximum Jdc As transistors switch, some high energy (hot) carriers may be injected into the gate oxide
More likely to occur for wires carrying DC currents and become trapped there
Contact cuts have lower current density than metal lines
Damaged oxides change I-V: increases current in PMOS and decreases current in NMOS
Self-heating
Hot carriers cause circuit wearout as NMOS transistors become too slow
Bidirectional wires are less prone to electromigration, their current density is limited by
Wear is limited by setting maximum values on input rise-time and stage electrical effort
self-heating
The maximum values depend on process and operating voltage
High current dissipate power, raising in temperature and thus resistance and delay
Latchup
Limited using reasonable values of Jrms
Parasitic bipolar transistors are formed by substrate, well and diffusion
In summary, electromigration is primarily a problem in power and ground lines, self-heat-
ing limits the RMS current density in bidirectional signal lines. Significant current flows If these transistors turn ON, it develops a low-resistance path between VDD and GND, caus-
through wire contacting NMOS and PMOS transistors and therefore needs consideration. ing catastrophic meltdown, called latchup.

8 9

Principles of VLSI Design Design Margin, Reliability and Scaling CMPE 413 Principles of VLSI Design Design Margin, Reliability and Scaling CMPE 413

Reliability Reliability

Latchup (contd) Overvoltage failures

Transistors can be easily damaged by overvoltage reliability problems due to:

p+ n+ n+ p+ p+ n+
„ Electrostatic Discharge (ESD): Static electricity entering I/O pads can cause very
Rsub Rwell
large voltage and current transients
„ Breakdown and Arcing: Undesired voltages applied to the gate can cause oxide
breakdown, destroying the device
The cross-coupled transistors form a bistable silicon-controlled rectifier (SCR) „ Punchthrough: Higher than normal voltages applied between source and drain, can
cause the source/drain depletion regions touch
Ordinarily both transistors are off, but latchup can be triggered by transient current during „ Time-dependent Dielectric Breakdown (TDDB): Gate oxides wear out with time as
normal chip power-up or external voltages outside the normal operating range tunneling currents cause irreversible damage to the oxide

Latchup can be prevented by minimizing the two resistance values.

Soft Errors
Can be accomplished by putting one tap (contact) per well, connecting substrate and well
Some errors are spontaneous and occur in random fashion. Known as soft errors and are
taps to the supply using metal lines, placing a tap per 5 transistors and clustering NMOS
mainly attributed to alpha particles (from decaying uranium, thorium etc used in the pack-
near GND and PMOS near VDD
age). Refer to the book for more details.

10 11
Principles of VLSI Design Design Margin, Reliability and Scaling CMPE 413 Principles of VLSI Design Design Margin, Reliability and Scaling CMPE 413

Scaling Scaling

Technology scaling rate is approximately 13%/year, halving every 5 years. Constant Field Scaling
100
Critical parameters are scaled by a factor of S:

„ All dimensions (in the x,y and z dimensions)

10 „ Device voltages
„ Doping concentration densities
µm
Lateral Scaling
1
Only the gate length is scaled. Commonly called a gate shrink.
Offers quadratic improvement according to first order model, but is close to linear improve-
ment due to velocity saturation effects
0.1
1960 1970 1980 1990 2000 Constant Voltage Scaling

The size of the circuits also continues to increase. Feature size is shrunk keeping the supply voltage constant, providing quadratic improve-
Besides increasing the number of devices, scaling has had a profound impact on both speed ment in delay as well as cost reduction. Worked for 6µm to 1µm.
and power.
12 13

Principles of VLSI Design Design Margin, Reliability and Scaling CMPE 413 Principles of VLSI Design Design Margin, Reliability and Scaling CMPE 413

Scaling International Technology Roadmap for Semiconductors (ITRS)

Parameter Sensitivity Constant Field Lateral Developed by the Semiconductor Industry Association (SIA) to guide research efforts and
Length: L and Width:W 1/S and 1/S 1/S and 1 predict future needs. Predictions from 2002 ITRS (high performance microprocessors):
Gate oxide thickness: tox 1/S 1 Year 2004 2007 2010 2013 2016
Supply voltage:V-and threshold voltage:Vt 1/S 1 Feature Size (nm) 90 65 45 32 22
Substrate doping NA S 1 VDD (V) 1-1.2 0.7-0.11 0.6-1.0 0.5-0.9 0.4-0.9
β W/L * 1/tox S S Millions of transistors/die 385 773 1564 3092 6184
Current: Ids β(VDD-Vt)2 1/S S Wiring levels 9-13 10-14 10-14 11-15 11-15
Gate Delay: τ RC 1*1/S = 1/S 1/S*1/S=1/S2 Intermediate wire pitch (nm) 275 195 135 95 65

Clock frequency: f 1/τ S Interconnect dielectric constant 2.6-3.1 2.3-2.7 2.1 1.9 1.8
S2
I/O signals 1024 1024 1280 1408 1472
Dynamic power dissipation (per gate): P 2
CV f 1/S 2 S
Clock rate (MHz) 3990 6739 11511 19348 28751
Chip area: A 1/S2 1
FO4 delays/cycle 8.4 6.8 5.8 4.8 4.7
Power density P/A 1 S Maximum power (W) 160 190 218 251 288
Current density Ids/A S S DRAM capacity (Gbits) 1 4 8 32 64

14 15
Principles of VLSI Design Design Margin, Reliability and Scaling CMPE 413 Principles of VLSI Design Design Margin, Reliability and Scaling CMPE 413

Impacts on Design Impacts on Design

Improved Performance and Cost Power

Positive impact of scaling: both are improving Both dynamic and static power are predicted to increase.
When the transistor was invented, the prediction was that the price would eventually Intel predictions of chip running with power density of a nuclear reactor in 2005, a rocket
decrease to 50 cents a transistor. Today we can buy more that 100,000 for a penny !!! nozzle in 2010 and surface of sun in 2015 !!!

Interconnect Productivity

We have shifted to Cu and low-k dielectrics and design methodology has changed to specif- Number of transistors on chip is increasing faster than design productivity
ically focus on interconnect delay Use EDA tools and make them more efficient while not degrading performance
Design teams approaching size of automotive and aerospace teams !!!
Chip Size
When will CMOS scaling end?

Scaling of Reachable Radius Predictions (or fallacies):

1972: 0.25µm, 10-30 MHz.
1999: 100nm around 2004
2004: Most believe 2013, 35nm. ANY BETS ???

16 17
CMOS INTEGRATED CIRCUIT DESIGN TECHNIQUES
University of Ioannina

VLSI Testing

Dept. of Computer Science and Engineering

Y. Tsiatouhas

CMOS Integrated Circuit Design Techniques

Overview

1 VLSI testing
1.
On‐chip/off
2. On‐chip/off‐‐chip, on‐
on‐line/off
line/off‐‐line testing
3. Fault models
4. Yield – Defect level – Fault coverage
5. Control/observation
/ points
6. Path delay fault testing
VLSI Systems
and Computer Architecture Lab 7. Circuit partition/segmentation

1
 Testing

With the term Integrated Circuit (IC) or VLSI Testing we refer

to those procedures that take place after chip fabrication in
order
d to detect
d possible
ibl manufacturing
f i defects.
d f

VLSI Testing 3

CMOS Technology Scaling

Nanometer
M6
Technologies
M5
Cu
M4

M3

M2
Low k
M1
Metal Gate
Tungsten

High k
VLSI Testing 4

2
 Testing Necessity
• Imperfections in chip fabrication may lead to
Early‐life manufacturing defects.
Failure Rate

failures Dominant !
Infant # _ of _ acceptable _ parts
mortality
Wearout Y
Aging total _# _ of _ fabricated _ parts

Bathtub Curve • The manufacturing yield (Y) ( α ασ ασ ι ή

από οση) depends on the used technology,
the silicon area and the layout design.
Burn‐In Working Lifetime Time • Early in a technology development the yield is
Testing too low (even less than 10%) and
(limitations)
continuously rises (even above 95%) as
technology is getting mature.
Rule:: The earlier a defect is detected the less the cost for the final product. The
Rule
rule of ten says that the cost of detecting a defective device increases by an
order of magnitude as we move from a manufacturing stage to the next
(device  board  system)
VLSI Testing 5

The Cost of Testing

VLSI Testing 6

3
 Reliability and Time to Market

Revenues Time to Product‐1

Market
M k t2

Time to
Market 1

Product‐2
ΔΤ Time in months

• A reliable product with small time to market will provide

higher revenues than another product with large time to
market.
 Testing procedures at the minimum cost in time and resources are
required!
VLSI Testing 7

Off‐‐Chip and On‐

Off On‐Chip Testing

Off chip testing: The test procedures are applied by external

to the chip test equipments (Automatic Test Equipment – ATE
or Tester).

Οn chip testing: Embedded, on‐chip, resources are also

provided in order to support the testing procedures.

VLSI Testing 8

4
 On‐‐Line and Off‐
On Off‐Line Testing

• On‐line testing: Testing procedures are applied in the field

of operation.
p
 Concurrent testing: Testing is performed concurrently with the
circuit operation in the field, during the normal mode.
 Periodic testing: Testing is performed periodically, during idle
times of the circuit operation.

• Off‐line testing: Testing procedures are applied out of the

field of operation, usually after fabrication (manufacturing
testing).

VLSI Testing 9

Defects – Faults – Errors

• Defects ( αττώ ατα): are circuit failures and malfunctions

due to the manufacturing process (e.g.
(e g short‐circuits,
short circuits opens
e.t.c.).
• Faults (Σφά ατα): model the influence of defects on the
circuit operation (e.g. a line (node) is permanently stuck‐at
“1” or “0”).
• Errors ( άθη): are the incorrect logic responses of the
circuit under the presence of faults.

VLSI Testing 10

5
 Short‐‐Circuit Defects
Open and Short
Early Technologies
Contact aspect ratio: L/D = 7/1
0.18m Technology

D L
d = defect size

STI

Nanometer Technologies

VLSI Testing 11

Fault Models
A F
B

• Stuck‐At Faults (Μό ι ης Τι ής): a

VDD
circuit node is permanently fixed to a
logic value.
A • Transistor Stuck‐On Faults: a transistor
B
is permanently in a conducting state.
F • Transistor Stuck‐Open Faults: a
transistor is permanently in a non‐
conducting state.
A
• Bridging Faults: short‐circuits between
adjacent nodes.
B • Delay Faults: signal propagation delays
(in one or more paths) that are outside
the circuit specifications.
Gnd

VLSI Testing 12

6
 Permanent and Temporary Faults

• Permanent Faults ( ό ι α Σφά ατα) are those faults

that have a permanent impact on the circuit operation.
operation
• Temporary Faults (Π όσ αι α Σφά ατα) are those faults
that do not have a permanent impact on the circuit
operation. They are categorized as:
 Transient (Πα ο ι ά): non‐repeated faults due to random effects
like power supply disturbances, electromagnetic interference,
radiation e.t.c.
 Intermittent
I i ( ια ί ο τα):
) repeated d faults
f l d
due to the
h
degradation of the circuit parameters (wearout, aging).

VLSI Testing 13

Yield Loss and Yield Enhancement

• There are two types of yield loss in IC manufacturing:
 Catastrophic yield loss: due to random defects.
 Parametric
P t i yield
i ld loss:
l d to process variations.
due i i

• Yield enhancement techniques:

 Design for Manufacturability: layout design rule adaption in
order to improve the manufacturability.
 Design
D i forf Yield:
Yi ld process improvements
i t to
t enhance
h yield.
i ld
 Design for Diagnosis: techniques that provide access to
proper information in order to find the root cause of a failure.
This will help to improve the layout design and/or the
manufacturing process.
VLSI Testing 14

7
 Yield and Defect Level
The targets (from design and fabrication point of view) are:

number of defect free ICs

Yi ld (Υ)=
Yield (Υ) total number of fabricated ICs

Mathematical model:  
Y  1  e  AD / A  D 
2 A = die area
D = defect density

number of defective ICs that pass the test

Defect Level (DL)= total number ICs that pass the test

These are test escapes!

DL is measured in defective parts per million (DPM) – < 100 DPM  high quality
VLSI Testing 15

Fault Coverage
Given that the yield is a priori less than 1, it is a prerequisite of a testing
procedure to provide the highest possible fault coverage ( ά η σφα ά ).

number of detected faults

F lt Coverage
Fault C (T) =
total number of possible faults


Theoretical relation among defect level, fault coverage and yield:

DL  1  Y(1  T)

approximation for small

DL  (1  T)  ln( Y) values of DL

TT = (1‐T)
C = stuck‐at fault coverage

VLSI Testing 16

8
 Fault Detection
The detection of faults in a circuit consisting of many hundred‐millions up
to few billions of transistors is an open issue. Possible approaches:
• Application of all possible input combinations and observation of the
circuit responses.
responses
Impractical solution due to the huge number of all possible
combinations.
• Use of efficient algorithms for the generation of a reduced set (test
test
set)
set of input combinations (test test vectors)
vectors along with the
corresponding responses, which is capable to detect “all” possible
faults of the fault model under consideration.
Main strategy:
gy “divide and conquer”
q
• Assist testing with embedded design for testability (DfT) techniques.
Main strategy: “divide and conquer”

Desired fault coverage 100%.

In practice a fault coverage of 9099.9% is achieved depending on the fault model and the circuit under
test.

VLSI Testing 17

Testability
Testability is defined as a measure of the ability to detect the faults of the fault
model under consideration in a circuit under test (CUT). It depends on the:
• Controllability ( ι ότητα): is a measure of the ability to set a node in a
predefined logic state using proper primary input values (vectors).
• Observability (Πα ατη ησι ότητα): is a measure of the ability to
determine the logic state of a node by observing the circuit responses at
the primary outputs.

Fault free circuit Circuit with stuck‐at faults

Fault detection is a process where a fault is sensitized by applying proper values at the
primary inputs of the circuit, so that an error is generated at a circuit node, and
afterwards this error is propagated to a primary output to be observed.

VLSI Testing 18

9
 Re‐‐convergent Fan‐
Re Fan‐Out Points
The presence of re‐convergent fan‐out points (ση ί πα ασύ ισης
ση ά ) makes fault detection a hard task. This is due to the fact that in such
cases it is not always feasible to independently set proper values at various
circuit nodes in order to sensitize a fault and/or propagate the generated error
to a primary output.
In the example that follows, there is not any proper value for node B that will
sensitize the fault and in parallel will permit the propagation of the generated
error to the output E. The re‐convergent fan‐out point is node E.

Fault free circuit Circuit with stuck‐at faults

VLSI Testing 19

Control – Observation Points (Ι)

1 Combinational Logic
OP

W L
U W L
U

Original Circuit Observation Point Insertion

W L U W U
L

CP0 CP0
CP1
“0” Control Point Insertion “0” and “1” Control Point Insertion

VLSI Testing 20

10
 Control – Observation Points (ΙI
(ΙI)
Sequential Logic

D Q D Q
Flip Flop Initialization
Flip‐Flop
CLK Q CLK Q

CLR CLR

CP0

CP0
RCO
Mbit Nbit

CP1 Counter Initialization

VLSI Testing 21

Path Delay Fault Testing (I)

2
Latch Flip‐Flop
In
Logic Out In
Logic Out
D Q D Q D Q D Q
CK1 CK CK2 CK CK CK CK CK

Delay
Time
Delay
CK1 Time

CK2 CK

t t

VLSI Testing 22

11
 Path Delay Fault Testing (II)
0 In1 0 Out1
D Q D Q
CK
side path
CK
0
0
In2 D Q D Q Out2 0
CK CK
Logic
CK path under test CK

1 In1 1
D Q D Q Out1

CK
side p
path
1 CK

In2 D Q D Q Out2

CK CK
Logic
CK path under test CK

VLSI Testing 23

Path Delay Fault Testing (III)

1 In1 1 Out1
D Q D Q
CK
side path Fault‐free
CK
1 case

In2 D Q D Q Out2 0
CK CK Faulty
Logic case
CK path under test CK

V1 = <10> ← Ini alizing test vector

V2 = <11> ← Path ac va on test vector

A path delay fault requires at least a pair of subsequent test vectors to be detected.
The first test vector initializes the circuit while the second test vector activates the path
under test.

VLSI Testing 24

12
 Circuit Partitioning (I)
3
Initial Circuit

Sub‐circuit Sub‐circuit
C1 C2

Circuit Under Test

VLSI Testing 25

Circuit Partitioning (II)

(Τ η α οποίηση Κ ώ α ος)

Modified Circuit
SEL
1
M
U
0 X
Sub‐circuit Sub‐circuit
C1 1 C2
M
U
X
0

0 MUX
1 0 MUX
1

SEL
Testing C1 partition
“0” Strategy: “divide and conquer”
VLSI Testing 26

13
 Circuit Segmentation
(Κα ά ηση Κ ώ α ος)
S=“0”
A & C are transparent

A
S
S=“1”
Β is transparent 0
M
B U
S
1 X

0
M
U
1 X

VLSI Testing 27

Hard Task:
Task: Sequential Logic Testing
In sequential circuits the initial state
(register’s values) is not known by default .
outputs = f(inputs, state) Consequently, the sensitization of faults
and the propagation of the corresponding
erroneous responses turns to be a hard
Inputs task.
Combinational Outputs
Logic A solution is to use techniques for the
proper initialization of the circuit state to
known values.
• Application of proper test vector
sequences and/or the use of Set/Reset
Registers signals to setup the required state.
• Development of efficient techniques to
Clock set the initial state and observe the
“State
State””
subsequent state after the response of
the circuit.

VLSI Testing 28

14
 Design for Testability
Design for testability (DFT) techniques are today a common practice to meet the
reliability levels required in modern integrated circuits (ICs). According to this
approach, proper testing circuitry is embedded along with the functional circuit
under test ((CUT)) aimingg to alleviate the testingg p
process and enhance testability.
y

• Scan testing techniques ( εχ ι ές σειρια ής σάρωσης).

They provide full controllability and observability of the circuit’s internal states.
• Built‐In Self Test ‐ BIST techniques ( εχ ι ές ε σω α ω έ ο α οε έγχο ).
Proper circuits are embedded in an IC to enable its self‐testing. These circuits
provide test vectors to the circuit under test (CUT) and monitor its responses to
detect errors.
BIST circuits can be also exploited for on‐line testing.
• IDDQ testing (or current monitoring) techniques.
Power consumption is the criterion to discriminate defective from defect free
ICs.
• Test standards.
Existing test standards, like the ΙΕΕΕ 1149.1 and ΙΕΕΕ 1500, provide a common
way to perform testing procedures in nanometer ICs.

VLSI Testing 29

Scan Testing
Registers Logic
Scan‐In

Inputs Outputs

Clock
Scan‐Out

All the memory elements (latches or Flip‐Flops) are properly connected to form a unified
shift register (scan register). This way the internal state of the circuit is determined
(controlled) by shifting in (scan‐in) to the scan register the required test data to be
applied to the combinational logic. Moreover, the existing internal state (previous logic
response) can be observed by shifting out (scan‐out) the data stored into the scan
register.

VLSI Testing 30

15
 Built‐‐In Self Test (BIST)
Built
Chip
Inputs
Circuit Under Outputs

UX
MU
Test
(CUT)

Test Vector Control Response

Generator Unit Analyzer
BIST Circuitry
In built‐in self testing, the test vectors are generated by an embedded circuit (test
vector/pattern generator) under the control of the BIST controller. The circuit responses
are compacted by the response analyzer and the final result (signature) after the
completion of the testing procedure is compared with the expected result to make a
decision. In case of discrepancy, the BIST controller provides a proper signal to indicate
that the CUT is defective.
VLSI Testing 31

On‐‐Line Testing
On
Secondary
Error_Indication
Cosmic Ray
Detector

Si Transition
Detectors
  
+ +
+ + 
 +
+ + +
Inputs Outputs

Burst of Electronic Charge

1M electrons/ m Si

Clock
Circuit

In on‐line testing the circuit is under monitoring for error detection during its operation
in the field. Many techniques exist to correct these errors (e.g. by a retry procedure) in
order to provide error tolerance to the circuit under monitoring.

VLSI Testing 32

16
 Testing Protocols

Scan Register
IEEE 1149.1 std.

BSR
BSR

PI
CUT PO

Decoder
MUX‐1
User Registers

Dev. ID Register
Shift_DR
Clock_DR Bypass
Update_DR
Run_Test MUX‐2

Decode Logic TDO

FF
TDI
IR Register
Shift_IR
TCK Clock_IR
TMS TAP Update_IR
TRST Controller Reset

VLSI Testing 33

The SoC Test Challenge

Digital Tester
Functional Tester Logic Tester

TAP

P Logic P Logic

BIST
BIST

Mixed Memory Mixed Memory

Signal Signal

SoC BIST BIST SoC

Mixed‐Signal
Memory Tester
Tester
VLSI Testing 34

17