OPA725, OPA2725

OPA726, OPA2726
SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004

Very Low Noise, High-Speed, 12V CMOS

Operational Amplifier

FEATURES DESCRIPTION
D BANDWIDTH: 20MHz
The OPA725 and OPA726 series op amps use a
D SLEW RATE: 30V/µs
state-of-the-art 12V analog CMOS process, and combine
D FAST 16-BIT SETTLING TIME outstanding ac performance with low bias current and
D LOW NOISE: 6nV/√Hz (typ) at 100kHz excellent CMRR, PSRR, and AOL. The 20MHz
D EXCELLENT CMRR, PSRR, and AOL Gain-Bandwidth (GBW) Product is achieved by using a
D RAIL-TO-RAIL OUTPUT proprietary and patent-pending output stage design.
D CM RANGE INCLUDES GND These characteristics allow excellent 16-bit settling times
D THD+N: 0.0003% (typ) at 1kHz for driving 16-bit Analog-to-Digital converters (ADCs).
D QUIESCENT CURRENT: 5.5mA/ch (max)
Excellent ac characteristics, such as 20MHz GBW, 30V/µs
D SUPPLY VOLTAGE: 4V to 12V
slew rate and 0.0003% THD+N make the OPA725 and
D SHUTDOWN MODE (OPAx726): 6µA/ch OPA726 well-suited for communication, high-end audio,
and active filter applications. With a bias current of less
APPLICATIONS than 200pA, they are well-suited for use as
D OPTICAL NETWORKING transimpedance (I/V-conversion) amplifiers for monitoring
D TRANSIMPEDANCE AMPLIFIERS optical power in ONET applications.
D INTEGRATORS
The OPA725 and OPA726 op amps can be used in
D ACTIVE FILTERS single-supply applications from 4V up to 12V, or
D A/D CONVERTER BUFFERS dual-supply from ±2V to ±6V. The output swings to within
D I/V CONVERTER FOR DACs 150mV of the rails, maximizing dynamic range. The
D PORTABLE AUDIO shutdown versions (OPAx726) reduce the quiescent
D PROCESS CONTROL current to less than 6µA and feature a reference pin for
D TEST EQUIPMENT easy shutdown operation with standard CMOS logic in
dual-supply applications.
OPA725 RELATED PRODUCTS The OPA725 (single) is available in SOT23-5 and SO-8
FEATURES PRODUCT packages, and the OPA2725 (dual) is available in MSOP-8
10MHz, 16V, 16V/µs, 8.5nV/√Hz at 1kHz TLC080 and SO-8 packages. The OPA726 (single with shutdown)
8MHz, 36V, FET Input, 20V/µs, 8.5nV/√Hz at 1kHz OPA132 is available in MSOP-8 and SO-8. The OPA2726 (dual with
100MHz, 5.5V, Precision Transimpedance Amplifier OPA380 shutdown) is available in MSOP-10. All versions are
500MHz, ±5V, FET Input, 290V/µs, 7nV/√Hz at 100kHz OPA656 specified for operation from −40°C to +125°C.
7MHz, 12V, RRIO, 10V/µs, 30nV/√Hz at 10kHz OPA743
16-Bit, 250kSPS, 4-Channel, Parallel Output ADC ADS8342

+5V
+12V +5V

75Ω
OPA725 AIN
O PA726 VOUT VIN ADS8342
λ ±2.5V
330pF 16−Bit ADC

Enable −5V Common

−VB −5V

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

             
 Copyright  2003−2004, Texas Instruments Incorporated
                  

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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004

ORDERING INFORMATION
SPECIFIED
PACKAGE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD TEMPERATURE
DESIGNATOR(1) MARKING NUMBER MEDIA, QUANTITY
RANGE
Non-Shutdown
OPA725 SOT23-5 DBV −40°C to +125°C OALI OPA725AIDBVT Tape and Reel, 250
″ ″ ″ ″ ″ OPA725AIDBVR Tape and Reel, 3000
OPA725 SO-8 D −40°C to +125°C OPA725A OPA725AID Rails, 100
″ ″ ″ ″ ″ OPA725AIDR Tape and Reel, 2500
OPA2725 SO-8 D −40°C to +125°C OPA2725A OPA2725AID Rails, 100
″ ″ ″ ″ ″ OPA2725AIDR Tape and Reel, 2500
OPA2725 MSOP-8 DGK −40°C to +125°C BGM OPA2725AIDGKT Tape and Reel, 250
″ ″ ″ ″ ″ OPA2725AIDGKR Tape and Reel, 2500
Shutdown
OPA726 SO-8 D −40°C to +125°C OPA726A OPA726AID Rails, 100
″ ″ ″ ″ ″ OPA726AIDR Tape and Reel, 2500
OPA726 MSOP-8 DGK −40°C to +125°C BHC OPA726AIDGKT Tape and Reel, 250
″ ″ ″ ″ ″ OPA726AIDGKR Tape and Reel, 2500
OPA2726 MSOP-10 DGS −40°C to +125°C BHB OPA2726AIDGST Tape and Reel, 250
″ ″ ″ ″ ″ OPA2726AIDGSR Tape and Reel, 2500
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet.

This integrated circuit can be damaged by ESD. Texas ABSOLUTE MAXIMUM RATINGS(1)
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.2V
proper handling and installation procedures can cause damage. Signal Input Terminals, Voltage(2) . . . . . . . . . −0.5V to (V+) + 0.5V
Current(2) . . . . . . . . . . . . . . . . . . . ±10mA
ESD damage can range from subtle performance degradation to Output Short Circuit(3) . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
complete device failure. Precision integrated circuits may be more Operating Temperature . . . . . . . . . . . . . . . . . . . . . −55°C to +125°C
susceptible to damage because very small parametric changes could Storage Termperature . . . . . . . . . . . . . . . . . . . . . . −55°C to +150°C
cause the device not to meet its published specifications. Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . . . . . 1000 V
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
(2) Input terminals are diode-clamped to the power-supply rails.
Input signals that can swing more than 0.5V beyond the supply
rails should be current limited to 10mA or less.
(3) Short-circuit to ground, one amplifier per package.

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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004

PIN CONFIGURATIONS

OPA725 OPA726
OPA725

NC(1) 1 8 NC(1) DGND(2) 1 8 Enable

Out 1 5 V+
−IN 2 7 V+ −IN 2 7 V+
V− 2
+IN 3 6 OUT +IN 3 6 OUT
+IN 3 4 −IN
V− 4 5 NC(1) V− 4 5 NC(1)

SOT23−5
SO−8 SO−8, MSOP−8

OPA2725 OPA2726

OUT A 1 8 V+ OUT A 1 10 V+

−IN A 2 A 7 OUT B −IN A 2 A 9 OUT B

+IN A 3 B 6 −IN B +IN A 3 B 8 −IN B

V− 4 5 +IN B V− 4 7 +IN B

DGND(2) 5 6 Enable
SO−8, MSOP−8
MSOP−10

(1) NC denotes no internal connection.

(2) DGND = reference voltage for Enable Reference pin. Voltage on this pin
will be the voltage to which the Enable Reference pin is referenced.

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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004

ELECTRICAL CHARACTERISTICS: VS = +4V to +12V or VS = ±2V to ±6V

Boldface limits apply over the specified temperature range, TA = −40°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
OPA725, OPA726, OPA2725, OPA2726
PARAMETER CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
Input Offset Voltage VOS
OPA725, OPA726 VS = ±6V, VCM = 0V 1.2 3 mV
OPA2725, OPA2726 VS = ±6V, VCM = 0V 1.5 5 mV
Drift dVOS/dT 4 µV/°C
vs Power Supply PSRR VS = ±2V to ±6V, VCM = V− 30 100 µV/V
Over Temperature VS = ±2V to ±6V, VCM = V− 150 mV/V
Channel Separation, DC 1 µV/V
INPUT BIAS CURRENT
Input Bias Current IB 30 200 pA
Over Temperature See Typical Characteristics
Input Offset Current IOS 10 50 pA
NOISE
Input Voltage Noise, f = 0.1Hz to 10Hz en VS = ±6V, VCM = 0V 10 µVPP
Input Voltage Noise Density, f = 10kHz en VS = ±6V, VCM = 0V 10 nV/√Hz
Input Voltage Noise Density, f = 100kHz en VS = ±6V, VCM = 0V 6 nV/√Hz
Input Current Noise Density, f = 1kHz in VS = ±6V, VCM = 0V 2.5 fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range VCM (V−) (V+) − 2 V
Common-Mode Rejection Ratio CMRR (V−) ≤ VCM ≤ (V+) − 2V 88 94 dB
Over Temperature (V−) ≤ VCM ≤ (V+) − 2V 84 dB
(V−) ≤ VCM ≤ (V+) − 3V 94 100 dB
Over Temperature (V−) ≤ VCM ≤ (V+) − 3V 84 dB
INPUT IMPEDANCE
Differential 1011 5 Ω pF
Common-Mode 1011 4 Ω pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain AOL
OPA725, OPA726 RL = 100kΩ, 0.15V < VO < (V+) − 0.15V 110 120 dB
Over Temperature RL = 100kΩ, 0.15V < VO < (V+) − 0.15V 100 dB
OPA2725, OPA2726 RL = 100kΩ, 0.175V < VO < (V+) − 0.175V 110 120 dB
Over Temperature RL = 100kΩ, 0.175V < VO < (V+) − 0.175V 100 dB
OPA725, OPA726 RL = 1kΩ, 0.25V < VO < (V+) − 0.25V 106 116 dB
Over Temperature RL = 1kΩ, 0.25V < VO < (V+) − 0.25V 96 dB
OPA2725, OPA2726 RL = 2kΩ, 0.25V < VO < (V+) − 0.25V 106 116 dB
Over Temperature RL = 2kΩ, 0.25V < VO < (V+) − 0.25V 96 dB
FREQUENCY RESPONSE CL = 20pF
Gain-Bandwidth Product GBW 20 MHz
Slew Rate SR G = +1 30 V/µs
Settling Time, 0.1% tS VS = ±6V, 5V Step, G = +1 350 ns
0.01% VS = ±6V, 5V Step, G = +1 450 ns
Overload Recovery Time VIN • Gain > VS 50 ns
Total Harmonic Distortion + Noise THD+N VS = ±6V, VOUT = 2VRMS, RL = 600Ω, 0.0003 %
G = +1, f = 1kHz

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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004

ELECTRICAL CHARACTERISTICS: VS = +4V to +12V or VS = ±2V to ±6V (continued)

Boldface limits apply over the specified temperature range, TA = −40°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
OPA725, OPA726, OPA2725, OPA2726
PARAMETER CONDITIONS MIN TYP MAX UNIT
OUTPUT
Voltage Output Swing from Rail
OPA725, OPA726 RL = 100kΩ, AOL > 110dB 100 150 mV
Over Temperature RL = 100kΩ, AOL > 100dB 150 mV
OPA2725, OPA2726 RL = 100kΩ, AOL > 110dB 125 175 mV
Over Temperature RL = 100kΩ, AOL > 100dB 175 mV
OPA725, OPA726 RL = 1kΩ, AOL > 106dB 200 250 mV
Over Temperature RL = 1kΩ, AOL > 96dB 250 mV
OPA2725, OPA2726 RL = 2kΩ, AOL > 106dB 200 250 mV
Over Temperature RL = 2kΩ, AOL > 96dB 250 mV
Output Current IOUT  VS − VOUT < 1V 40 mA
Short-Circuit Current ISC ±55 mA
Capacitive Load Drive CLOAD See Typical Characteristics
Open-Loop Output Impedance f = 1MHz, IO = 0 40 Ω
ENABLE/SHUTDOWN (OPAx726)
tOFF 5 µs
tON 30 µs
Enable Reference (DGND) Voltage Range VDGND V− (V+) − 2 V
VL (shutdown) < VDGND +0.8V V
VH (amplifier is active) > VDGND +2V V
Input Disable Current Ref Pin = Enable Pin = V− 5 µA
IQSD (per amplifier) 6 15 µA
POWER SUPPLY
Specified Voltage Range VS 4 12 V
Operating Voltage Range VS 3.5 to 13.2 V
Quiescent Current (per amplifier) IQ IO = 0 4.3 5.5 mA
Over Temperature 6 mA
TEMPERATURE RANGE
Specified Range −40 125 °C
Operating Range −55 125 °C
Storage Range −55 150 °C
Thermal Resistance qJA
SOT23-5 200 °C/W
MSOP-8, MSOP-10, SO-8 150 °C/W

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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004

TYPICAL CHARACTERISTICS
At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.

COMMON−MODE REJECTION RATIO vs FREQUENCY

GAIN AND PHASE vs FREQUENCY
180 180 120

160 160
100
140 140
120 Phase 120 80

CMRR (dB)
Phase (_)
Gain (dB)

100 100
80 80 60
60 Gain 60
40 40 40

20 20
20
0 0
(V−) ≤ VCM ≤ (V+) − 2V
−20 −20 0
10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M
Frequency (Hz)
Frequency (Hz)

POWER−SUPPLY REJECTION RATIO vs FREQUENCY MAXIMUM OUTPUT VOLTAGE vs FREQUENCY

100 7
VS = ±6V
90
6
80
70 5
Amplitude (V)
PSRR (dB)

60 4
50
3
40
30 Indicates maximum output
2
for no visible distortion.
20
1
10
0 0
100 1k 10k 100k 1M 10M 100M 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

CHANNEL SEPARATION vs FREQUENCY INPUT VOLTAGE NOISE SPECTRAL DENSITY

140 vs FREQUENCY
1000

120
Channel Separation (dB)

Voltage Noise (nV/√Hz)

100
100

80

60
10

40

20
1k 10k 100k 1M 10M 100M 1
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
Frequency (Hz)

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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004

TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.

INPUT BIAS CURRENT vs COMMON −MODE VOLTAGE OFFSET CURRENT vs TEMPERATURE

100k 10k
+125_C
10k
1k
1k
Input Bias Current (pA)

+85_C
100 100
+25_ C

IOS (pA)
10
IB < ±10pA 10
−10
+25_C
−100 1
−1k
+85_ C 0.1
−10k
+125_ C
−100k 0.01
−50 −25
−6.5

−5.5

−4.5

−3.5

−2.5

−1.5

−0.5

0 25 50 75 100 125 150

0.5

1.5

2.5

3.5

4.5

5.5

6.5
Temperature (_ C)
Common−Mode Voltage (V)

OPEN−LOOP GAIN vs TEMPERATURE POWER−SUPPLY REJECTION RATIO vs TEMPERATURE

140 120

130
RL = 100kΩ
120 100
PSRR (dB)
AOL (dB)

110

RL = 1kΩ
100 80

90

80 60
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
Temperature (_ C) Temperature (_C)

COMMON−MODE REJECTION RATIO vs TEMPERATURE QUIESCENT CURRENT vs TEMPERATURE

110 5

100 4
CMRR (dB)

3
IQ (mA)

90

80 2

70 1

(V−) ≤ VCM ≤ (V+) − 2V

60 0
−50 −25 −50 −25 0 25 50 75 100 125 150
0 25 50 75 100 125 150
Temperature (_ C) Temperature (_C)

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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004

TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.

QUIESCENT CURRENT vs SUPPLY VOLTAGE SHORT−CIRCUIT CURRENT vs TEMPERATURE

5.0 90
4.8 80
Sourcing
4.6 70
I Q per Amplifier (mA)

Short−Circuit (mA)
4.4 60
4.2
50
4.0 Sinking
40
3.8
30
3.6
20
3.4
3.2 10

3.0 0
3 4 5 6 7 8 9 10 11 12 13 14 −50 −25 0 25 50 75 100 125 150
Supply Voltage (V) Temperature (_ C)

SHORT−CIRCUIT CURRENT vs SUPPLY VOLTAGE

90 OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
6
Sourcing −40_ C
80
Short−Circuit Current (mA)

70 4
Output Voltage (V)

60
2
50 Sinking
125_C 25_C
40 0

30
−2
20

10 −4
−40_C
0
−6
3.5

4.5

5.5

6.5

7.5

8.5

9.5

10.5

11.5

12.5

13.5

0 10 20 30 40 50 60 70 80
Output Current (mA)
Supply Voltage (V)

TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY SETTLING TIME vs GAIN

0.01 5000
RL = 600Ω
4500
VOUT = 2Vrms
BW = 80kHz 4000
3500
Settling Time (ns)
THD + Noise (%)

3000

0.001 2500
2000
1500
0.01%
1000
0.1%
500

0.0001 0
10 100 1k 10k 100k 1 10 100
Frequency (Hz) Noninverting Gain (V/V)

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.

OFFSET VOLTAGE PRODUCTION DISTRIBUTION

SMALL−SIGNAL OVERSHOOT vs CAPACITIVE LOAD
90

80
70
Overshoot (%)

60

Population
G = +1
50
40

30 G = −1
CF = 3pF
20
G = +5
10
CF = 1pF
0

−3.3
−3.0
−2.7
−2.4
−2.1
−1.8
−1.5
−1.2
−0.9
−0.6
−0.3
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
10 100 1000
Capacitive Load (pF)
Offset Voltage (mV)

VOLTAGE OFFSET DRIFT PRODUCTION DISTRIBUTION

SMALL−SIGNAL STEP RESPONSE
Typical production distribution
of packaged units. G = +1
RL = 10kΩ
CL = 20pF
Population

10mV/div

0 2 4 6 8 10 12 14 16
100ns/div
Voltage Offset Drift (µV/_C)

LARGE−SIGNAL STEP RESPONSE SMALL−SIGNAL STEP RESPONSE

G = +1 CF = 2pF CF = 3pF
RL = 10kΩ
CL = 20pF

CF = 4pF
10mV/div
1V/div

CF
G = −1
RF
10kΩ

10kΩ

O P A 7 25
CL
20pF

400ns/div 200ns/div

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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004

TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.

LARGE−SIGNAL STEP RESPONSE

CF
1V/div

4pF G = −1
RF
10kΩ

10kΩ

OPA725
CL
20pF

400ns/div

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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004

APPLICATIONS INFORMATION a) Single−Supply Configuration

OPA725 and OPA726 series 20MHz CMOS op amps have
a fast slew rate, low noise, and excellent PSRR, CMRR, Enable

and AOL. These op amps can operate on typically 4.3mA Digital +12V

quiescent current from a single (or split) supply in the range Logic

of 4V to 12V (±2V to ±6V), making them highly versatile OPA726 VOUT

and easy to use. They are stable in a unity-gain

configuration. DGND
Power-supply pins should be bypassed with 1nF ceramic
capacitors in parallel with 1µF tantalum capacitors.

OPERATING VOLTAGE b) Dual−Supply Configuration

OPA725 series op amps are specified from 4V to 12V Enable

supplies over a temperature range of −40°C to +125°C. Digital +5V
They will operate well in ±5V or +5V to +12V power-supply Logic
systems. Parameters that vary significantly with operating OPA726 VOUT
voltage or temperature are shown in the Typical
Characteristics. −5V
DGND

ENABLE/SHUTDOWN
OPA725 series op amps require approximately 4.3mA
quiescent current. The enable/shutdown feature of the Figure 1. Enable Reference Pin Connection for
OPA726 allows the op amp to be shut off to reduce this Single- and Dual-Supply Configurations
current to approximately 6µA.
The enable/shutdown input is referenced to the Enable INPUT OVER-VOLTAGE PROTECTION
Reference Pin, DGND (see Pin Configurations). This pin
can be connected to logic ground in dual-supply op amp Device inputs are protected by ESD diodes that will
configurations to avoid level-shifting the enable logic conduct if the input voltages exceed the power supplies by
signal, as shown in Figure 1. more than approximately 300mV. Momentary voltages
greater than 300mV beyond the power supply can be
The Enable Reference Pin voltage, VDGND, must not
tolerated if the current is limited to 10mA. This is easily
exceed (V+) − 2V. It may be set as low as V−. The amplifier accomplished with an input resistor in series with the op
is enabled when the Enable Pin voltage is greater than amp, as shown in Figure 2. The OPA725 series features
VDGND + 2V. The amplifier is disabled (shutdown) if the
no phase inversion when the inputs extend beyond
Enable Pin voltage is less than VDGND + 0.8V. The Enable
supplies, if the input is current limited.
Pin is connected to internal pull-up circuitry and will enable
the device if left unconnected.

COMMON-MODE VOLTAGE RANGE IOVERLOAD

V+

The input common-mode voltage range of the OPA725 10mA max

and OPA726 series extends from V− to (V+) − 2V. VOUT
R OPA725
Common-mode rejection is excellent throughout the input VIN
voltage range from V− to (V+) − 3V. CMRR decreases
V−
somewhat as the common-mode voltage extends to
(V+) − 2V, but remains very good and is tested throughout
this range. See the Electrical Characteristics table for Figure 2. Input Current Protection for Voltages
details. Exceeding the Supply Voltage

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RAIL-TO-RAIL OUTPUT
+5V
+5V
A class AB output stage with common-source transistors
is used to achieve rail-to-rail output. This output stage is 75Ω
capable of driving heavy loads connected to any point VIN
OPA725 AIN
ADS8342
between V+ and V−. For light resistive loads ( > 100kΩ ), ±2.5V 330pF 16−Bit ADC
the output voltage can swing to 150mV (175mV for dual) −5V Common
from the supply rail, while still maintaining excellent
linearity (AOL > 110dB). With 1kΩ (2kΩ for dual) resistive −5V
loads, the output is specified to swing to within 250mV from
the supply rails with excellent linearity (see the Typical
Characteristics curve Output Voltage Swing vs Output
Figure 4. OPA725 Driving an ADC
Current).

CAPACITIVE LOAD AND STABILITY TRANSIMPEDANCE AMPLIFIER

Capacitive load drive is dependent upon gain and the
Wide bandwidth, low input bias current, and low input
overshoot requirements of the application. Increasing the
voltage and current noise make the OPA725 an ideal
gain enhances the ability of the amplifier to drive greater
wideband photodiode transimpedance amplifier. Low-
capacitive loads (see the Typical Characteristics curve
voltage noise is important because photodiode capaci-
Small-Signal Overshoot vs Capacitive Load).
tance causes the effective noise gain of the circuit to
One method of improving capacitive load drive in the increase at high frequency.
unity-gain configuration is to insert a 10Ω to 20Ω resistor
inside the feedback loop, as shown in Figure 3. This The key elements to a transimpedance design, as shown
reduces ringing with large capacitive loads while in Figure 5, are the expected diode capacitance (CD),
maintaining DC accuracy. which should include the parasitic input common-mode
and differential-mode input capacitance (4pF + 5pF for the
OPA725); the desired transimpedance gain (RF); and the
GBW for the OPA725 (20MHz). With these three variables
V+ set, the feedback capacitor value (CF) can be set to control
RS the frequency response. CF includes the stray capacitance
20Ω
OPA725 VOUT
of RF, which is 0.2pF for a typical surface-mount resistor.
VIN
CL RL

CF(1)
< 1pF

Figure 3. Series Resistor in Unity-Gain Buffer

Configuration Improves Capacitive Load Drive
RF
10MΩ
DRIVING FAST 16-BIT ADCs
The OPA725 series is optimized for driving fast 16-bit
ADCs such as the ADS8342. The OPA725 op amps buffer
+5V
the converter input capacitance and resulting charge
injection, while providing signal gain. Figure 4 shows the λ
OPA725 in a single-ended method of interfacing to the CD OPA725 VOUT
ADS8342 16-bit, 250kSPS, 4-channel ADC with an input
range of ±2.5V. The OPA725 has demonstrated excellent
settling time to the 16-bit level within the 600ns acquisition −5V

time of the ADS8342. The RC filter, shown in Figure 4, has

been carefully tuned for best noise and settling
NOTE: (1) CF is optional to prevent gain peaking.
performance. It may need to be adjusted for different op It includes the stray capacitance of RF.
amp configurations. Please refer to the ADS8342 data
sheet (available for download at www.ti.com) for additional
information on this product. Figure 5. Dual-Supply Transimpedance Amplifier
12
 
"#$% 
#"#$

"#&% 
#"#&
www.ti.com
SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004

To achieve a maximally-flat, 2nd-order Butterworth For additional information, refer to Application Bulletin
frequency response, the feedback pole should be set to: SBOA055, Compensate Transimpedance Amplifiers
1
2pR FCF
+ Ǹ4pR
GBW
C F D (1)
Intuitively, available for download at www.ti.com.

OPTIMIZING THE TRANSIMPEDANCE

Bandwidth is calculated by: CIRCUIT

f *3dB + Ǹ2pR
GBW Hz
C F D (2)
To achieve the best performance, components should be
selected according to the following guidelines:
1. For lowest noise, select RF to create the total required
For even higher transimpedance bandwidth, the
gain. Using a lower value for RF and adding gain after
high-speed CMOS OPA354 (100MHz GBW), OPA300
the transimpedance amplifier generally produces
(180 MHz GBW), OPA355 (200MHz GBW), or OPA656,
poorer noise performance. The noise produced by RF
OPA657 (400MHz GBW) may be used.
increases with the square-root of RF, whereas the
For single-supply applications, the +IN input can be biased signal increases linearly. Therefore, signal-to-noise
with a positive dc voltage to allow the output to reach true ratio is improved when all the required gain is placed
zero when the photodiode is not exposed to any light, and in the transimpedance stage.
respond without the added delay that results from coming
2. Minimize photodiode capacitance and stray
out of the negative rail. (Refer to Figure 6.) This bias
capacitance at the summing junction (inverting input).
voltage also appears across the photodiode, providing a
This capacitance causes the voltage noise of the op
reverse bias for faster operation.
amp to be amplified (increasing amplification at high
frequency). Using a low-noise voltage source to
CF(1) reverse-bias a photodiode can significantly reduce its
< 1pF capacitance. Smaller photodiodes have lower
capacitance. Use optics to concentrate light on a small
photodiode.
RF 3. Noise increases with increased bandwidth. Limit the
10MΩ circuit bandwidth to only that required. Use a capacitor
across the RF to limit bandwidth, even if not required
for stability.
V+ 4. Circuit board leakage can degrade the performance of
an otherwise well-designed amplifier. Clean the circuit
λ board carefully. A circuit board guard trace that
OPA725 VOUT
encircles the summing junction and is driven at the
+VBias
same voltage can help control leakage.
For additional information, refer to the Application Bulletins
Noise Analysis of FET Transimpedance Amplifiers
NOTE: (1) CF is optional to prevent gain peaking.
(SBOA060), and Noise Analysis for High-Speed Op Amps
It includes the stray capacitance of RF. (SBOA066), available for download at the TI web site.

Figure 6. Single-Supply Transimpedance

Amplifier

13

"#$% 
#"#$

"#&% 
#"#&
www.ti.com
SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004

C3
C1 2.2nF
1nF

R3 R4 1/2
R1 R2 2.07kΩ 22.3kΩ OPA2725 VOUT
1/2
1.93kΩ 15.9kΩ OPA2725

C4
C2 100pF
330pF

DC Gain = 1
Cutoff Frequency = 50kHz

NOTE: FilterPro is a low-pass filter design program available for download at no cost from TI’s web site (www.ti.com). The program can be used
to determine component values for other cutoff frequencies or filter types.

Figure 7. Four-Pole Butterworth Sallen-Key Low-Pass Filter

14
 PACKAGE OPTION ADDENDUM

www.ti.com 6-May-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA2725AID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA Samples
2725A
OPA2725AIDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA Samples
2725A
OPA2725AIDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 BGM Samples

OPA2725AIDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green Call TI | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 BGM Samples

OPA2725AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA Samples
2725A
OPA2726AIDGST ACTIVE VSSOP DGS 10 250 RoHS & Green Call TI | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 BHB Samples

OPA2726AIDGSTG4 ACTIVE VSSOP DGS 10 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 BHB Samples

OPA725AID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA Samples
725A
OPA725AIDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OALI Samples

OPA725AIDBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OALI Samples

OPA725AIDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OALI Samples

OPA725AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA Samples
725A
OPA726AID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA Samples
726A
OPA726AIDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green Call TI | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 BHC Samples

OPA726AIDGKTG4 ACTIVE VSSOP DGK 8 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 BHC Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-May-2022

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2725AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA725AIDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA725AIDBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA725AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2725AIDR SOIC D 8 2500 356.0 356.0 35.0
OPA725AIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
OPA725AIDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
OPA725AIDR SOIC D 8 2500 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
OPA2725AID D SOIC 8 75 506.6 8 3940 4.32
OPA2725AIDG4 D SOIC 8 75 506.6 8 3940 4.32
OPA725AID D SOIC 8 75 506.6 8 3940 4.32
OPA726AID D SOIC 8 75 506.6 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
DGS0010A SCALE 3.200
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
TYP SEATING PLANE
4.75

A PIN 1 ID 0.1 C
AREA

8X 0.5
10
1

3.1
2.9 2X
NOTE 3 2

5
6
0.27
10X
0.17
3.1 0.1 C A B 1.1 MAX
B
2.9
NOTE 4

0.23
TYP
SEE DETAIL A 0.13

0.25
GAGE PLANE

0.7 0.15
0 -8 0.05
0.4

DETAIL A
TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
10X (0.3) SYMM (R0.05)
1 TYP
10

SYMM

8X (0.5) 5 6

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
SYMM (R0.05) TYP
10X (0.3)
1
10

SYMM
8X (0.5)

5 6

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221984/A 05/2015
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 (1.1) TYP
0.00
1.45
0.90

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

ALTERNATIVE PACKAGE SINGULATION VIEW

4214839/J 02/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/J 02/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/J 02/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DGK0008A SCALE 4.000
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
TYP
A 4.75
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A
0.25
GAGE PLANE

1.1 MAX

0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20

TYPICAL

4214862/A 04/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

www.ti.com
 EXAMPLE BOARD LAYOUT
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

SYMM
8X (1.4) (R0.05) TYP

8X (0.45) 1 8

SYMM

6X (0.65)
5
4

SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214862/A 04/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

SYMM

8X (1.4) (R0.05) TYP

8X (0.45) 1 8

SYMM

6X (0.65)
5
4

(4.4)

SOLDER PASTE EXAMPLE

SCALE: 15X

4214862/A 04/2023
NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
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