Electronics Circuit Design Lab Lab#05

Lab # 05
Common Source Amplifier
Objective:

To experimentally an theoretically analyze the characteristics of common source amplifier.

Apparatus:

• Capacitors
• Resistors
• JFET(2N5456)
• Connecting wires
• DMM
• Breadboard

JFET Amplifier Operation:

A transistor is a semiconductor device that uses a low-power electrical signal to control current
flow. Bipolar and field-effect transistors can be loosely categorized into two basic categories. We
looked at bipolar transistors in the last chapter, which use a little current to control a large
current, and then we concentrated on one specific kind, the junction field-effect transistor. The
insulated gate variant of field-effect transistors will be covered in more detail in the following
chapter. Field-effect transistors in general are unipolar, not bipolar, devices. That is, either
electrons via an N-type semiconductor or holes through a P-type semiconductor make up the
majority of the current flowing through them. When the device's physical diagram is seen, this is
made clearer.

Drain Characteristics:
Drain Characteristics of JFET with VG = 0:

A circuit for determining the drain current versus drain-source voltage characteristics of n
channel JFET with VGS = 0. VDS is increased in convenient steps from zero, and ID is measured
at each VDS level. This produces a table of ID/VDS values for plotting the characteristic

Working:
• The input signals gate-to-source (VGS) to swing above and below the Q-point (VGSQ)
causing a swing in drain current.

Aleen Qureshi 1 UW-21-MTS-BSC-016

Electronics Circuit Design Lab Lab#05

• At the drain current increases the voltage drop across, the voltage drop across RD also
increases.
• Which will cause ID to decrease.
• The drain current to swings below and above Q-point value in the phase with VGS
• The VGS is out phase of 180 degree to the VGS

Transfer Characteristics of JFET:

Transfer Characteristics of JFET are a plot of ID versus VGS. The gate-source voltage of a FET
controls the level of the drain current, so, the transfer characteristic shows how ID is controlled by
VGS. As illustrated in Fig. 9-13(a), the transfer characteristic extends from ID = IDSS at VGS = 0, to
ID = 0 at VGS = Vp. Referring to the JFET Characteristics, it is seen that when VDS = 0, ID = 0.
There is no channel voltage drop, so the voltage between the gate and all points on the channel is
zero, and there is no depletion region penetration. When VDS is increased by a small amount (less
than 1 V), a small drain current flows producing some voltage drop along the channel. This results
in some depletion penetration of the channel (as explained for Fig. 9-6), but it is so small that it
has no significant effect on the channel resistance. With further small increases in VDS the drain
current increase is approximately linear, and the channel behaves as an almost constant-value
resistance.

Aleen Qureshi 2 UW-21-MTS-BSC-016

Electronics Circuit Design Lab Lab#05

Above figure shows that a circuit for experimentally determining a table of quantities for plotting
the transfer characteristic of a given FET. The drain-source voltage is maintained constant, VGS is
adjusted in convenient step, and the corresponding levels of VGS and ID are recorded. The
characteristic shows that, as -VGS is increased, ID is progressively reduced from IDSS at VGS = 0, to
ID = 0 at VGS = -Vp

The transfer characteristic for a FET can be derived from the drain characteristics. A line is drawn
vertically on the drain characteristics to represent a constant VDS level. The corresponding ID and
VGS values along this line are noted and then used to plot the transfer characteristic

Task:

Procedure:
1. In the very first step we take all the required components and identified them.
2. In the next step we identify the gate drain and source of JFET.
3. Then we placed the transistor in the breadboard
4. Then we connect the VDD power supply to is drain transistor.
5. Then we applied input to the gate and output is taken from drain
6. Now we apply the +10 V VDD.
7. Now we apply the +5V input to the circuit.
8. Now we Note the output voltage on the oscilloscope.
9. Amplified voltage will be drawn to the output.

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Electronics Circuit Design Lab Lab#05

Conclusion:

Safety Precautions:
• Don’t interfere with lab equipment.
• Do not touch the electrical components.
• Do not meddle with others.
• Be careful while handling the power supply and other current sources.
• Do not exceed voltage limits for the components because they can burn.
• Return all the equipment after performing the experiment.

Aleen Qureshi 4 UW-21-MTS-BSC-016