Faculty of Information and Communication Technology (FICT)

Timer Chip: 8253/8254: Functions

Dividing clock frequency

Generates accurate time delays

Used in applications as…
UCCE2043 Basic Microprocessor  A real-time clock, an event counter, a square wave generator or
a complex waveform generator
8088/86 Programmable
Includes three identical 16 bits down counters that can
operate independently in any one of the six modes.
Interval Timer  To operate a counter, a 16 bit count is loaded in its register and
the register begins to decrement the count until it reaches 0. At
the end it generates a pulse.
H Y Lee
The counter can count either in BCD or Binary.
[email protected]
Input clock frequency from pin CLK

Models
 8253: 2 MHz, 8254: 8 MHz, 8254-2: 10 MHz
 8254 superseded its predecessor 8253
1 2

BLOCK DIAGRAM & PIN

CONFIGURATIONS
8253/8254 : Pins

CLK - Input clock frequency.

OUT - Programmable output frequency.
 Output = Clock or Pulse

GATE – enable or disable the counter.
 +5V – enables the counter and vice versa.

 Note: Initialization required before use!

8254 PROGRAMMABLE INTERVAL TIMER datasheet
3 4
 Accessing The Registers of The 8253/4
Addressing 8253/4

5 From the book The 8088 and 8086 Microprocessors by Triebel and Singh. 6
Pg 510

Control Word - I Control Word (II) – Reading Count Register

Counter Latching Command Format
Content of Count Register can be read
by at any time

Approach 1:
 Simply read with input instruction
 Must first set GATE# = 0 to inhibit
the count to ensure valid reading

Approach 2: On the Fly
 Command must first be issued to
the Control Register to capture the
current value of count to temporary
internal storage register.
 D5 and D4 = 0, D0-D3 = Don’t care

7 8
 Control Word (III) - Read Back Mode (I) Control Word (III) - Read Back Mode (II)
Read-Back Command Format

Permits programmer to capture
the current count values and
status information of all three
counters with a single command.
 D7 and D6 must be 1

Example:
 To capture the values in all
three counters

DE16 or 110111102 must
Status Byte (RD = 0; to be read by CPU) be written into the Control
Word Register.

Programmer must next
read these values by
issuing read commands for
the individual counters

Slide 7
9 From the book The 8088 and 8086 Microprocessors by Triebel and Singh. 10
Pg 514

Example Example (cont’)

From the book The 80x86 IBM PC by Muhammad

From the book The 80x86 IBM PC by Muhammad 11 12
Ali Mazidi pg. 390
Ali Mazidi pg. 389
 8253 Decoding in PC PC Board

13 14

Timers in PC 8253/8254 : Counting in Mode 0-5 & GATE# Inputs

Counter 0 GATE# Input (G) Signal Status
Modes
 To IRQ0 – TOD (time of day)
Low or going low Rising High
 O/p 18.2 Hz (1.193 MHz / 65536)
Mode 0 Disables counting -- Enables counting
 Mode 3, control word: 36H

Counter 1 1) Initiates counting
Mode 1 -- 2) Resets output --
 For DRAM refresh – using DMA (at least after next clock
every .015ms)
 2 ms / 128 rows = .015 ms (.015ms =
66278Hz1.193/18) 1) Disables counting
1) Reloads counter
Mode 2 2) Sets output Enables counting
2) Initiates counting
 Mode 2, control word: 54H immediately high

Counter 2
 To speaker and PC5 of 8255 1) Disables counting
Mode 3 2) Sets output Initiates counting Enables counting
 896 Hz (1.193MHz / 1331) immediately high
 Mode 3, control word: B6H
 GATE2 is connected to PB0 (port 61H) Mode 4 Disables counting -- Enables counting

Mode 5 -- Initiates counting --

15 16
 Mode 0 (Interrupt on Terminal Count)
Mode 0 (cont’)

Used to generate an interrupt to the microprocessor after a certain
interval of time has elapsed.

Low for (N+1)*T then high (Remain high until new control word or
Mode 0: An events counter enabled with G.
count number)
The output becomes a logic 0 when the control
 N (clock pulses) = Count Number (pre-programmed in count register)
 T (seconds) = Clock period
word is written and remains there until n plus the

Assume GATE=1, CLK=10MHz and the clock count N=9,999 number of programmed counts.
F = 10MHz = 107 MHz
T = 1/f = 10-7 s
(N+1)*T = 104 x 10-7 s n
= 103 x 10-6 s
= 1000 µs

Delay 400 µs

=>OUT1 rise after

1000+400=1400 µs
17 18

Mode 1 (Programmable One Shot) Mode 1 (cont’)

Hardware trigger-able one shot
Mode 1: One-shot mode.

OUT# will be low for N*T after a 0 to 1 transition on GATE#  Produces a single pulse at output

The G input triggers (when switches from 0 to 1) the
counter to output a 0 pulse for a duration of “count”
clocks.

Retrigger-able
 Counter reloaded if G is pulsed again within the first count.
 Pulse width will be extended.

19 20
 Mode 2 (Rate Generator) Mode 2 (cont’)

Operate as divide by N counter
Mode 2: Counter generates a series of pulses
 N = Value of the count loaded into the counter (negative) of 1 clock pulse wide.

As long as GATE# = 1,
The separation between pulses is determined
 OUT# will be high for N*T and Low for 1*T
by the count.

The cycle is repeated until reprogrammed or G
pin set to 0.

21 22

Mode 3 (Square Wave Rate Generator) Mode 3 (cont’)

Output is a square wave with 50% duty cycle whenever the counter
is loaded with an even number (N).
 Output = Low N/2 and High N/2

IF N = odd
Mode 3: Generates a continuous square-
 Output High for (N+1)/2 wave when G is set to 1.
 Output Low for (N-1)/2

If count is even, 50% duty cycle otherwise
OUT is high 1 cycle longer.

23 24
Mode 4 (Software Triggered Strobe Counter) Mode 4 (cont’)

GATE# input needs to be logic 1 for counter to function

Starts upon loading the count

High for (N+1) clock pulses, low for 1 clock pulse and
Mode 4: Software triggered one-shot (G
then high again must be 1).

Similar to Mode 2 except the counter is not automatically
reloaded

6
601

601

25 26

8254 & Operating Modes Summary

Mode 5 (Hardware Triggered Strobe)

Similar to Mode 4 except that counting is initiated by a signal at the
GATE# input.
 Initiated by 0 to 1 pulse on GATE#

OUT# switches to logic 0 N clock pulses after GATE# becomes
active.

If CLK=1MHz and N=400

27 28
 Solution
Example
First, we need to determine the base address of the 82C54. the base address,
which is also the address of counter 0, is determined with A1A0 set to 00.

In the figure we find that to select the 8254, /CS must be logic 0. This requires

Write an instruction that
sequence to set up the A15 -> A2 = 000000000010000
three counters of the
Combining this part of the address with the 00 at A1A0, gives the base address
82C54 in the Figure beside, as
0000000001000000=40H
as follows:
 Counter 0 = Binary counter
Since the base address of the 8254 is 40H, and to select the mode register
operating in mode 0 with an requires A1A0 =11, its address is 43H. Similarly, the three counters 0, 1, and 2
are at addresses 40H, 41H, 42H, respectively. Let us first determine the mode
initial value of 1234H. words for the three counters. We get
 Counter 1 = BCD counter Mode word for counter 0 = 00110000 = 30H
operating in mode 2 with an Mode word for counter 1 = 01110101 = 75H
initial value of 0100H. Mode word for counter 2 = 10111000 = B8H

 Counter 2: Binary counter
The following instruction sequence can be used to set up the 8254 with the
operating in mode 4 with an desired mode words and counts:
initial value of 1FFFH.

From the book The 808 and 8086 by Walter A.

29 30
Triebel pg. 511

Solution Example
MOV AL,30H ;Set up counter 0 mode Program counter 1 of the 8254 so that it generates a
OUT 43H,AL
MOV AL,75H ;Set up counter 1 mode continuous series of pulses that have a high time of
OUT 43H,AL 100us and a low time of 1us. Make sure to indicate the
MOV AL,0B8H ;Set up counter 2 mode CLK frequency required for this task. USING A 1MHZ
OUT 43H,AL
MOV AL,1234H ;Initialize counter 0 with 1234H CLOCK
OUT 40H,AL
MOV AL,12H
OUT 40H,AL
MOV AL,0100H ;Initialize counter1 with 0100H CONTROL = Address
of control word register
OUT 41H,AL
MOV AL,01H MOV AL,74H 65H=101 dec
OUT 41H,AL OUT CONTROL,AL
74H=0111 0100 MOV AL,65H ;count of 101dec
MOV AL,1FFFH =>01 =counter1
OUT 42H,AL ;Initialize counter2 with 1FFFH OUT TIMER1,AL
=>11 = LSB followed
MOV AL,1FH by MSB MOV AL,0 TIMER1 = Address of
OUT 42H,AL =>010 = mode 2 OUT TIMER1,AL counter 1
=>0 = Binary

31 32