Faculty of Information and Communication Technology (FICT)

I/O

Special purpose I/O interfaces
UCCE2043 Basic Microprocessor  display
 parallel printer interface
Basic Input/Output  serial communication interface
 local area network interface

Not all microcomputer systems employ
H Y Lee
each of these types
[email protected]
Special purpose interfaces are
implemented as add-on cards on the PC
 Ex: PCI-USB Card, PCI-eSATA Card, etc…

1 2

Basic Input/Output Instruction E.g.

IN and OUT - instructions for the transfer of data from and to
an I/O device.

MOV DX,500H

IN and OUT transfer data between an I/O device and the
microprocessor’s accumulator ( only AL or AX ). IN AL,DX

The I/O address…
 Could be stored in register DX as a 16-bit I/O address (variable
--- address is stored in DX first
addressing). --- input data to AL from port address 500H
 Could immediately follows the opcode as an 8-bit I/O address
(can only access 00H to FFH, 256 I/O locations)
OUT 20H,AL

Only 16-bits (A0 to A15) are decoded.
E.g.
--- output AL to I/O port 0020H.
IN AL, 20H ; 8-bits are saved to AL from I/O port 20H.
IN AX, 30H ; A word is input from port 30H into AX
OUT DX, AL ; A byte is output from AL to the port
addressed by DX
OUT 21H, AX ;16-bits are written to I/O port 0021H.
3 4
 Isolated vs Memory-mapped I/O Isolated I/O

I/O locations are isolated from the memory system in a separate
I/O address space.

I/O devices are treated separately from memory

Separate control signals for the I/O space are developed using M/
IO’ and WR’ / RD’ to indicate an I/O read (IORC) or an I/O write
(IOWC) operation.

Advantage:
 No portion of memory is used for I/O.
 Specially tailored I/O instructions are used to maximize I/O
performance.

Disadvantage: All I/O operations take place between AL/AX
register and the I/O port.

Examples of Isolated I/O:
 Direct I/O:

IN AL, 70H

OUT 80H, AL
 Indirect I/O:

MOV DX, 1000H

IN AX, DX ; Input a word

OUT DX, AL ; Output a byte

From the book The Intel Microprocessor by Barry B 5 6

Brey pg. 389

Memory-mapped I/O

A memory-mapped I/O device is treated as a memory
location in the memory map.

No separate I/O interface, separate I/O instructions, separate

I/O control signals such as IORC and IOWC is required.
Advantage:
Personal computer
 Any memory transfer instruction can be used to access the
I/O device.
I/O Map

Disadvantage:
 A portion of the memory system is used as the I/O map.

 Memory mapped I/O operations execute slower than isolated

I/O operations.

Example data transfer using memory mapped I/O:
 MOV AX, A000H

MOV DS, AX ; Establish DS base address

MOV BX, 0000H ; Establish address of port 0
MOV [BX], AL ; output contents of AL to port 0
Or
MOV AL, [BX] ; input from port 0

7 8
 Input Output
Bus Bus
cycle Cycle
Of Of
8088 8088

9 10

Quiz Answer (a)-8088

1st bus cycle
 T1: Address 0338h is put on pins AD0-AD7, A8-15 and

Assume that AX = 1233h. Analyze the data latched when ALE is activated
transfer for a) 8088 b) 8086 when  T2: The low byte 33h is put on the data bus pins AD0-AD7
and IOWC’ is activated
MOV DX, 338h  T3: Setup time
OUT DX,AX  T4: Byte is written to the port assuming zero wait states

2nd Bus Cycle (Similar to 1st Bus Cycle)
 T1: Address 0339h is put on pins AD0-AD7, A8-15 and
latched when ALE is activated
 T2: The high byte 12h is put on the data bus pins and
IOWC’ is activated
 T3: Setup time
 T4: Byte is written to the port assuming zero wait states

11 12
 Answer (b)-8086 Answer (b)-8086

T1: Address 0338h is put on pins AD0-AD15 plus
BHE=low is latched by the 74LS373 when ALE is
activated

T2: 1233h, the contents of AX, is put on AD0-AD15
(33h on AD0-AD7, 12h on AD8-AD15) and IOWC’ is
activated

T3: Setup time
 During this interval, with the help of the signals A0=0 and
BHE=0, the low and high bytes are written to the appropriate
ports.
 It must be noted that since the operand is a 16 bit word and the
port address is an even address, the 8086 CPU does not
generate address 0339h
 Port address 338h is connected to the D0-D7 data bus and port
address 339h is connected to the D8- D15 data bus.

T4: Byte is written to the port assuming zero wait states
13 14

I/O address decoding I/O Design

The 8086, I/O system contains two 8-bit banks, just as
memory does.

Any 8-bit I/O write requires a separate write strobe to function
When data is sent out by the CPU, the data on the
correctly. data bus must be latched by the receiving device

I/O reads do not require separate I/O read strobes as the
While memories have an internal latch to grab the
microprocessor reads only the byte it expects and ignores the data on the data bus, a latching system must be
other byte. designed for ports

The data provided by the CPU to the port is on the
system data bus for a limited amount of time (50 -
1000ns) it must be latched before it is lost

Likewise, when data is coming in by way of a data
bus (either from port or memory) it must come in
through a three-state buffer

From the book The Intel Microprocessor by Barry B 15 16

Brey pg. 399
 I/O interfaces – 3 State Buffer I/O interfaces – 3 State Buffer (Refresh)

To prevent any unwanted data to come into
the system data bus, all input devices must
be isolated through the tri-state buffer.

74LS244 not only plays this role but also
provides the incoming signals sufficient
strength (driving capability) to travel all the
way to the CPU

Every device (memory, peripheral) connected
to the global data bus must have a latch or a
Design for IN AL,9CH tri-state buffer.
17 18

I/O E.g.
interfaces
– Latch

SEL

MOV DX, 8000h ;initialize address of port 0

MOV AL, 00h ; load data with bit 7 as logic 0
ON_OFF: OUT DX,AL ; turned on
MOV CX,0FFFFh ; load delay count of FFFFh
HERE: LOOP HERE ; Aprox. 17 T states
Design for OUT 9CH,AL XOR AL,80h
JMP ON_OFF
; complement bit 7

19 From the book The 8088 and 8086 Microprocessor 20

by Walter A. Triebel Avtar Singh pg. 470
 Handshaking / Polling Interface Circuitry

In practical applications, it is sometimes necessary within an I/O service
routine to repeatedly read the value at an input line and test this value for
Characteristics of the processor must be
a specific logic level.
 Many I/O devices are much slower than the microprocessor (Parallel
matched to those of the I/O devices.
printer, etc…)
 Microprocessor needs to synchronize by continuously testing on certain

Input Devices:
status signal line (BUSY, etc…)  They are either:
+5V
TTL (0.0V-0.8V low and 2.0-5.0V high) or compatible.
I0
Switch-based; usually either open or connected.
MOV DX,8000h  These must be conditioned before they can be used
. properly.
74245 . POLL: IN AL,DX
.  For example, to make a simple toggle switch TTL
SHR AL,1
compatible: +5V
I7 JC POLL TTL
output

21 From the book The Intel Microprocessor by Barry B 22

Brey pg. 383-386

Input devices Input devices 2

When a mechanical push button key is pressed or
released the metal contacts of the key momentarily
bounce before giving a steady-state reading.
S/w solution----delay

The bouncing of the key not be read as an input.
H/w solution

Can be eliminated using either software or hardware.

5 to
20ms

23 24
 DC Characteristics of 8088 Output devices

Interfacing an output device requires matching the voltage and
current relationships of the devices and processor.

From the datasheet, output levels of TTL compatible devices
are 0.0 to 0.4V for logic 0 and 2.4V to 5.0V for logic 1.

The current levels are 0.0 to 2.0mA (logic 0) and 0.0 to -400uA
(logic 1).

From the datasheet 8088 8-BIT HMOS 25 26

MICROPROCESSOR 8088/8088-2 page 16

8255 Programmable Peripheral Interface PPI (8255A)

Intel has developed several peripheral controller chips
designed to support the 80x86 processor family. The intent is
40-pin IC
to provide a complete I/O interface in one chip.

It is used to interface to the keyboard and a parallel printer port
3 ports (A, B, C; all are 8 bits)
in PCs (usually as part of an integrated chipset).

Requires insertion of wait states if used with a microprocessor
Data bus (D0-D7)
using higher that an 8 MHz clock.

PPI has 24 pins for I/O that are programmable in groups of 12
A0, A1 – port select input
pins and has three distinct modes of operation.

8255 PPI provides three 8 bit input ports in one 40 pin package

CS – chip select (active low)

The chip interfaces directly to the data bus of the processor,
RD / WR – read input / write
allowing its functions to be programmed; that is in one
application a port may appears as an output, but in another, as
input (active low)
an input (by reprogramming).
 This is in contrast with the 74LS373 and 74LS244 which are
RESET – reset input
hardwired and fixed

In the PC, an 82C55 or its equivalent is decoded at I/O ports

Vcc and GND
60H-63H.

27 28
 PPI (8255A) PPI (8255A)

PA0 - PA7: input or output

PB0 - PB7: input or output

PC0 - PC7: This 8 bit port can be all input or output.
It can also be split into two parts,CU (PC4 - PC7)
and CL (PC0 - PC3). 8
Data
Port A
8

Each can be used for input and output.

RD’ or WR’ RD
Port B
8

IOR and IOW of the system are connected WR

4

RESET RESET
CH

A0, A1, and CS {
Port C
4

CS’ selects the entire chip whereas A0 and A1 select the CS CL

specific port (A, B, or C) A1

A0
IN or OUT 8 bits at a time
IN or OUT 8 bits at a time
IN or OUT 8 bits at a time or 4 with 4 combination
Write only! OUT 8 bits at a time

29 30

Group A and Group B Addressing the 8255

Group A
 consists of port A and the upper part of port C. IO/M
 can be programmed as either input or output pins.
 can operate in modes 0, 1 and 2. 8-bit data bus 8

Mode 0: Basic I/O mode. Data transferred thru PA7-PA0 and PC7- Data Port A
PC4

Mode 1: Data transferred thru PA7-PA0, Handshaking signals 20-bit address bus RD 8
provided by Port C (PC7-PC4)

Mode 2: Bi-directional mode
Port B

Group B
WR
 consists of port B and the lower part of port C. RESET 4
can be programmed as either input or output pins. A15 CH
{

 can operate in modes 0 and 1. Logic Port
-A2 CS 4

Mode 0: Basic I/O mode. Data transferred thru PB7-PB0 and PC3- Circuit C
PC0 CL

Mode 1: Data transferred thru PB7-PB0, Handshaking signals
A1
provided by Port C (PC3-PC0) A1 A0
A0

31 32
 Mode 0 (Basic Input and output) Interfacing 8255 with LEDs

No handshaking is required; data are simply

written onto or read from a specified port.

There are two-8 bit ports and two 4-bit ports.
 Group A: PA7-PA0 and PC7-PC4
 Group B: PB7-PB0 and PC3-PC0

Any port can be input or output

Output are latched

Inputs are not latched

33 34

Running CODE SEGMENT

Software – How to Program 8255? light

ASSUME CS:CODE

MOV DX,0FF13H
MOV AL,89H

Some programming hints for PPI connection program OUT DX,AL

MOV DX,0FF10H
 (Step 1) Initialize 8255A: BEGIN:
MOV_L:
MOV
OUT
AL,01H
DX,AL
 Command word needs to be written to command register CALL
ROL
DELAY
AL,1
 MOV AL, ????? (which command word is to be written) TEST
JZ
AL,80H
MOV_L
 OUT ?????, AL (which port should we output)
MOV AL,80H
MOV_R: OUT DX,AL
 (Step 2) Initialize the output: CALL DELAY
ROR AL,1
 All data in the output need to be cleared (start counting TEST AL,01H
JZ MOV_R
from 0) JMP BEGIN
 Try to modified the above instructions DELAY PROC NEAR
MOV CX,4FFFH
LOOP $
RET
DELAY ENDP

CODE ENDS
END

35 36
 8-7segment display through 8255 Common anode
a-1 b-10 c-8 d-6 e-5 f-2 g-9
0 0 0 0 0 0 0 1 40
74LS244? 1 1 0 0 1 1 1 1 79
2 0 0 1 0 0 1 0 24
3 0 0 0 0 1 1 0 30
4 1 0 0 1 1 0 0 19
5 0 1 0 0 1 0 0 12
6 0 1 0 0 0 0 0 02
7 0 0 0 1 1 1 1 78

8 0 0 0 0 0 0 0 00

9 0 0 0 1 1 0 0
A 0 0 0 1 0 0 0
b 1 1 0 0 0 0 0
C 0 1 1 0 0 0 1
d 1 0 0 0 0 1 0
WHY 37ohm, 2.2kohm, 1Kohm?
E 0 1 1 0 0 0 0
F 0 1 1 1 0 0 0

From the book The Intel Microprocessor by Barry B 37 38

Brey pg. 399-401

Program to display 1-8 to 7-segment

Using 4511 with 7-Segment Display
mem db 79H,24H,30H,19H,12H,02H,78H,00H Common
cathode!

Manufacture
recommendation-
the LED display
flash between
100 HZ and
4511 –BCD to 7-segment latch/decoder/driver
1500Hz, 1ms =
What is the cost?
125Hz

From the data sheet HEF4511B MSI BCD to 7-segment

From the book The Intel Microprocessor by Barry B 39 latch/decoder/driver page 4 40
Brey pg. 401
 4511 Function Table Program to run 0 to 9 continuously
CODE SEGMENT
ASSUME CS:CODE
MOV DX,0FF13H
MOV AL,89H
OUT DX,AL
MOV DX,0FF10H
MOV AL,00H
BEGIN: OUT DX,AL
MOV CX,0000H
LOOP $
INC AL
DAA
JMP BEGIN
CODE ENDS
END

From the data sheet HEF4511B MSI BCD to 7-segment

latch/decoder/driver page 4 41 42

Programming Command Byte B (Refer Slide 30)

BGC-8088 -
8088 and Clock
Program PC4 of the 8255 to Control Circuits
generate a pulse of 50ms Section
with 50% duty cycle.

MOV DX,83H
MOV AL,9H
OUT DX,AL
CALL DELAY
MOV AL,8H
OUT DX,AL
CALL DELAY

43 44
 BGC-8088 - Memory & I/O
Device Address Decoder

BGC-8088 -
8255 (PPI), 8259 (PIC) and
8254 (Timer) Sections

FF10-FF1F

45 46

BGC-8088 - The Speaker Driver

BGC-8088 –
Programmable
Keyboard/Display Interface

47 UPDATE 2009 48