Fabrication Processes

NMOS Process
 PolySi Gate process
Mask 1 : Device well ( or Thinox or diffusion )

SiO2 (Field oxide)

P Si

Poly Si
Thin oxide
(gate oxide)

P Si

thinox
poly
Mask 2 : Pattern the poly Si ( gate mask )

P Si

Phosphorous source
S G D

n n
P Si

Mask 3 : contacts
Deposited
SiO2

P Si
PolySi Gate process (contd.)
Mask 4 : Metal Patterning

W
S D
P Si

MOST = thinox “AND” Poly Si

Green “AND” Red

G

W
D
S

L
CHANNEL
 NMOS Process

Mask 1 : Device well or thinox

Sio2

P Si

Mask 2 : Ion implantation of depletion Tr

Ion Implant

P Si
NMOS Process (Contd)
Mask 3 : PolySi

P Si

Diffusion Step
Phosphorous n+ Diffusion

P Si
N+ diffusion
Enh. MOST Depletion MOST

n+ n+ n+
NMOS Process (Contd)
Mask 4 : Contacts

SiO2

P Si

Enh. MOST Depletion MOST

A A

Mask 5 : Metalization

SiO2

P Si
Input
GND

VDD

A A

Ouput
NMOS Process (Contd)

N MOS Enh . Tr = thinox “AND”

Poly Si “AND” NOT (Ion Implant)

N MOS Depl. Tr = thinox “AND”

Poly Si “AND” Ion Implant
 NMOS Process Design Rules

Widths and Spacings

3λ 2λ 2λ

2λ
3λ
3λ
2λ
2λ
3λ
Diffusion PolySilicon lines
Metal

2λ
PolySi line to Diffusion line λ
2λ

Transistors

Depletion Transistor
Transistor
2λ

2λ

2λ 2λ

2λ
2λ 2λ

Depletion transistor rules Extension rule

Contacts (Exact DRC)

λ λ λ λ λ λ
2λ 2λ 2λ

Metal Poly Diffusion

Contact Contact Contact

Metal, Poly or
Diffusion

2λ

2λ
Contact to Transistor Spacing
Contact to Contact Spacing