Dp83867ir Rgmii
Dp83867ir Rgmii
Dp83867ir Rgmii
DP83867IR
SNLS484B – FEBRUARY 2015 – REVISED AUGUST 2015
4 System Diagram
MII 10BASE-T
GMII 100BASE-TX
RGMII 1000BASE-T
DP83867
Ethernet MAC 10/100/1000 Mb/s Magnetics RJ-45
Ethernet Physical Layer
25 MHz Status
Crystal or Oscillator LEDs
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DP83867IR
SNLS484B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Detailed Description ............................................ 20
2 Applications ........................................................... 1 8.1 Overview ................................................................. 20
3 Description ............................................................. 1 8.2 Functional Block Diagram ....................................... 21
4 System Diagram..................................................... 1 8.3 Feature Description................................................. 22
8.4 Device Functional Modes........................................ 24
5 Revision History..................................................... 2
8.5 Programming .......................................................... 38
6 Pin Configuration and Functions ......................... 4
8.6 Register Maps ......................................................... 45
7 Specifications......................................................... 9
9 Application and Implementation ........................ 97
7.1 Absolute Maximum Ratings ...................................... 9
9.1 Application Information............................................ 97
7.2 ESD Ratings.............................................................. 9
9.2 Typical Application ................................................. 97
7.3 Recommended Operating Conditions....................... 9
7.4 Thermal Information .................................................. 9 10 Power Supply Recommendations ................... 101
7.5 Electrical Characteristics......................................... 10 11 Layout................................................................. 103
7.6 Powerup Timing ..................................................... 11 11.1 General Layout Guidelines ................................. 103
7.7 Reset Timing ........................................................... 12 11.2 PCB Layer Stacking............................................ 104
7.8 MII Serial Management Timing ............................... 13 11.3 Layout Example .................................................. 105
7.9 RGMII Timing .......................................................... 14 12 Device and Documentation Support ............... 106
7.10 GMII Transmit Timing ........................................... 15 12.1 Documentation Support ..................................... 106
7.11 GMII Receive Timing ............................................ 16 12.2 Community Resources........................................ 106
7.12 100Mb/s MII Transmit Timing ............................... 17 12.3 Trademarks ......................................................... 106
7.13 100Mb/s MII Receive Timing ................................ 17 12.4 Electrostatic Discharge Caution .......................... 106
7.14 10Mb/s MII Transmit Timing ................................. 18 12.5 Glossary .............................................................. 106
7.15 10Mb/s MII Receive Timing .................................. 18 13 Mechanical, Packaging, and Orderable
7.16 Typical Characteristics .......................................... 19 Information ......................................................... 106
5 Revision History
Changes from Revision A (June 2015) to Revision B Page
• Added "Power consumption as low as 490 mW" to the Features list .................................................................................... 1
• Changed Description text From: "The DP83867 consumes only 565 mW" To: "The DP83867 consumes only 490 mW" ... 1
• Changed Pin RBIAS Description From: "A 10 kΩ +/-1% resistor" To: "A 11 kΩ ±1% resistor". ............................................ 8
• Changed Power consumption, 2 supplies TYP value From 565 mW To 530 mW in the Electrical Characteristics ............ 10
• Changed Power consumption, optional 3rd supply TYP value From 545 mW To 490 mW in the Electrical
Characteristics ...................................................................................................................................................................... 10
• Changed Register address: From: "BICSR1 register (0x0039)" To: "BICSR2 register (0x0072)", and changed From:
"read from the BISCR register (0x0016h)" To: "read from the STS2 register (0x0017h)" in the BIST Configuration .......... 34
• Changed section BIST Control and Status Register 1 (BICSR1) and Table 40 From: Address 0x0039 To: Address
0x0071 .................................................................................................................................................................................. 80
• Changed section BIST Control and Status Register 2 (BICSR2) and Table 41 From: Address 0x003A To: Address
0x0072 .................................................................................................................................................................................. 80
• Changed the document title From: "Robust, Low Power" To: "Robust, High Immunity" ....................................................... 1
• Changed the Features listed under "Highlights" .................................................................................................................... 1
• Changed the Applications list ................................................................................................................................................ 1
• Changed the Description text and layout .............................................................................................................................. 1
• Added descriptions for LED INTERFACE pins in the Pin Function table .............................................................................. 7
• Added TF fall time = 0.75 ns (Max) in RGMII Timing (4) ........................................................................................................ 14
• Added T4, MDI to GMII Latency = 264 ns (NOM) to GMII Receive Timing (6). .................................................................... 16
• Changed the title of Figure 21 From: Typical MDC/MDIO Read Operation To: Fast Link Drop Mechanism....................... 35
• Moved text From the end of Table 5 To PHY Identifier Register #1 (PHYIDR1) ................................................................ 49
• Changed format of loopback control bits in Table 25 "BIST Control Register (BISCR)" .................................................... 67
• Changed BIT NAME (11:8) From: "LED_ACT_SEL To: LED_2_SEL in Table 27 .............................................................. 70
• Changed BIT NAME (7:4) From: "LED_SPD_SEL To: LED_1_SEL in Table 27 ............................................................... 71
• Changed BIT NAME (3:0 From: "LED_LNK_SEL To: LED_0_SEL in Table 27 ................................................................. 71
• Changed the title of Table 39 From: Address 0x006FE To: Address 0x006F .................................................................... 79
• Deleted text "of the 64-QFP package" from the second paragraph in section Cable Line Driver........................................ 98
• Deleted text "for MII Mode" from the second paragraph in section Clock In (X_I) Recommendation ................................. 99
64-Pin QFP
Package PAP
Top View
RX_DV/RX_CTRL
TX_EN/TX_CTRL
RX_ER/GPIO
RXD_7/GPIO
RX_D6/GPIO
RX_D5/GPIO
INT/PWDN
COL/GPIO
RESET_N
VDDA1P8
CS/GPIO
VDD1P1
VDDIO
LED_0
LED_1
LED_2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RESERVED 1 48 RX_D4/GPIO
TD_P_A 2 47 RX_D3
TD_M_A 3 46 RX_D2
VDDA2P5 4 45 RX_D1
TD_P_B 5 44 RX_D0
TD_M_B 6 43 RX_CLK
RESERVED 7 42 VDD1P1
VDD1P1 8 41 VDDIO
RESERVED 9 DP83867 40 GTX_CLK
TD_P_C 10 39 TX_ER
TD_M_C 11 38 TX_D0
VDDA2P5 12 37 TX_D1
TD_P_D 13 36 TX_D2
TD_M_D 14 35 TX_D3
RBIAS 15 34 TX_D4
RESERVED 16 33 TX_D5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDDA1P8
X_O
X_I
MDC
MDIO
CLK_OUT
VDDIO
JTAG_TRSTN
JTAG_CLK
JTAG_TDO
JTAG_TMS
JTAG_TDI
VDD1P1
TX_CLK
TX_D7
TX_D6
Pin Functions
PIN
NUMBER TYPE (1) DESCRIPTION
NAME
PAP
MAC INTERFACES (RGMII, GMII, MII)
MII TRANSMIT CLOCK: TX_CLK is a continuous clock signal driven by the
PHY during 10 Mbps or 100 Mbps MII mode. TX_CLK clocks the data or error
TX_CLK 30 O out of the MAC layer and into the PHY.
The TX_CLK clock frequency is 2.5 MHz in 10BASE-Te and 25 MHz in
100BASE-TX mode.
GMII TRANSMIT DATA Bit 7: This signal carries data from the MAC to the PHY
TX_D7 31 I, PD
in GMII mode. It is synchronous to the transmit clock GTX_CLK.
GMII TRANSMIT DATA Bit 6: This signal carries data from the MAC to the PHY
TX_D6 32 I, PD
in GMII mode. It is synchronous to the transmit clock GTX_CLK.
GMII TRANSMIT DATA Bit 5: This signal carries data from the MAC to the PHY
TX_D5 33 I, PD
in GMII mode. It is synchronous to the transmit clock GTX_CLK.
GMII TRANSMIT DATA Bit 4: This signal carries data from the MAC to the PHY
TX_D4 34 I, PD
in GMII mode. It is synchronous to the transmit clock GTX_CLK.
TRANSMIT DATA Bit 3: This signal carries data from the MAC to the PHY in
GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to
TX_D3 35 I, PD
the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit
clock TX_CLK.
TRANSMIT DATA Bit 2: This signal carries data from the MAC to the PHY in
GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to
TX_D2 36 I, PD
the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit
clock TX_CLK.
TRANSMIT DATA Bit 1: This signal carries data from the MAC to the PHY in
GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to
TX_D1 37 I, PD
the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit
clock TX_CLK.
TRANSMIT DATA Bit 0: This signal carries data from the MAC to the PHY in
GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to
TX_D0 38 I, PD
the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit
clock TX_CLK.
GMII TRANSMIT ERROR: This signal is used in GMII mode to force the PHY
to transmit invalid symbols. The TX_ER signal is synchronous to the GMII
transmit clock GTX_CLK.
In MII 4B nibble mode, assertion of Transmit Error by the controller causes the
TX_ER 39 I, PD
PHY to issue invalid symbols followed by Halt (H) symbols until deassertion
occurs.
In GMII mode, assertion causes the PHY to emit one or more code-groups that
are invalid data or delimiter in the transmitted frame.
GMII and RGMII TRANSMIT CLOCK: This continuous clock signal is sourced
GTX_CLK 40 I, PD
from the MAC layer to the PHY. Nominal frequency is 125 MHz.
RECEIVE CLOCK: Provides the recovered receive clocks for different modes of
operation:
RX_CLK 43 O 2.5 MHz in 10 Mbps mode.
25 MHz in 100 Mbps mode.
125 MHz in 1000 Mps GMII and RGMII mode.
RECIEVE DATA Bit 0: This signal carries data from the PHY to the MAC in
RX_D0 44 S, O, PD
GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
RECIEVE DATA Bit 1: This signal carries data from the PHY to the MAC in
RX_D1 45 O, PD
GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
7 Specifications
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply Voltage (VDDA2P5) -0.3 3.0 V
Supply Voltage (VDDA1P8) -0.3 2.1 V
Supply Voltage (VDD1P1) -0.3 1.3 V
3.3 V Option -0.3 3.8 V
Supply Voltage (VDDIO) 2.5 V Option -0.3 3.0 V
1.8 V Option -0.3 2.1 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±8 V and/or ± 2 V may actually have higher
performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(1)
7.6 Powerup Timing
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
T1 Post Power Up Stabilization time
MDIO is pulled high for 32-bit
prior to MDC preamble for 200 ms
serial management initialization.
register accesses
T2 Hardware Configuration Latch-in Hardware Configuration Pins are
200 ms
Time from power up described in Strap Configuration.
T3 Hardware Configuration pins
64 ns
transition to output drivers
VDD
X1 clock
T1
Hardware
RESET_N
32 CLOCKS
MDC
T2
Latch-In of Hardware
Configuration Pins
T3
VDD
X1 clock
T1
T4
Hardware
RESET _N
32 CLOCKS
MDC
T2
Latch-In of Hardware
Configuration Pins
T3
MDC
T4 T1
MDIO (output )
MDC
T2 T3
TXC
(at Transmitter)
TskewT
TskewR
TXC
(at Receiver)
TsetupT
TholdT
RXC
TholdR
(at Receiver)
TsetupR
tT5t tT1t
GTX_CLK
T2 T4 T2
TXD [7:0]
TX_EN
TX_ER
T3
tT6t
tT2t T3 T3
RX_CLK
tT1t
RXD [7:0]
RX_DV Valid Data
RX_ER
tT4t
T1 T1
TX_CLK
T2 T3
TXD[3:0]
Valid Data
TX_EN
T1 T1
RX_CLK
T2
RXD[3: 0]
RX_DV Valid Data
RX_ER
T1 T1
TX_CLK
T2
T3
TXD[3:0]
Valid Data
TX_EN
T1 T1
RX_CLK
T2 T3
RXD[3:0]
Valid Data
RX_DV
(500 mV/DIV)
C1
C1
Time (4 ns/DIV) Time (32 ns/DIV)
8 Detailed Description
8.1 Overview
The DP83867 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-
Te, 100BASE-TX and 1000BASE-T Ethernet protocols.
The DP83867 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. It interfaces directly to
twisted pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE
802.3u Standard Media Independent Interface (MII), the IEEE 802.3z Gigabit Media Independent Interface
(GMII), or Reduced GMII (RGMII).
The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. It has
deterministic, low latency and provides IEEE 1588 Start of Frame Detection.
The DP83867 offers innovative diagnostic features including dynamic link quality monitoring for fault prediction
during normal operation.
GTX_CLK
RXD[7:0]
TXD[7:0]
RX_CLK
TX_CLK
Interrupt
RX_ER
RX_DV
TX_ER
TX_EN
MDIO
MDC
CRS
COL
MGNT
MUX / DMUX
& PHY CNTRL
MII GMII
MII MII
GMII
Auto-
Negotiation
Manchester
100BASE-TX 10 Mb/s PAM-5
PMD 17 Level PR Shaped
125 Msymbols/s
MLT-3
100 Mb/s
DAC / ADC
SUBSYSTEM
TIMING
DRIVERS /
RECEIVERS
DAC / ADC
TIMING BLOCK
MAGNETICS
DEST (6 bytes)
SRC (6 bytes)
))«))(6 bytes)
MAGIC pattern
DEST * 16
CRC (4 bytes)
The SFD pulse output can be configured using the GPIO Mux Control registers, GPIO_MUX_CTRL1 (register
address 0x0171) and GPIO_MUX_CTRL2 (register address 0x0172).
The initial strap value for the RGMII disable is also available in the Strap Configuration Status Register 1
(STRAP_STS1).
The timing paths can either be configured for Aligned mode or Shift mode. In Aligned mode, no clock skew is
introduced. In Shift mode, the clock skew can be introduced in 0.25 ns increments (via register configuration).
Configuration of the Aligned mode or Shift mode is accomplished via the RGMII Control Register (RGMIICTL),
address 0x0032. In Shift mode, the clock skew can be adjusted using the RGMII Delay Control Register
(RGMIIDCTL), address 0x0086.
The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched
on the rising edge of the MDC clock. The MDIO pin requires a pull-up resistor (2.2 kΩ) which, during IDLE and
turnaround, pulls MDIO high.
Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, a 5-bit address is used. During
power-up reset, the DP83867 latches the PHY_ADD configuration pins to determine its address.
The management entity must not start an SMI transaction in the first cycle after power-up reset. To maintain valid
operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is deasserted. In normal
MDIO transactions, the register address is taken directly from the management-frame reg_addr field, thus
allowing direct access to 32 16-bit registers (including those defined in IEEE 802.3 and vendor specific). The
data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern makes
sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time
inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no
device may actively drive the MDIO signal during the first bit of Turnaround. The addressed DP83867 drives the
MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 19 shows the
timing relationship between MDC and the MDIO as driven/received by the Station (STA) and the DP83867 (PHY)
for a typical register read access.
For write transactions, the station-management entity writes data to the addressed DP83867, thus eliminating the
requirement for MDIO Turnaround. The Turnaround time is filled by the management entity by inserting <10>.
Figure 19 shows the timing relationship for a typical MII register write access. The frame structure and general
read/write transactions are shown in Table 1, Figure 19, and Figure 20.
8.4.3 Auto-Negotiation
All 1000BASE-T PHYs are required to support Auto-Negotiation. The Auto-Negotiation function in 1000BASE-T
has three primary purposes:
• Auto-Negotiation of Speed & Duplex Selection
• Auto-Negotiation of Master/Slave Resolution
• Auto-Negotiation of Pause/Asymetrical Pause Resolution
8.4.6.1 TDR
The DP83867 uses Time Domain Reflectometry (TDR) to determine the quality of the cables, connectors, and
terminations in addition to estimating the cable length. Some of the possible problems that can be diagnosed
include opens, shorts, cable impedance mismatch, bad connectors, termination mismatches, cross faults, cross
shorts and any other discontinuities along the cable.
The DP83867 transmits a test pulse of known amplitude (1 V or 2.5 V) down each of the two pairs of an attached
cable. The transmitted signal continues down the cable and reflects from each cable imperfection, fault, bad
connector, and from the end of the cable itself. After the pulse transmission, the DP83867 measures the return
time and amplitude of all these reflected pulses. This technique enables measuring the distance and magnitude
(impedance) of non-terminated cables (open or short), discontinuities (bad connectors), and improperly-
terminated cables with ±1m accuracy.
The DP83867 also uses data averaging to reduce noise and improve accuracy. The DP83867 can record up to
five reflections within the tested pair. If more than 5 reflections are recorded, the DP83867 saves the first 5 of
them. If a cross fault is detected, the TDR saves the first location of the cross fault and up to 4 reflections in the
tested channel. The DP83867 TDR can measure cables beyond 100m in length.
For all TDR measurements, the transformation between time of arrival and physical distance is done by the
external host using minor computations (such as multiplication, addition and lookup tables). The host must know
the expected propagation delay of the cable, which depends, among other things, on the cable category (for
example, CAT5, CAT5e, or CAT6).
8.4.6.2 ALCD
The DP83867 also supports Active Link Cable Diagnostic (ALCD). The ALCD offers a passive method to
estimate the cable length during active link. The ALCD uses passive digital signal processing based on adapted
data, thus enabling measurement of cable length with an active link partner. The ALCD Cable length
measurement accuracy is ±5m for the pair used in the Rx path (due to the passive nature of the test, only the
receive path is measured).
Signal
Link Drop
T1
Link Loss
Indication
(Link LED)
As described in Figure 21, the link loss mechanism is based on a time window search period, in which the signal
behavior is monitored. The T1 window is set by default to reduce typical link-drops to less than 1ms.
The DP83867 supports enhanced modes that shorten the window called Fast Link Down mode. In this mode,
which can be configured using the FLD_CFG register (address 0x002C) and the FLD_THR_CFG register
(address 0x002D), the T1 window is shortened significantly, in most cases less than 10 μs. In this period of time
there are several criteria allowed to generate link loss event and drop the link:
1. Loss of descrambler sync
2. Receive errors
3. MLT3 errors
4. Mean Squared Error (MSE)
5. Energy loss
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Links: DP83867IR
DP83867IR
SNLS484B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com
The Fast Link Down functionality allows the use of each of these options separately or in any combination. Note
that since this mode enables extremely quick reaction time, it is more exposed to temporary bad link quality
scenarios.
100M Fast Link Down based on loss of energy can be configured by strap. Other modes require register
configuration.
For Fast Link Down operation in Gigabit operation, the recommended configuration is:
1. Set FLD_1G (bit 14) in FLD_CFG.
2. Select ENERGY_LOST (bit 0) in FLD_CFG.
3. Set the ENERGY_LOST_FLD_THR (bits 2:0) in FLD_THR_CFG to 0x1.
Mirror mode can be enabled via strap or via register configuration using the Port Mirror Enable bit in the CFG4
register (address 0x0031).
8.4.6.8 Interrupt
The DP83867 can be configured to generate an interrupt when changes of internal status occur. The interrupt
allows a MAC to act upon the status in the PHY without polling the PHY registers. The interrupt source can be
selected through the interrrupt registers, MICR (register address 0x0012) and ISR (register address 0x0013).
8.5 Programming
8.5.1 Strap Configuration
The DP83867 uses many of the functional pins as strap options to place the device into specific modes of
operation. The values of these pins are sampled at power up or hard reset. During software resets, the strap
options are internally reloaded from the values sampled at power up or hard reset. The strap option pin
assignments are defined below. The functional pin name is indicated in parentheses.
The strap pins supported are 4-level straps, which are described in greater detail below.
NOTE
Since strap pins may have alternate functions after reset is deasserted, they should not be
connected directly to VDD or GND.
Configuration of the device may be done via the 4-level strap pins or via the management register interface. A
pullup resistor and a pulldown resistor of suggested values may be used to set the voltage ratio of the 4-level
strap pin input and the supply to select one of the possible selected modes.
The MAC interface pins must support I/O voltages of 3.3 V, 2.5 V, and 1.8 V. As the strap inputs will be
implemented on these pins, the straps must also support operation at 3.3-V, 2.5-V, and 1.8-V supplies.
The device should feature 4-level strap pins, each supporting at least 4 selectable options.
VDDIO
Rhi
V STRAP
Rlo
NOTE
Note: Strap modes 1 and 2 are not applicable for RX_DV/RX_CTRL. The
RX_DV/RX_CTRL strap must be configured for strap mode 3 or strap mode 4.
NOTE
Note: Strap modes 3 and 4 are not applicable for CRS. The CRS strap must be configured
for strap mode 1 or strap mode 2.
NOTE
Note: Strap modes 2 and 4 are not applicable for LED_0. The LED_0 strap must be
configured for strap mode 1 or strap mode 3.
Refer to Figure 23 for an example of strap connections to external components. In this example, the strapping
results in Mode 1 for LED_0 and Mode 4 for LED_1.
The adaptive nature of the LED outputs helps to simplify potential implementation issues of these dual purpose
pins.
LED_0
LED_1
Mode 1 Mode 4
2.49 lQ
470Q 470Q
VDD
GND
LED_2
2.5V or 3.3V
Mode 2
200 Q
1.8V
11 lQ
2.49 lQ
GND GND
11 N
RX_D0
6.04 N
RX_D2
2.49 N
RX_D4
2.49 N
Table 10. Auto-Negotiation Link Partner Ability Register (ANLPAR), Address 0x0005
BIT BIT NAME DEFAULT DESCRIPTION
15 NP 0, RO Next Page Indication:
0 = Link Partner does not desire Next Page Transfer.
1 = Link Partner desires Next Page Transfer.
14 ACK 0, RO Acknowledge:
1 = Link Partner acknowledges reception of the ability data word.
0 = Not acknowledged.
The Auto-Negotiation state machine will automatically control this bit
based on the incoming FLP bursts.
13 RF 0, RO Remote Fault:
1 = Remote Fault indicated by Link Partner.
0 = No Remote Fault indicated by Link Partner.
12 RESERVED 0, RO RESERVED for Future IEEE use: Write as 0, read as 0.
11 ASM_DIR 0, RO ASYMMETRIC PAUSE:
1 = Asymmetric pause is supported by the Link Partner.
0 = Asymmetric pause is not supported by the Link Partner.
10 PAUSE 0, RO PAUSE:
1 = Pause function is supported by the Link Partner.
0 = Pause function is not supported by the Link Partner.
9 T4 0, RO 100BASE-T4 Support:
1 = 100BASE-T4 is supported by the Link Partner.
0 = 100BASE-T4 not supported by the Link Partner.
8 TX_FD 0, RO 100BASE-TX Full Duplex Support:
1 = 100BASE-TX Full Duplex is supported by the Link Partner.
0 = 100BASE-TX Full Duplex not supported by the Link Partner.
7 TX 0, RO 100BASE-TX Support:
1 = 100BASE-TX is supported by the Link Partner.
0 = 100BASE-TX not supported by the Link Partner.
6 10_FD 0, RO 10BASE-T Full Duplex Support:
1 = 10BASE-T Full Duplex is supported by the Link Partner.
0 = 10BASE-T Full Duplex not supported by the Link Partner.
5 10 0, RO 10BASE-T Support:
1 = 10BASE-T is supported by the Link Partner.
0 = 10BASE-T not supported by the Link Partner.
4:0 SELECTOR 0 0000, RO Protocol Selection Bits:
Link Partner's binary encoded protocol selector.
Table 12. Auto-Negotiation Next Page Transmit Register (ANNPTR), Address 0x0007
BIT BIT NAME DEFAULT DESCRIPTION
15 NP 0, RW Next Page Indication:
0 = No other Next Page Transfer desired.
1 = Another Next Page desired.
14 ACK 0, RO Acknowledge:
1 = Acknowledge reception of link code word
0 = Do not acknowledge of link code word.
13 MP 1, RW Message Page:
1 = Current page is a Message Page.
0 = Current page is an Unformatted Page.
12 ACK2 0, RW Acknowledge2:
1 = Will comply with message.
0 = Cannot comply with message.
Acknowledge2 is used by the next page function to indicate that
Local Device has the ability to comply with the message received.
11 TOG_TX 0, RO Toggle:
1 = Value of toggle bit in previously transmitted Link Code Word
was 0.
0 = Value of toggle bit in previously transmitted Link Code Word
was 1.
Toggle is used by the Arbitration function within Auto-Negotiation to
ensure synchronization with the Link Partner during Next Page
exchange. This bit shall always take the opposite value of the
Toggle bit in the previously exchanged Link Code Word.
10:0 CODE 000 0000 0001, Code:
RW
This field represents the code field of the next page transmission. If
the MP bit is set (bit 13 of this register), then the code shall be
interpreted as a "Message Page”, as defined in Annex 28C of IEEE
802.3u. Otherwise, the code shall be interpreted as an "Unformatted
Page”, and the interpretation is application specific.
The default value of the CODE represents a Null Page as defined in
Annex 28C of IEEE 802.3u.
Table 13. Auto-Negotiation Next Page Transmit Register (ANNPTR), Address 0x0008
BIT BIT NAME DEFAULT DESCRIPTION
15 NP 0, RW Next Page Indication:
0 = No other Next Page Transfer desired by the link partner.
1 = Another Next Page desired by the link partner.
14 ACK 0, RO Acknowledge:
1 = Acknowledge reception of link code word by the link partner.
0 = Link partner does not acknowledge reception of link code word.
13 MP 1, RW Message Page:
1 = Received page is a Message Page.
0 = Received page is an Unformatted Page.
12 ACK2 0, RW Acknowledge2:
1 = Link partner sets the ACK2 bit.
0 = Link partner coes not set the ACK2 bit.
Acknowledge2 is used by the next page function to indicate that link
partner has the ability to comply with the message received.
11 TOG_TX 0, RO Toggle:
1 = Value of toggle bit in previously transmitted Link Code Word
was 0.
0 = Value of toggle bit in previously transmitted Link Code Word
was 1.
Toggle is used by the Arbitration function within Auto-Negotiation to
ensure synchronization with the Link Partner during Next Page
exchange. This bit shall always take the opposite value of the
Toggle bit in the previously exchanged Link Code Word.
10:0 CODE 000 0000 0001, Code:
RW
This field represents the code field of the next page transmission. If
the MP bit is set (bit 13 of this register), then the code shall be
interpreted as a "Message Page”, as defined in Annex 28C of IEEE
802.3u. Otherwise, the code shall be interpreted as an "Unformatted
Page”, and the interpretation is application specific.
The default value of the CODE represents a Null Page as defined in
Annex 28C of IEEE 802.3u.
Table 21. MII Interrupt Control Register (MICR), Address 0x0012 (continued)
BIT BIT NAME DEFAULT DESCRIPTION
2 XGMII_ERR_INT_EN 0, RW Enable xGMII Error Interrupt:
1 = Enable xGMII Error Interrupt.
0 = Disable xGMII Error Interrupt.
1 POLARITY_CHNG_INT_EN 0, RW Enable Polarity Change Interrupt:
1 = Enable Polarity Change interrupt.
0 = Disable Polarity Change interrupt.
0 JABBER_INT_EN 0, RW Enable Jabber Interrupt:
1 = Enable Jabber interrupt.
0 = Disable Jabber interrupt.
Table 32. Fast Link Drop Configuration Register (FLD_CFG), Address 0x002C
BIT BIT NAME DEFAULT DESCRIPTION
15 FLD_EN 0, RW Fast Link Drop Enable:
1 = Enable FLD.
0 = Normal operation.
14 FLD_1G 0, RW 1000BASE-T Fast Link Drop:
1 = Configure FLD for 1000BASE-T operation.
0 = Normal operation.
13 RESERVED 0, RO RESERVED
12:8 FLD_STS 0, RO, LH Fast Link Drop Status:
Status Registers that latch high each time a given Fast Link Down
mode is activated and causes a link drop (assuming this criterion
was enabled):
Bit 12: Descrambler Loss Sync
Bit 11: RX Errors
Bit 10: MLT3 Errors
Bit 9: SNR level
Bit 8: Signal/Energy Lost
7:5 RESERVED 0, RO RESERVED
4:0 FLD_SRC_CFG 0, RW Fast Link Drop Source Configuration:
The following FLD sources can be configured independently:
Bit 4: Descrambler Loss Sync
Bit 3: RX Errors
Bit 2: MLT3 Errors
Bit 1: SNR level
Bit 0: Signal/Energy Lost
Table 33. Fast Link Drop Threshold Configuration Register (FLD_THR_CFG), Address 0x002D
BIT BIT NAME DEFAULT DESCRIPTION
15:3 RESERVED 0 0000 0100 RESERVED
0100, RO
2:0 FLD_ENERGY_LOST_THR 010, RW Energy lost threshold for FLD energy lost mode
Energy_lost indication will be asserted if energy detector
accumulator falls below this threshold.
Table 40. BIST Control and Status Register 1 (BICSR1), Address 0x0071
BIT BIT NAME DEFAULT DESCRIPTION
15:0 PRBS_BYTE_CNT 0x0000, RO Holds the number of total bytes received by the PRBS checker.
Value in this register is locked when write is done to register
BICSR2 bit[0] or bit[1].
The count stops at 0xFFFF when PRBS_COUNT_MODE in BISCR
register (0x0016) is set to 0.
Table 41. BIST Control and Status Register 2 (BICSR2), Address 0x0072
BIT BIT NAME DEFAULT DESCRIPTION
15:11 Reserved 0x00, RO Ignored on Read
PRBS Checker Packet Count Overflow
10 PRBS_PKT_CNT_OVF 0, RO If set, PRBS Packet counter has reached overflow. Overflow is
cleared when PRBS counters are cleared by setting bit #1 of this
register.
PRBS Byte Count Overflow
9 PRBS_BYTE_CNT_OVF 0, RO If set, PRBS Byte counter has reached overflow. Overflow is cleared
when PRBS counters are cleared by setting bit #1 of this register.
8 Reserved 0,RO Ignore on Read
Holds number of error bytes that are received by PRBS checker.
Value in this register is locked when write is done to bit[0] or bit[1]
When PRBS Count Mode set to zero, count stops on 0xFF (see
7:0 PRBS_ERR_CNT 0x00, RO register 0x0016)
Notes: Writing bit 0 generates a lock signal for the PRBS counters.
Writing bit 1 generates a lock and clear signal for the PRBS
counters
Table 84. Receive Pattern Byte Mask Register 1 (RXFPBM1), Address 0x015C
BIT BIT NAME DEFAULT DESCRIPTION
15:0 PATTERN_BYTES_ 0, RW Masks for bytes 0 to 15 of the pattern. A '1' indicates a mask for the
MASK_0_15 associated byte.
Table 85. Receive Pattern Byte Mask Register 2 (RXFPBM2), Address 0x015D
BIT BIT NAME DEFAULT DESCRIPTION
15:0 PATTERN_BYTES_ 0, RW Masks for bytes 16 to 31 of the pattern. A '1' indicates a mask for
MASK_16_31 the associated byte.
Table 86. Receive Pattern Byte Mask Register 3 (RXFPBM3), Address 0x015E
BIT BIT NAME DEFAULT DESCRIPTION
15:0 PATTERN_BYTES_ 0, RW Masks for bytes 32 to 47 of the pattern. A '1' indicates a mask for
MASK_32_47 the associated byte.
Table 87. Receive Pattern Byte Mask Register 4 (RXFPBM4), Address 0x015F
BIT BIT NAME DEFAULT DESCRIPTION
15:0 PATTERN_BYTES_ 0, RW Masks for bytes 48 to 63 of the pattern. A '1' indicates a mask for
MASK_48_63 the associated byte.
Table 90. GPIO Mux Control Register 1 (GPIO_MUX_CTRL1), Address 0x0171 (continued)
BIT BIT NAME DEFAULT DESCRIPTION
3:0 RX_D4_GPIO_CTRL RW, 0000 RX_D4 GPIO Control:
1010 - 1111: RESERVED
1001: Constant '1'
1000: Constant '0'
0111: PRBS Errors / Loss of Sync
0110: LED 4
0101: RESERVED
0100: Energy Detect (1000Base-T and 100Base-TX only)
0011: WOL
0010: 1588 RX SFD
0001: 1588 TX SFD
0000: RX_D4
Table 93. Advanced Link Cable Diagnostics Control Register (ALCD_CTRL), Address 0x01A7
BIT BIT NAME DEFAULT DESCRIPTION
15:8 ALCD_SUM 0000 0000, RO ALCD result
7:6 RESERVED 0, RO RESERVED
5 ALCD_SUM_DONE 0, RO ALCD Complete:
1 = ALCD process has completed.
0 = ALCD process has not completed.
4 ALCD_CLEAR 0, RW, SC Clear ALCD:
1 = Reset the ALCD results.
3:0 RESERVED 0, RO RESERVED
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
DP83867
Ethernet MAC 10/100/1000 Mb/s Magnetics RJ-45
Ethernet Physical Layer
25 MHz Status
Crystal or Oscillator LEDs
TD_P_A
TD_M_A
TD_P_B
TD_M_B
TD_P_C
TD_M_C
TD_P_D
TD_M_D
X_I X_O
3.3V or 2.5V
Clock Source
CD1
CD2
X_I X_O
R1
CL1 CL2
As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, CL1 and
CL2 should be set at 27 pF, and R1 should be set at 0 Ω.
Specification for 25-MHz crystal are listed in Table 95.
VDDIO VDD1P1
VDDIO 1.1V
Supply 1 PF 1 PF Supply
VDDIO VDD1P1
10 PF 10 nF 1 PF 1 PF 10 nF 10 PF
VDDIO VDD1P1
1 PF 1 PF
VDD1P1
1 PF
VDDA2P5 VDDA1P8
2.5V
Supply 1 PF
VDDA2P5 VDDA1P8
10 PF 10 nF 1 PF
GND
(Die Attach Pad
For two supply configuration, both VDDA1P8 pins must be left unconnected.
Place 1µF decoupling capacitors as close as possible to component VDD pins.
VDDIO may be 3.3 V or 2.5 V or 1.8 V.
VDDIO VDD1P1
VDDIO 1.1V
Supply 1 PF 1 PF Supply
VDDIO VDD1P1
10 PF 10 nF 1 PF 1 PF 10 nF 10 PF
VDDIO VDD1P1
1 PF 1 PF
VDD1P1
1 PF
VDDA2P5 VDDA1P8
2.5V 1.8V
Supply 1 PF 1 PF Supply
VDDA2P5 VDDA1P8
10 PF 10 nF 1 PF 1 PF 10 nF 10 PF
GND
(Die Attach Pad
11 Layout
xxx
Legend
Ground
xxx
High-speed signal
VDD supply
xxx
xx xxxxx
4-Layer 6-Layer 8-Layer
Figure 34. Layout Example
Within a PCB, it may be desirable to run traces using different methods, microstrip vs. stripline, depending on the
location of the signal on the PCB. For example, it may be desirable to change layer stacking where an isolated
chassis ground plane is used. Figure 35 illustrates alternative PCB stacking options.
xxx
Legend
Chassis ground
xxxxxx
High-speed signal
VDD supply
Plane Coupling
Component
Transformer
(if not RJ45
PHY
Component Integrated in Connector
RJ45)
Plane Coupling
Note: Power/Ground Planes
Component
Voided under Transformer
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 17-Sep-2015
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
DP83867IRPAPR ACTIVE HTQFP PAP 64 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 DP83867IR
& no Sb/Br)
DP83867IRPAPT ACTIVE HTQFP PAP 64 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 DP83867IR
& no Sb/Br)
DP83867IRRGZR PREVIEW VQFN RGZ 48 2500 TBD Call TI Call TI -40 to 85 DP83867IR
DP83867IRRGZT PREVIEW VQFN RGZ 48 250 TBD Call TI Call TI -40 to 85 DP83867IR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 17-Sep-2015
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Aug-2015
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Aug-2015
Pack Materials-Page 2
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