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S6 Verilog LAB Project Report

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29 views4 pages

S6 Verilog LAB Project Report

Uploaded by

athithiyavs102
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Project Report

Title: Verilog HDL Design for Automatic Washing Machine Operations

Group Members:
 Aravind Krishnan - ECE21110
 Athithya V S - ECE21112
 Avanthika S - ECE21113

Abstract
This project presents the design and implementation of an automatic washing machine
control system using Verilog HDL. The controller operates in several states: rinse, soak,
wash, spin, and dry, with specific time durations allocated to each state. The system is
triggered by inserting a coin and completes the washing cycle by transitioning through all the
states. The design is implemented on an FPGA and verified using simulation. The results
show the correct operation of the FSM, timing logic, and output signals.

Methodology
Design Code

The washing machine controller is implemented using Verilog HDL. The FSM has states
corresponding to rinse, soak, wash, spin, and dry, with respective time durations. The
following is the Verilog code for the controller:

module washing_machine_controller (
input clk,
input rst,
input coin,
output reg on,
output reg completed,
output reg [6:0] remaining_time
);

// Define state encoding


parameter OFF = 3'b000, RINSE = 3'b001, SOAK = 3'b010, WASH = 3'b011,
SPIN = 3'b100, DRY = 3'b101;

reg [2:0] state, next_state;


reg [6:0] time_counter;

// Time durations for each state


parameter RINSE_TIME = 10, SOAK_TIME = 20, WASH_TIME = 30, SPIN_TIME =
20, DRY_TIME = 10;
// FSM state transitions and timer logic
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= OFF;
time_counter <= 0;
on <= 0;
completed <= 0;
remaining_time <= 0;
end else begin
state <= next_state;
if (on) begin
if (time_counter > 0) begin
time_counter <= time_counter - 1;
remaining_time <= time_counter;
end else begin
time_counter <= 0;
end
end
end
end

// FSM next state logic


always @(*) begin
next_state = state;
completed = 0;
case (state)
OFF: begin
on = 0;
remaining_time = 0;
if (coin) begin
next_state = RINSE;
on = 1;
time_counter = RINSE_TIME;
end
end
RINSE: begin
if (time_counter == 0) begin
next_state = SOAK;
time_counter = SOAK_TIME;
end
end
SOAK: begin
if (time_counter == 0) begin
next_state = WASH;
time_counter = WASH_TIME;
end
end
WASH: begin
if (time_counter == 0) begin
next_state = SPIN;
time_counter = SPIN_TIME;
end
end
SPIN: begin
if (time_counter == 0) begin
next_state = DRY;
time_counter = DRY_TIME;
end
end
DRY: begin
if (time_counter == 0) begin
next_state = OFF;
completed = 1;
end
end
default: begin
next_state = OFF;
end
endcase
end
endmodule

Testbench

The testbench simulates the behavior of the washing machine controller. It initializes the
inputs, applies a reset, inserts a coin to start the washing machine, and waits for the washing
cycle to complete.

verilog
Copy code
module tb_washing_machine_controller;

reg clk;
reg rst;
reg coin;
wire on;
wire completed;
wire [6:0] remaining_time;

// Instantiate the washing machine controller


washing_machine_controller uut (
.clk(clk),
.rst(rst),
.coin(coin),
.on(on),
.completed(completed),
.remaining_time(remaining_time)
);

// Clock generation
always #5 clk = ~clk; // 10ns period

initial begin
// Initialize signals
clk = 0;
rst = 0;
coin = 0;

// Apply reset
#10;
rst = 1;
#10;
rst = 0;

// Insert a coin to start the washing machine


#10;
coin = 1;
#10;
coin = 0;
// Wait for the washing cycle to complete
#5000; // Adjust based on the state durations

// Apply reset to stop the machine


#10;
rst = 1;
#10;
rst = 0;

// Finish simulation
#100;
$stop;
end

// Monitor the state and display signals


initial begin
$monitor("Time: %0t, State: %b, On: %b, Completed: %b, Remaining
Time: %0d",
$time, uut.state, on, completed, remaining_time);
end

endmodule

Results

The simulation results are shown in the waveform below:

The waveform indicates the correct operation of the washing machine controller. The FSM
transitions through the states of rinse, soak, wash, spin, and dry with the specified time
durations. The remaining_time output shows the countdown of time units for each state, and
the completed signal is asserted at the end of the cycle. The on signal correctly indicates the
on/off state of the washing machine.

ReferenceAn Implementation of Automatic Washing Machine Control System Using


Verilog HDL https://www.ijrti.org/papers/IJRTI1707011.pdf

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