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0-3 ExtendedVerilogReview

vcxvxcvxcvxcd

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0% found this document useful (0 votes)
11 views40 pages

0-3 ExtendedVerilogReview

vcxvxcvxcvxcd

Uploaded by

mhasan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 40

SUO

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Yuchen Huang

Content copied verbatim from ECE 571 material developed by Professor Mark G. Faust @ PSU ECE
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module FullAdder(S, CO, A, B, CI); module FullAdder(S, CO, A, B, CI);
input A, B, CI; input A,B,CI;
output S, CO; output reg
S, S,
CO;
CO;

assign S = A ^ B ^ CI; always @(A, B, CI) *%* + - +0# *+


begin
assign CO = A & B | A & CI | B & CI;
endmodule S = A ^ B ^ CI; 
CO = A & B | A & CI | B & CI;
end
endmodule

S
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module FullAdder(S, CO, A, B, CI);


input A,B,CI;
output S, CO;

wire W0, W1, W2, W3;

xor
xor1(W0, A, CI),
xor2(S, W0, B);

and
and1(W1, A, B),
and2(W2, A, CI),
and3(W3, B, CI);

or
or1(CO, W1, W2, W3);
endmodule

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input clock;
input j, k;
output q, qbar;

reg q; *%* + - +0# *++) )*-#,+ &%&')&,)#


assign qbar = ~q; #&" %= %+ **'&* + ->
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always @(posedge clock)
begin 
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q <= ~q;
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q <= 0;
else
q <= q;
end
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endmodule
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if (!Value) is NOT equal to if (~Value)

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O0F==7G5H8R4 of 1/2 is also an integer which is 0, so 9.0 **(1/2) = 9.0 ** (0) = 1.0, so result is 1.0 which is a floating
point since 9.0 is a floating point.

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13 % -4 = 1 because modular always takes the sign of the 1st number.

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module b;
 $9M/F:. reg signed [7:0] shorter;
reg [15:0] longer;
 $9GK/F:. reg signed [15:0] slonger;

RJAGFGF.
 initial
RGLA. begin
R. shorter = 8'b11110000;
longer = shorter;
slonger = shorter;

$display("longer = %b",longer);
A = 4'b1010 => A = 8'b00001010 $display("slonger = %b",slonger);
B = 16'hcAFE => A = 0xFE end
endmodule

RR
/')** &% +#%+&+*2
  
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&** %$%+4+ *#*& %#,*+#+:%* >6

reg [15:0] a, b, r;

r = (a + b) >> 1; // carry bit already lost
 = (a + b + 0) >> 1; // will move carry into r[15], 0 is an integer, which is 32 bit wide
r

module bitlength;
reg [3:0] a, b, c;
reg [4:0] d;

initial
begin
a = 9;
b = 8;
c = 1;
$display("answer = %b", c ? (a&b) : d);
end
endmodule
RS
/')** &% +#%+&+*2
&%* )+&##&. %&

 module arith;

 reg [7:0] a, b;
reg [7:0] dif;
reg [7:0] binv;
reg cd;

initial
begin

{cd, dif} = a + ~b + 1'b1;

binv = ~b;
{cd, dif} = a + binv + 1'b1;

end
endmodule

In a + ~b + 1'b1, -b has 1 sign bit and 8 bit value b, so a + ~b + 1'b1 is a 9 bit value

In a + binv + 1'b1, binv = -b which happens on 8 bit value

Therefore: RT
a + !b + 1'b1 is NOT equal to a + binv + 1'b1
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 *'#0,%+ &%*
module t;
reg a, b;

initial
begin
$monitor($time, "\tmonitor a = %0b, b = %0b",a,b);
a = 0;
#5;
a <= 1; &%:#&" %** %$%+/,+* %  ) &%
b = 1;
 "\tdisplay a = %0b, b = %0b",a,b);
$display($time,
$strobe($time, "\tstrobe a = %0b, b = %0b",a,b);
end
endmodule

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