0-3 ExtendedVerilogReview
0-3 ExtendedVerilogReview
Content copied verbatim from ECE 571 material developed by Professor Mark G. Faust @ PSU ECE
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module FullAdder(S, CO, A, B, CI); module FullAdder(S, CO, A, B, CI);
input A, B, CI; input A,B,CI;
output S, CO; output reg
S, S,
CO;
CO;
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xor
xor1(W0, A, CI),
xor2(S, W0, B);
and
and1(W1, A, B),
and2(W2, A, CI),
and3(W3, B, CI);
or
or1(CO, W1, W2, W3);
endmodule
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module b;
$9M/F:. reg signed [7:0] shorter;
reg [15:0] longer;
$9GK/F:. reg signed [15:0] slonger;
RJAGFGF.
initial
RGLA. begin
R. shorter = 8'b11110000;
longer = shorter;
slonger = shorter;
$display("longer = %b",longer);
A = 4'b1010 => A = 8'b00001010 $display("slonger = %b",slonger);
B = 16'hcAFE => A = 0xFE end
endmodule
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reg [15:0] a, b, r;
r = (a + b) >> 1; // carry bit already lost
= (a + b + 0) >> 1; // will move carry into r[15], 0 is an integer, which is 32 bit wide
r
module bitlength;
reg [3:0] a, b, c;
reg [4:0] d;
initial
begin
a = 9;
b = 8;
c = 1;
$display("answer = %b", c ? (a&b) : d);
end
endmodule
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module arith;
reg [7:0] a, b;
reg [7:0] dif;
reg [7:0] binv;
reg cd;
initial
begin
binv = ~b;
{cd, dif} = a + binv + 1'b1;
end
endmodule
In a + ~b + 1'b1, -b has 1 sign bit and 8 bit value b, so a + ~b + 1'b1 is a 9 bit value
Therefore: RT
a + !b + 1'b1 is NOT equal to a + binv + 1'b1
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module t;
reg a, b;
initial
begin
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b = 1;
"\tdisplay a = %0b, b = %0b",a,b);
$display($time,
$strobe($time, "\tstrobe a = %0b, b = %0b",a,b);
end
endmodule
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