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RTL Training Course

Vlsi related note.

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Loknath karmakar
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55 views4 pages

RTL Training Course

Vlsi related note.

Uploaded by

Loknath karmakar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Title: Mastering VLSI Design with Verilog: A Comprehensive RTL Training Course

Course Description:

This course provides a comprehensive understanding of Verilog, a hardware description language used
in digital circuit design and simulation. Starting from the basics, participants will delve into the evolution
of Verilog, its constructs, data types, modeling styles, and advanced topics such as timing control,
procedural blocks, and race conditions. Through hands-on exercises with multiple project and examples,
participants will gain practical skills in Verilog programming, enabling them to design and simulate
complex digital systems efficiently.

Course Outline:

1) INTRODUCTION TO VLSI DESIGN

✓ INTRODUCTION
✓ CONVENTIONAL APPROACH TO DIGITAL DESIGN
✓ VLSI DESIGN
✓ ASIC DESIGN FLOW

2) Verilog Constructs

✓ KEYWORDS
✓ IDENTIFIERS
✓ WHITE SPACE CHARACTERS
✓ COMMENTS
✓ NUMBERS
✓ STRINGS
✓ LOGIC VALUES
✓ STRENGTHS
✓ DATA TYPES
✓ SCALARS AND VECTORS
✓ PARAMETERS
3) GATE LEVEL MODELING

✓ INTRODUCTION
✓ ALL GATE PRIMITIVE
✓ NET TYPES
✓ Gate delays
✓ Delay specification types Additional controls min/ typ/ max
✓ values in delays
✓ Design example of combinational Circuits with GATE PRIMITIVES
✓ DESIGN OF FLIP-FLOPS With GATE PRIMITIVES

4) MODELING AT DATA FLOW LEVEL

✓ Introduction
✓ Continuous Assignment Structures
✓ Delays And Continuous Assignments
✓ Assignment To Vectors
✓ Operators
✓ Additional Examples Using Operators

5) BEHAVIORAL MODELING

✓ Introduction
✓ Operations And Assignments
✓ Initial Construct
✓ Always Construct
✓ Assignments With Delays
✓ Wait Construct
✓ Multiple Always Blocks
✓ Designs At Behavioral Level (All Sequential Circuit)
✓ Blocking And Nonblocking Assignments
✓ The Case Statement
✓ If And If–else Constructs
✓ Assign–deassign Construct
✓ Repeat Construct
✓ For Loop
✓ The Disable Construct
✓ While Loop
✓ Forever Loop
✓ Parallel Blocks
✓ Force–release Construct
✓ Event
6) FUNCTIONS, TASKS, AND USER-DEFINED PRIMITIVES

✓ Introductiuon
✓ Function
✓ Tasks
✓ User-defined Primitives (Udp)
✓ Exercises

7) SWITCH LEVEL MODELING


✓ Introduction
✓ Basic Transistor Switches
✓ Cmos Switch
✓ Bidirectional Gates
✓ Time Delays With Switch Primitives
✓ Instantiations With Strengths And Delays
✓ Strength Contention With Trireg Nets
✓ Exercises

8) FSM
✓ Introduction
✓ Melay Machine
✓ Moore Machine
✓ Sequence Detector

9) Memory Design
✓ RAM
✓ ROM

10) Hands On Projects


✓ Asynchronous FIFO Verilog Code.
✓ I2S Interface
✓ I2C Interface
✓ Serial Peripheral Interface
✓ AMBA BUS (AXI-4,APB)
Assessment:

✓ Regular quizzes to reinforce understanding.


✓ Hands-on assignments to apply learned concepts.
✓ Final project to design and simulate a complex digital system using Verilog.

Prerequisites:

✓ Basic understanding of digital logic.


✓ Familiarity with programming concepts.

Duration:

✓ This course is designed to be completed in 8 to 10 weeks, with 2 hours of


instruction per week.

Target Audience:

✓ Electrical and Electronics Engineer. (3rd, 4th Year).


✓ Students pursuing courses in VLSI Design.
✓ Professionals working in semiconductor industry.

Payment: BDT 12k

Teaching Mood: Online

Upon completion of this course, participants will have a thorough understanding of Verilog
programming, enabling them to design, simulate, and analyze digital circuits effectively. They will be
equipped with practical skills and knowledge to tackle complex digital design challenges in various
domains.

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