Kingdom of Saudi Arabia

Ministry of Education
King Faisal University
College of Computer Sciences & Information Technology

Laboratory Manual

Digital Logic and Design

Computer Engineering Department

Name: _________________________

Student ID: _________________________

Section: _________________________

Prepared by: Naveed Rasul Last Updated: Mar 13th 2023

Digital Logic and Design Lab Manual Page 1

 Table of Contents
Lab 1 ................................................................................................................................................................................................. 3
1.1 To study the operation of AND, OR and NOT gates ............................................................................................. 4
Lab 2 ............................................................................................................................................................................................. ….7
2.1 To construct logic circuits ..................................................................................................................................... 8
Lab 3 ............................................................................................................................................................................................... 11
3.1 To study the Associative Law ............................................................................................................................... 12
3.2 To study the Distributive Law .............................................................................................................................. 14
3.3 To study the DeMorgan’s Law ............................................................................................................................. 16
Lab 4 ............................................................................................................................................................................................... 19
4.1 Implement AND, OR and NOT functions using NAND gates ................................................................................ 20
4.2 Implementation using NAND gates only .............................................................................................................. 22
Lab 5 ............................................................................................................................................................................................... 26
5.1 Boolean Algebra Simplification ............................................................................................................................. 27
5.2 K-map Simplification ............................................................................................................................................ 29
Lab 6 ............................................................................................................................................................................................... 32
6 Logical Circuit Design ........................................................................................................................................... 33
Lab 7 ............................................................................................................................................................................................... 36
7.1 Design a BCD to Seven Segment Display Decoder Circuit ..................................................................................... 37
7.2 Seven Segment Display ........................................................................................................................................ 40
Lab 8 ............................................................................................................................................................................................... 43
8.1 Half Adder and Full Adder..................................................................................................................................... 44
8.2 4-bit Adder Circuit ................................................................................................................................................ 46
Lab 9 ............................................................................................................................................................................................... 49
9.1 Design 3-8-line decoder circuit ............................................................................................................................. 50
9.2 Design 8-1-line multiplexer circuit ....................................................................................................................... 53
Lab 10 ............................................................................................................................................................................................. 56
10.1 SR Flip Flop ........................................................................................................................................................... 57
10.2 D Flip Flop ............................................................................................................................................................ 59
10.3 JK Flip Flop ............................................................................................................................................................ 61
Lab 11 ............................................................................................................................................................................................. 64
11.1 Asynchronous Counter ......................................................................................................................................... 65
11.2 Synchronous Counter ........................................................................................................................................... 67
Appendix ........................................................................................................................................................................................ 70

Digital Logic and Design Lab Manual Page 2

 Lab 1

Digital Logic and Design Lab Manual Page 3

 Experiment 1.1

Objective: To study the operation of AND, OR and NOT gates

Equipment:

- COM3LAB Master unit

- COM3LAB Digital Technology 1 (DT1) module
- Jumpers

Circuit Diagram:

AND Gate

Fig 1.1

OR Gate

Fig 1.2

Digital Logic and Design Lab Manual Page 4

NOT Gate

Fig 1.3

Procedure:

1. Start COM3LAB software with Digital Technology 1 module.

2. Connect the circuits as shown in Fig 1.1, 1.2 and 1.3.

3. Change the values of inputs A and B using switches S0 and S1 respectively and observe output
Q connected to LED H0 for the logic circuits shown in Fig 1.1, 1.2 and 1.3.

4. Record the observations by filling out Table 1.1, 1.2 and 1.3 respectively.

Observations and Results:

A B Q A B Q A Q
0 0 0 0 0
0 1 0 1 1
1 0 1 0
1 1 1 1

Table 1.1 Table 1.2 Table 1.3

Digital Logic and Design Lab Manual Page 5

Exercise:

1. Write the names of the logic gates whose symbols are shown below:

Symbol Name of Gate Symbol Name of Gate

2. Fill in the table below for the operations mentioned in the respective columns.
___ ___

A B A B A . B A + B
0 0
0 1
1 0
1 1

Name: _________________________

Student ID: _________________________

Instructor Signature: _________________________

Digital Logic and Design Lab Manual Page 6

 Lab 2

Digital Logic and Design Lab Manual Page 7

 Experiment 2.1

Objective: To construct logic circuits

Equipment:

- COM3LAB Master unit

- COM3LAB Digital Technology 1 (DT 1) module
- COM3LAB software
- Jumpers

Circuit Diagram:

_
A . B

Fig 2.1

_ _
A . B + A . B

Fig 2.2

Digital Logic and Design Lab Manual Page 8

 _____
A + B

Fig 2.3

Procedure:

1. Start COM3LAB software with Digital Technology 1 module.

2. Connect the circuits as shown in Fig 2.1, 2.2 and 2.3.

3. Change the values of inputs A and B using switches S0 and S1 respectively and observe output
Q connected to LED H0 for the logic circuits shown in Fig 2.1, 2.2 and 2.3.

4. Record these observations by filling out Table 2.1, 2.2 and 2.3 respectively.

Observations and Results:

A B Q A B Q A B Q
0 0 0 0 0 0
0 1 0 1 0 1
1 0 1 0 1 0
1 1 1 1 1 1

Table 2.1 Table 2.2 Table 2.3

Digital Logic and Design Lab Manual Page 9

Exercise:

1. Write the logical expression for output Q in the logical circuit shown below:

Logical Expression: _____________________

2. Draw the logic circuit diagram for the logical expression shown below:
_ _
A . B + C. ( A + B )

Name: _________________________

Student ID: _________________________

Instructor Signature: _________________________

Digital Logic and Design Lab Manual Page 10

 Lab 3

Digital Logic and Design Lab Manual Page 11

 Experiment 3.1

Objective:

To study the Associative Law.

( A . B ) . C = A . ( B . C )

( A + B ) + C = A + ( B + C )

Equipment:

- COM3LAB Master unit

- COM3LAB Digital Technology 1 (DT 1) module
- COM3LAB software
- Jumpers

Circuit Diagram:

( A . B ) . C A . ( B . C )

Fig 3.1 Fig 3.2

( A + B ) + C A + ( B + C )

Fig 3.3 Fig 3.4

Digital Logic and Design Lab Manual Page 12

Procedure:

1. Start COM3LAB software with Digital Technology 1 module.

2. Connect the circuits as shown in Fig 3.1, 3.2, 3.3 and 3.4.

3. Change the values of inputs A, B and C using switches S0, S1 and S2 respectively and observe
output Q connected to LED H0 for the logic circuits shown in Fig 3.1, 3.2, 3.3 and 3.4.

4. Record these observations by filling out Table 3.1, 3.2, 3.3 and 3.4 respectively.

5. Compare Table 3.1 and Table 3.2 to see if both are same. Also, compare Table 3.3
and Table 3.4 to see if both are same.

Observations and Results:

A B C Q A B C Q
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 1 1 0
1 1 1 1 1 1

Table 3.1: Truth Table for circuit Table 3.2: Truth Table for circuit
shown in Fig 3.1 shown in Fig 3.2

A B C Q A B C Q
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 1 1 0
1 1 1 1 1 1

Table 3.3: Truth Table for circuit Table 3.4: Truth Table for circuit
shown in Fig 3.3 shown in Fig 3.4

Digital Logic and Design Lab Manual Page 13

 Experiment 3.2

Objective:

To study the Distributive Law.

A . ( B + C ) = A . B + A . C

A + B . C = ( A + B ) . ( A + C )

Equipment:

- COM3LAB Master unit

- COM3LAB Digital Technology 1 (DT 1) module
- COM3LAB software
- Jumpers

Circuit Diagram:

A . ( B + C ) A . B + A . C

Fig 3.5 Fig 3.6

A + B . C ( A + B ) . ( A + C )

Fig 3.7 Fig 3.8

Digital Logic and Design Lab Manual Page 14

Procedure:

1. Start COM3LAB software with Digital Technology 1 module.

2. Connect the circuits as shown in Fig 3.5, 3.6, 3.7 and 3.8.

3. Change the values of inputs A, B and C using switches S0, S1 and S2 respectively and observe
output Q connected to LED H0 for the logic circuits shown in Fig 3.5, 3.6, 3.7 and 3.8.

4. Record these observations by filling out Table 3.5, 3.6, 3.7 and 3.8 respectively.

5. Compare Table 3.5 and Table 3.6 to see if both are same. Also, compare Table 3.7
and Table 3.8 to see if both are same.

Observations and Results:

A B C Q A B C Q
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 1 1 0
1 1 1 1 1 1

Table 3.5: Truth Table for circuit Table 3.6: Truth Table for circuit
shown in Fig 3.5 shown in Fig 3.6

A B C Q A B C Q
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 1 1 0
1 1 1 1 1 1

Table 3.7: Truth Table for circuit Table 3.8: Truth Table for circuit
shown in Fig 3.7 shown in Fig 3.8

Digital Logic and Design Lab Manual Page 15

 Experiment 3.3

Objective:

To study the DeMorgan’s Law

_____ _ _
A . B = A + B
_____ _ _
A + B = A . B

Equipment:

- COM3LAB Master unit

- COM3LAB Digital Technology 1 (DT 1) module
- COM3LAB software
- Jumpers

Circuit Diagram:

_____ _ _
A . B A + B

Fig 3.9 Fig 3.10

_____ _ _
A + B A . B

Fig 3.11 Fig 3.12

Digital Logic and Design Lab Manual Page 16

Procedure:

1. Start COM3LAB software with Digital Technology 1 module.

2. Connect the circuits as shown in Fig 3.9, 3.10, 3.11 and 3.12.

3. Change the values of inputs A and B using switches S0 and S1 respectively and observe output
Q connected to LED H0 for the logic circuits shown in Fig 3.9, 3.10, 3.11 and 3.12.

4. Record these observations by filling out Table 3.9, 3.10, 3.11 and 3.12 respectively.

5. Compare Table 3.9 and Table 3.10 to see if both are same.

6. Also, compare Table 3.11 and Table 3.12 to see if both are same.

Observations and Results:

A B Q A B Q
0 0 0 0
0 1 0 1
1 0 1 0
1 1 1 1

Table 3.9: Truth Table for circuit Table 3.10: Truth Table for circuit
in Fig 3.9 in Fig 3.10

A B Q A B Q
0 0 0 0
0 1 0 1
1 0 1 0
1 1 1 1

Table 3.11: Truth Table for circuit Table 3.12: Truth Table for circuit
in Fig 3.11 in Fig 3.12

Digital Logic and Design Lab Manual Page 17

Exercise:

For the logical expressions below, choose the correct choices.

_
1. X . ( Y + Z) = __________________

_
a) X . Y + X . Z
_
b) X + Y . Z
_
c) ( X . Y ) + Z

d) ( X + Y ) . ( X + Z )

_____
_
2. X + Y = __________________

_
a) X + Y
_
b) X + Y
_
c) X . Y
_
a) X . Y

Name: _________________________

Student ID: _________________________

Instructor Signature: _________________________

Digital Logic and Design Lab Manual Page 18

 Lab 4

Digital Logic and Design Lab Manual Page 19

 Experiment 4.1

Objective: Implement AND, OR and NOT functions using NAND gates

Equipment:

- COM3LAB Master unit

- COM3LAB Digital Technology 1 (DT 1) module
- COM3LAB software
- Jumpers

Circuit Diagram:

Fig 4.1

Fig 4.2

Digital Logic and Design Lab Manual Page 20

 Fig 4.3

Procedure:

1. Start COM3LAB software with Digital Technology 1 module.

2. Connect the circuits as shown in Fig 4.1, 4.2 and 4.3.

3. Change the values of inputs A and B using switches S0 and S1 respectively and observe output
Q connected to LED H0 for the logic circuits shown in Fig 4.1, 4.2 and 4.3.

4. Record these observations by filling out Table 4.1, 4.2 and 4.3 respectively.

5. Compare the Table 4.1, 4.2 and 4.3 to the truth tables of NOT, AND and OR logic operations
respectively to see if they are identical.

Observations and Results:

A Q A B Q A B Q
0 0 0 0 0
1 0 1 0 1
1 0 1 0
1 1 1 1

Table 4.1 Table 4.2 Table 4.3

Digital Logic and Design Lab Manual Page 21

 Experiment 4.2

Objective:

Implementation using NAND gates only

Equipment:

- COM3LAB Master unit

- COM3LAB Digital Technology 1 (DT 1) module
- COM3LAB software
- Jumpers

Circuit Diagram:

Fig 4.4

Fig 4.5

Digital Logic and Design Lab Manual Page 22

 Fig 4.6

Fig 4.7

Procedure:

1. Start COM3LAB software with Digital Technology 1 module.

2. Connect the circuit as shown in Fig 4.4.

3. Change the values of inputs A, B and C using switches S0, S1 and S2 respectively and observe
output Q connected to LED H0 for the logic circuit shown in Fig 4.4. Record these
observations by filling out Table 4.4.

4. The AND, OR and NOT gates are replaced with respective NAND implementations as shown in
Fig 4.5.

Digital Logic and Design Lab Manual Page 23

 5. The back-to-back NOT equivalents in Fig 4.5 are crossed out. This results in the circuit
shown in Fig 4.6.
6. Connect the circuit as shown in Fig 4.7.

7. Change the values of inputs A, B and C using switches S0, S1 and S2 respectively and observe
output Q connected to LED H0 for the logic circuit shown in Fig 4.7. Record these
observations by filling out Table 4.5.

8. Compare Table 4.4 and 4.5 to see if they are identical.

Observations and Results:

A B C Q A B C Q

0 0 0 0 0 0

0 0 1 0 0 1

0 1 0 0 1 0
0 1 1 0 1 1

1 0 0 1 0 0
1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Table 4.4: Truth Table for circuit Table 4.5: Truth Table for circuit
in Fig 4.4 in Fig 4.7

Digital Logic and Design Lab Manual Page 24

Exercise:

Draw the two symbols for NAND and NOR gates and also write their truth tables.

NAND Gate: NOR Gate:

Symbols for NAND Gate Symbols for NOR Gate

A B Q A B Q
0 0 0 0
0 1 0 1
1 0 1 0
1 1 1 1

Truth Table for NAND Gate Truth Table for NOR Gate

Name: _________________________

Student ID: _________________________

Instructor Signature: _________________________

Digital Logic and Design Lab Manual Page 25

 Lab 5

Digital Logic and Design Lab Manual Page 26

 Experiment 5.1

Objective: Boolean Algebra Simplification

Equipment:
- Logisim Simulator

Circuit Diagram:
_ _ _ _ _ _ _ _
A B C + A B C + A B C + A B C + A B C

Fig 5.1

_ _ _
B C + B C + A B

Fig 5.2

Digital Logic and Design Lab Manual Page 27

Procedure:

1. Simplify the logic expression below using boolean algebra rules.

_ _ _ _ _ _ _ _
A B C + A B C + A B C + A B C + A B C

2. Build the circuits for the two logic expressions (original and simplified) using the LOGISIM
simulator.

3. Find the truth tables for two circuits and record these observations in Table 5.1 and Table
5.2.

4. Compare the two truth tables to see if they are identical.

Observations and Results:

A B C Q A B C Q
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 1 1 0
1 1 1 1 1 1

Table 5.1 Table 5.2

Digital Logic and Design Lab Manual Page 28

 Experiment 5.2

Objective:

K-map Simplification

Equipment:

- Logisim Simulator

Circuit Diagram:

_ _ _ _ _ _ _ _ _ _
A B C D + A B C D + A B C + A C D + A C D + C D

Fig 5.3

Digital Logic and Design Lab Manual Page 29

 _ _ _ _
D + A C + A B C

Fig 5.4

Procedure:

1. Simplify the logic expression below using K-map.

_ _ _ _ _ _ _ _ _ _
A B C D + A B C D + A B C + A C D + A C D + C D

Simplified Expression: ________________________________

2. Build the circuits for the two logic expressions (original and simplified) using the LOGISIM
simulator.

3. Find the truth tables for two circuits and record these observations in Table 5.3 and Table
5.4.

4. Compare the two truth tables to see if they are identical.

Digital Logic and Design Lab Manual Page 30

Observations and Results:

A B C D Q A B C D Q

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 0

0 0 1 1 0 0 1 1

0 1 0 0 0 1 0 0
0 1 0 1 0 1 0 1

0 1 1 0 0 1 1 0

0 1 1 1 0 1 1 1
1 0 0 0 1 0 0 0

1 0 0 1 1 0 0 1
1 0 1 0 1 0 1 0
1 0 1 1 1 0 1 1

1 1 0 0 1 1 0 0
1 1 0 1 1 1 0 1
1 1 1 0 1 1 1 0

1 1 1 1 1 1 1 1

Table 5.3 Table 5.4

Name: _________________________

Student ID: _________________________

Instructor Signature: _________________________

Digital Logic and Design Lab Manual Page 31

 Lab 6

Digital Logic and Design Lab Manual Page 32

 Experiment 6

Objective:

Logical Circuit Design

Equipment:

- Logisim Simulator
- COM3LAB Master unit
- COM3LAB Digital Technology 1 (DT 1) module
- COM3LAB software
- Jumpers

Problem Specification:

A three member committee requires a majority vote to decide if the student has passed or failed in the
graduation project. Design a circuit that turns an LED on if the majority voted for the student and turns
the LED off if the majority voted against the student.

Procedure:

1. Start the LOGISIM simulator and select Project >Analyze Circuit menu.

2. In the Input tab, mention the number of inputs for the above mentioned problem. In the
Outputs tab, mention the number of outputs.

3. Derive the truth table for the problem logic mentioned in the problem specification and write it
down in truth table shown in Table tab. Also, write down the truth table in Table 6.2.

4. The Minimized tab shows the K-Map for the output and derives the simplified output
expression. Write them down in the K-Map shown in Fig 6.2.

5. Click Build Circuit button and select Use two-input Gates Only option. The software
displays the logic circuit for the problem. Draw the circuit in Fig 6.3.

6. Save the design and logic circuit using File > Save As menu.

7. Implement the circuit in Fig 6.3 on the experiment board.

8. Change the values of inputs A, B and C using switches and observe the output Q on the LED.
Record these observations by filling out Table 6.4.

5. Compare the observations in Table 6.4 with the design criteria mentioned in Table 6.1 to
see if they are identical and are in compliance with the problem specification.

Digital Logic and Design Lab Manual Page 33

Observations and Results:

A B C Q

0 0 0
0 0 1

0 1 0

0 1 1
1 0 0

1 0 1

1 1 0

1 1 1

Table 6.1: Derived Truth Table

00 01 11 10
0

Simplified Output Expression: ___________________

Fig 6.2: K-Map for simplified output expression

Fig 6.3: Circuit diagram

Digital Logic and Design Lab Manual Page 34

 A B C Q

0 0 0
0 0 1

0 1 0

0 1 1

1 0 0
1 0 1

1 1 0
1 1 1

Table 6.4: Truth Table for circuit shown in Fig 6.3

Name: _________________________

Student ID: _________________________

Instructor Signature: _________________________

Digital Logic and Design Lab Manual Page 35

 Lab 7

Digital Logic and Design Lab Manual Page 36

 Experiment 7.1

Objective: Design a BCD to Seven Segment Display Decoder Circuit

Equipment:

- Logisim Simulator

Diagram:

Inputs Outputs
A B C D a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
1 0 1 0 x x x x x x x
1 0 1 1 x x x x x x x
1 1 0 0 x x x x x x x Fig 7.2
1 1 0 1 x x x x x x x
1 1 1 0 x x x x x x x
1 1 1 1 x x x x x x x

Fig 7.1

Procedure:

1. Start LOGISIM simulator and select Project >Analyze Circuit menu.

2. In the Input tab, mention the number of inputs and in the Outputs tab, mention the number of
outputs as shown in Fig 7.1.

3. in Table tab, write down the truth table as shown in Fig 7.1.

4. Click Build Circuit button and the software displays the logic circuit shown in Fig 7.3

5. Construct the circuit shown in Fig 7.4 by using seven segment display.

Digital Logic and Design Lab Manual Page 37

 6. Save the design and logic circuit using File > Save As menu.

7. Change the values of inputs A, B, C and D and observe the output on the seven segment display
and record it in Table 7.1.

Fig 7.4

Fig 7.3

Digital Logic and Design Lab Manual Page 38

Observations and Results:

A B C D Q

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

Table 7.1

Digital Logic and Design Lab Manual Page 39

 Experiment 7.2

Objective: Seven Segment Display

Equipment:

- COM3LAB Master unit

- COM3LAB Digital Technology 1 (DT 1) module
- COM3LAB software
- Jumpers

Circuit Diagram:

Fig 7.4

Procedure:

1. Start COM3LAB software with Digital Technology 1 module.

2. Connect the circuit as shown in Fig 7.4.

3. Change the values of inputs D0, D1, D2 and D3 using switches S0, S1, S2 and S3 respectively
as shown in Table 7.2 and observe the output of seven segment display.

4. Record these observations by filling out Table 7.2.

Digital Logic and Design Lab Manual Page 40

Observations and Results:

S0 S1 S2 S3 Q

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

Table 7.2

Digital Logic and Design Lab Manual Page 41

Exercise:

1. If the BCD - 7 Segment decoder circuit produces the following outputs, which letters will be
displayed on the 7-segment display?

a b c d e f g Q

1 1 0 0 1 1 1

1 0 0 0 1 1 1

2. For the BCD - 7 Segment decoder circuit, determine the circuit outputs to display the following
letters on the 7-segment display?

Q a b c d e f g

Name: _________________________

Student ID: _________________________

Instructor Signature: _________________________

Digital Logic and Design Lab Manual Page 42

 Lab 8

Digital Logic and Design Lab Manual Page 43

 Experiment 8.1

Objective: Half Adder and Full Adder

Equipment:

- COM3LAB Master unit

- COM3LAB Digital Technology 1 (DT 1) module
- COM3LAB software
- Jumpers

Circuit Diagram:

Fig 8.1

Fig 8.2

Digital Logic and Design Lab Manual Page 44

Procedure:

1. Start the COM3LAB software with Digital Technology 1 module.

2. Connect the circuits as shown in Fig 8.1 and 8.2.

3. Change the values of inputs A and B using switches S0 and S1 respectively and observe the
outputs S and C on LEDs H0 and H1 respectively.

4. Record these observations by filling out Table 8.1 and 8.2 respectively.

Observations and Results:

A B C S
0 0
0 1
1 0
1 1

Table 8.1

A B C C1 S
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Table 8.2

Digital Logic and Design Lab Manual Page 45

 Experiment 8.2
Objective: 4-bit Adder

Equipment:
- Logisim Simulator

Circuit Diagram:

Fig 8.1 Fig 8.2

Fig 8.3

Fig 8.4

Digital Logic and Design Lab Manual Page 46

Procedure:

1. Start the LOGISIM simulator.

2. Construct a half adder circuit as shown in Fig 8.1.

3. Construct a full adder circuit by joining two half adder circuits as shown in Fig 8.2.

4. Change the values of inputs and observe the output and record these observations by filling out
Table 8.2.

5. Construct a 4-bit full adder circuit by joining four full adder circuits as shown in Fig 8.3.

6. Change the values of inputs and observe the output.

7. Record these observations by filling out Table 8.3.

8. Build the circuit in Fig 8.4 and test this out.

Observations and Results:

A B S
A3 A2 A1 A0 B3 B2 B1 B0 C4 S3 S2 S1 S0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 1
0 1 0 0 0 1 0 1
0 1 1 1 0 1 1 0
1 0 0 0 1 0 0 0
1 0 1 0 1 0 1 1
1 1 0 1 1 1 0 0
1 1 1 1 1 1 1 1

Table 8.3

Digital Logic and Design Lab Manual Page 47

Exercise:

1. If A and B are the input of a half adder, the carry is given by:

a) A + B

b) A . B

c) A B
______
d) A B

2. How many bits are added by a full adder circuit :

a) 2

b) 3

c) 4

d) 5

3. How many full adder circuits are required to design a circuit needed to add two 8-bit numbers
together?

a) 2

b) 8

c) 16

d) 32

Name: _________________________

Student ID: _________________________

Instructor Signature: _________________________

Digital Logic and Design Lab Manual Page 48

 Lab 9

Digital Logic and Design Lab Manual Page 49

 Experiment 9.1

Objective:

Design 3-8-line decoder circuit

Equipment:

- Logisim Simulator

Circuit Diagram:

Digital Logic and Design Lab Manual Page 50

 Fig 9.1

Fig 9.2

Procedure:

Digital Logic and Design Lab Manual Page 51

 1. Start the LOGISIM simulator.

2. Construct a 3-8-line decoder circuit as shown in Fig 9.1.

3. Change the inputs A2, A1 and A0 and observe the outputs D0, D1, D2, D3, D4, D5, D6 and D7.
Record these observations in Table 9.1.

4. Construct the circuit in Fig 9.2 and compare the results with the observations in Table 9.1.

Observations and Results:

A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Table 9.1

Digital Logic and Design Lab Manual Page 52

 Experiment 9.2

Objective:

Design 8-1-line multiplexer circuit

Equipment:

- Logisim Simulator

Circuit Diagram:

Fig 9.3

Digital Logic and Design Lab Manual Page 53

 Fig 9.4

Procedure:

1. Start the LOGISIM simulator.

2. Construct a 8-1-line multiplexer circuit as shown in Fig 9.3.

3. Change the inputs S2, S1 and S0 and observe the output Q. Record these observations in
Table 9.2.

4. Construct the circuit in Fig 9.4 and compare the results with the observations in Table 9.2.

Observations and Results:

S2 S1 S0 Q
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Table 9.2

Digital Logic and Design Lab Manual Page 54

Exercise:

1. The number of output(s) in a decoder with 4 inputs are:

a) 1

b) 4

c) 8

d) 16

2. The number of select lines in 8-1- multiplexer are:

a) 1

b) 2

c) 3

d) 8

Name: _________________________

Student ID: _________________________

Instructor Signature: _________________________

Digital Logic and Design Lab Manual Page 55

 Lab 10

Digital Logic and Design Lab Manual Page 56

 Experiment 10.1

Objective: SR Flip Flop

Equipment:

- COM3LAB Master unit

- COM3LAB Digital Technology 2 (DT 2) module
- COM3LAB software
- Jumpers

Circuit Diagram:

Fig 10.1

Procedure:

1. Start COM3LAB software with Digital Technology 2 module.

2. Connect the circuit as shown in Fig 10.1.

3. Change the values of inputs S and R using switches S0 and S1 respectively and observe output
Q on LED H0.

4. Record these observations by filling out Table 10.1.

5. Rearrange the contents of Table 10.1 into Table 10.2.

6. By observing columns Qn-1 and Q in Table 10.2, fill out Table 10.3.

Digital Logic and Design Lab Manual Page 57

Observations and Results:

Qn-1 S R Q S R Qn-1 Q
0 0 1 0 0 0
0 1 0 0 0 1
1 0 0 0 1 0
1 1 0 0 1 1
1 0 1 1 0 0
0 0 0 1 0 1

Table 10.1 Table 10.2

S R Q
0 0
0 1
1 0
1 1 X

Table 10.3

Digital Logic and Design Lab Manual Page 58

 Experiment 10.2

Objective: D Flip Flop

Equipment:

- COM3LAB Master unit

- COM3LAB Digital Technology 2 (DT 2) module
- COM3LAB software
- Jumpers

Circuit Diagram:

Fig 10.2

Procedure:

1. Start COM3LAB software with Digital Technology 2 module.

2. Connect the circuit as shown in Fig 10.2.

3. Change the values of inputs C and D using switches S0 and S1 respectively and observe output
Q on LED H0.

4. Record these observations by filling out Table 10.4.

5. Rearrange the contents of Table 10.4 into Table 10.5.

6. By observing columns Qn-1 and Q in Table 10.5, fill out Table 10.6.

Digital Logic and Design Lab Manual Page 59

Observations and Results:

Qn-1 C D Q C D Qn-1 Q
0 0 1 0 0 0
0 1 0 0 0 1
0 1 1 0 1 0
1 0 0 0 1 1
1 0 1 1 0 0
1 1 1 1 0 1
1 1 0 1 1 0
0 0 0 1 1 1

Table 10.4 Table 10.5

C D Q
0 0
0 1
1 0
1 1

Table 10.6

Digital Logic and Design Lab Manual Page 60

 Experiment 10.3

Objective: JK Flip Flop

Equipment:

- COM3LAB Master unit

- COM3LAB Digital Technology 2 (DT 2) module
- COM3LAB software
- Jumpers

Circuit Diagram:

Fig 10.3

Procedure:

1. Start COM3LAB software with Digital Technology 2 module.

2. Connect the circuit as shown in Fig 10.3.

3. Change the values of inputs J, K and C using switches S0, S1 and S2 respectively and observe
output Q on LED H0 and H1.

4. Record these observations by filling out Table 10.7.

5. Rearrange the contents of Table 10.7 into Table 10.8.

6. By observing columns Qn-1 and Q in Table 10.8, fill out Table 10.9.

Digital Logic and Design Lab Manual Page 61

Observations and Results:

Qn-1 J K C Q J K C Qn-1 Q
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
1 1 0 1 0 0
1 0 1 1 0 1
0 1 1 1 1 0
1 1 1 1 1 1

Table 10.7 Table 10.8

J K C Q
0 0
0 1
1 0
1 1

Table 10.9

Digital Logic and Design Lab Manual Page 62

Exercise:

1. In SR Flip Flop, which settings result in an irregular state?

a) S = 0 R = 0
b) S = 0 R = 1
c) S = 1 R = 0
d) S = 1 R = 1

2. What will be output of D Flip Flop, if C = 1 and D = 1?

a) 0
b) 1

3. Determine whether the symbols below identify a positive or negative

edge triggered JK flip flop?

_________________________

_________________________

4. The output of a –ive edge triggered JK flip flop is 1. If J = 1 and

K = 1, what will be output after the application of three –ive edges?

a) 0
b) 1

Name: _________________________

Student ID: _________________________

Instructor Signature: _________________________

Digital Logic and Design Lab Manual Page 63

 Lab 11

Digital Logic and Design Lab Manual Page 64

 Experiment 11.1

Objective: Asynchronous Counter

Equipment:

- COM3LAB Master unit

- COM3LAB Digital Technology 2 (DT 2) module
- COM3LAB software
- Jumpers

Circuit Diagram:

Fig 11.1

Fig 11.2

Digital Logic and Design Lab Manual Page 65

Procedure:

1. Start COM3LAB software with Digital Technology 2 module.

2. Connect the circuits as shown in Fig 11.1 and Fig 11.2.

3. Apply the –ive edge of clock pulse by pressing and releasing the switch S0 repeatedly and
observe outputs on seven-segment display.

4. Record these observations by filling out Table 11.1 and Table 11.2.

Observations and Results:

Table 11.1: Counting Sequence for Table 11.2: Counting Sequence for
circuit in Fig 11.1 circuit in Fig 11.2

Digital Logic and Design Lab Manual Page 66

 Experiment 11.2

Objective: Synchronous Counter

Equipment:

- COM3LAB Master unit

- COM3LAB Digital Technology 2 (DT 2) module
- COM3LAB software
- Jumpers

Circuit Diagram:

Fig 11.3

Fig 11.4

Digital Logic and Design Lab Manual Page 67

Procedure:

1. Start COM3LAB software with Digital Technology 2 module.

2. Connect the circuits as shown in Fig 11.3 and Fig 11.4.

3. Apply the –ive edge of clock pulse by pressing and releasing the switch S0 repeatedly and
observe output on seven-segment display.

4. Record these observations by filling out Table 11.3 and Table 11.4.

Observations and Results:

Table 11.3: Counting Sequence for Table 11.4: Counting Sequence for
circuit in Fig 11.3 circuit in Fig 11.4

Digital Logic and Design Lab Manual Page 68

Exercise:

1. The current state of MOD 8 forward counter is 110, what will be

counter state of the application of 3 clock pulses?

a) 001

b) 010

c) 011

d) 111

2. The current state of MOD 8 reverse counter is 011, what will be

counter state of the application of 4 clock pulses?

a) 001

b) 010

c) 011

d) 111

Name: _________________________

Student ID: _________________________

Instructor Signature: _________________________

Digital Logic and Design Lab Manual Page 69

 Appendix

AND Gate

OR Gate

Fig 1.6

NOT Gate

Digital Logic and Design Lab Manual Page 70