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COA Major Assignment4

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17 views2 pages

COA Major Assignment4

Uploaded by

V Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CSE 2011: Computer Organization and Architecture

ASSIGNMENT 5:
Implementaion of recursion using MIPS ISA and design of processor data path and control.
Due date: 16.4.2016(Saturday)
This assignment is designed to give you practice with:
1. Implementation of recursive procedure using MIPS instruction set.
2. Design of processor datapath and control for single cycle implementation and
pipeline implementation.

(You are allowed to use only those concepts which are covered in the lecture class till date.)
Plagiarized assignments will be given a zero mark.
1. Write an assembly language program to read two integers through console.
-Find the GCD between two numbers using recursion,
where GCD(m,n)=n (if m%n=0)
= GCD(n,m%n), otherwise.
2. Write a recursive function to find the sum of digits of a number n.
Where sumdig=0 (if n=0)
= (n%10)+sumdig(n/10)
3. Write a recursive function in MIPS to generate first n terms of the fibonacci series.
4. Assume we are going to design a processor, data path and control for the following subset
of instructions:
lh, sh, bne, sub, and, ori.
The 2bit AluOp and the corresponding ALU operations for these instructions are as per the
table below.

Instruction ALUOp ALU Function


lh 00 add
sh 00 add
bne 01 sub
sub 10 sub
and 10 and
ori 11 or

(a) Identify the different steps of execution for each instruction.


(b) Identify the datapath components and control signals needed for implementation of
each instruction.
(c) Design a single data path supporting the implementation of all the above instructions.
(d) Specify the value of each control signal used in the designed data path.
(e) Specify the new functional units need to be added to the designed datatpath so that it
will able to support implementation of a new instruction “add3 Rd, Rs, Rt, Rx”.
5. The logic blocks needed to implement a processor's data path have the following latencies.
I-Mem Adder Mux ALU RegRead RegWrite D-Mem Sign-Extnd Shift-Left-2
a 400ps 100ps 30ps 120ps 100ps 100ps 350ps 20ps 2ps
b 500ps 150ps 100ps 180ps 110ps 110ps 1000ps 90ps 20ps

[Hint: If any phase of instruction execution uses two or more data path conponents
parallelly, (i.e one's input does not depends on another's output) then the time
required for that phase is the time required for the slowest component in that step.]
• What would be the clock cycle time required for the processor to implement 5
consequitive fetch instructions using single clock cycle implementation?
• What is the total clock cycle time required by the processor for implementation of
each of the following instructions:
beq, lw, sw, ori.
6. Assume that the following sequenses of instructions are executed on a five stage pipelined
data path.

Sequence 1 Sequence 2 Sequence 3 Sequence 4


lw $t0 0($t0) sub $t1 $t0 $t0 addi $t1 $t0 1 add $t1 $t0 $t2
add $t1 $t0 $t0 ori $t2 $t1 5 addi $t2 $t0 2 add $t5 $t0 $t3
add $t4 $t2 $t1 addi $t3 $t0 2 sw $t1 10($t4)
addi $t3 $t0 4
add $t5 $t0 $t1

(a) Represent each set of instructions using the multiple clock cycle pipeline diagram.
(b) Indicate the dependencies in the pipeline diagram for each code sequence.
(c) Indicate the type of hazard by analyzing the dependencies.
(d) For each code sequence, state whether it must stall. Can avoid stalls using only forwarding
or can execute without stalling or forwarding.

Submission and Grading:

Submit your hard copy assignment by the due date, i.e. 16.4.2016(Saturday).

Part of your assignment grade comes from its "external correctness." This is based on
correct output on various sample inputs (like you have seen in the laboratory classes).
Your output should match the format of the sample run exactly.

The rest of your assignment's score comes from "internal correctness." Internal
correctness includes:
1. Use of minimal MIPS instructions and registers in your program.
2. Appropriate use of the theoretical concepts and suitable diagrams to enhance
readability of your responses.

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