ComputerOrganizationandArchitecture

COMPUTER
ORGANIZATION &
ARCHITECTURE
LAB MANUAL
for
Bachelor of Technology
in
Computer Science and Engineering& Master Of

LDC INSTITUTE OF TECHNICAL STUDIES SORAON PRAYAGRAJ

Lab manual Prepared by: Harshit Mishra CSE

2nd year
Roll no. 22028301000019

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ComputerOrganizationandArchitecture

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING &

MASTER OF COMPUTER APPLICATION

COMPUTER ORGANIZATION
ANDARCHITECTURE

SUBJECT CODE-BCS-352
& KCA-152

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 LAB MANUAL

List of Experiments (Indicative & not limited to)

1. Implementing HALF ADDER, FULL ADDER using basic logic gates

2. Implementing Binary -to -Gray, Gray -to -Binary code conversions.
3. Implementing 3-8 line DECODER.
4. Implementing 4x1 and 8x1 MULTIPLEXERS.
5. Verify the excitation tables of various FLIP-FLOPS.
6. Design of an 8-bit Input/ Output system with four 8-bit Internal Registers.
7. Design of an 8-bit ARITHMETIC LOGIC UNIT.
8. Design the data path of a computer from its register transfer language description.
9. Design the control unit of a computer using either hardwiring or
microprogramming based on its registertransfer language description.
10. Implement a simple instruction set computer with a control unit and a data path.

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LABMANUAL

Experiment No: 1STUDYOFLOGICGATE

1.1Objective1.2Apparatusrequired1.3Theory1.4Observationtable1.5Calculation1.6Result1.7Discussion1.8Precautions

OBJECTIVE:-V e r i f i c a t i o n trutht a b l e s oflogicgates:NAND-7400, NOR-7402, NOT-7404,

AND-7408, OR-7432,
EX-OR-7486 EX-NOR-74266
APPARATUSREQUIRED:

S.No.
NameofApparatus
Range/Rating
Quantity

1
DIGITALTRAINERKIT
………
5
2
CONNECTINGLEAD
………..
ASPERREQUIREMENT
3
IC’s
NAND7400NOR7402

OR7432AND7408NOT7404
EXOR7486E X N O R 74266

10
4
WIRECUTTER,
POWERSUPPLY

01
FROMTRAINERKIT

THEORY:
LogicgatesareidealizedorphysicaldevicesimplementingaBooleanfunction,whichitperforms a logical operation on one or
more logical inputs and produce a single output.Depending on the context, the term may refer to an ideal logic gate,
one that has for instancezerorisetimeandunlimitedfanout oritmayreferto a non-ideal physical device.

Themainhierarchyisas follows:-
Basic Gates-(AND,OR,NOT)
UniversalGates-( N A N D , NOR)
AdvancedGates-( E X - O R , EXNOR)
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AND Gate: The AND operation is defined as the output as (1) one if and only if all the inputs are
(1) one. 7408 is the two Inputs AND gate IC.A&B are the Input terminals &Y is the Output terminal.
Y = A.B

OR Gate: The OR operation is defined as the output as (1) one if one or more than 0 inputs are
(1) one. 7432 is the two Input OR gate IC. A&B are the input terminals & Y is the Output terminal.
Y=A+B

NOT GATE: The NOT gate is also known as Inverter. It has one input (A) & one output (Y). IC No. is
7404. Its logical equation is,
Y = A’

NAND GATE: The IC no. for NAND gate is 7400. The NOT-AND operation is known as NAND
operation. If all inputs are 1 then output produced is 0. NAND gate is inverted AND gate.
Y = (A. B)’

NOR GATE: The NOR gate has two or more input signals but only one output signal. IC 7402 is
two I/P IC. The NOT- OR operation is known as NOR operation. If all the inputs are 0 then the
O/P is 1. NOR gate is inverted OR gate.
Y = (A+B)’

EX-OR GATE: The EX-OR gate can have two or more inputs but produce one output. 7486 is two
inputs IC. EX-OR gate is not a basic operation & can be performed using basic gates.

Y=A B

EX-NOR GATE: The EX-NOR gate can have two or more inputs but produce one output. 7486 is
two inputs IC. EX-NOR gate is not a basic operation & can be performed using basic gates.

Y = (A B)’ = AʘB

OBSERVATION TABLE

1. AND GATE: - Function of AND gate is to give the output true when both the inputs
are true. In all the other remaining cases output becomes false. Following table
justifies the statement:-
A B Y

0 0 0

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0 1 0

1 0 0

1 1 1

2. OR GATE: - Function of AND gate is to give the output true when any of the inputs
is/or true. In all the other remaining case(when all inputs are false) output
becomes false. Following table justifies the statement:-

A B Y

0 0 0
0 1 1
1 0 1
1 1 1

3. NOT GATE: - Function of NOR gate is to reverse the nature of the input .It converts

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 LABMANUA

true input to false and vice versa. Following table justifies the statement :-
A Y

0 1
1 0

UNIVERSAL GATES

4. NAND GATE: - Function of NAND gate is to give the output true when any of the
inputs is/or false. In all the other remaining case(when all inputs are true) output
becomes false. Following table justifies the statement:-
A B Y

0 0 1
0 1 1
1 0 1
1 1 0

5. NOR GATE: - Function of NOR gate is to give the output true when all inputs are

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 LABMANUA

false. In all the other remaining cases output becomes false. Following table justifies
the statement:-
A B Y

0 0 1
0 1 0
1 0 0
1 1 0

SPECIAL GATES

6. EX-OR GATE : - Function of EX-OR gate is to give the output true when two inputs
are in different states (if one is true and another is false). In all the other remaining
cases output becomes false. Following table justifies the statement:-
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

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7. EX-NOR GATE: - Function of AND gate is to give the output true when both the
inputs are same in state(either both are true or both are false). In all the other
remaining cases output becomes false. Following table justifies the statement:-
A B Y
0 0 1
0 1 0
1 0 0
1 1 1

Result:-

All logic gates are verified. Observed output matches theoretical concepts.

PRECAUTION:-

1. Connecting wires should be rubbed with sand papers so that there is no rust.

2. Make sure that the apparatus is switched off while placing ICs and connecting of wires.

3. The connections should be tights.

4. ICs are placed in a proper way in the breadboard. There is no short of current in the in
same inputs.

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 LAB MANUAL

Experiment No: 2

STUDY OF HALF ADDER & FULL ADDER

1.1 Objective 1.2 Apparatus required 1.3 Theory 1.4 Observation table 1.5 Calculation 1.6 Result
1.7 Discussion 1.8 Precautions 1.9 Pre-Requisite 1.10 Post- Requisite

OBJECTIVE: To design and construct half adder and half subtractor circuits and verify the truth
table using logic gates.

1.2 APPARATUS REQUIRED:

S. Name of Apparatus Range/ Quantity

No Rating
.
1 DIGITAL TRAINER KIT ……… 5

2 CONNECTING LEAD ……….. ………..

3 IC’s : AND-7408, OR-7432 10

EX-OR 7486,

NOT 7404

4 WIRE CUTTER, POWER As per

SUPPLY requirement

1.3 THEORY:

HALF ADDER:

A half adder has two inputs for the two bits to be added and two outputs one from the
sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is called as a
carry signal from the addition of the less significant bits sum from the X-OR Gate the carry out
from the AND gate.

FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of
three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder
cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken
from OR Gate.

The difference can be applied using X-OR Gate, borrow output can be implemented using
an AND Gate and an inverter.
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LOGIC DIAGRAM:

HALF ADDER

TRUTH TABLE:

A B CARRY SUM

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

K-Map for SUM: K-Map for CARRY

SUM = A’B + AB’ CARRY = AB

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FULL ADDER

FULL ADDER USING TWO HALF ADDER

TRUTH TABLE:

A B C CARRY SU
M

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

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1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC=A B C

K-Map for CARRY:

CARRY = AB + BC + AC

RESULT: The half adder and full adder circuits are studied and verified.

PROCEEDURE:

Connections are given as per circuit diagram.

Logical inputs are given as per circuit diagram.

Observe the output and verify the truth table.

PRECAUTIONS:-

1. Connecting wires should be rubbed with sand papers so that there is no rust.

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 LABMANUA

3. Make sure that the apparatus is switched off while placing ICs and connecting of wires.

3. The connections should be tights.

4. ICs are placed in a proper way in the breadboard. There should not be shorting of wires in
the same input.

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 LAB MANUAL

Experiment No: 3

STUDY OF HALF SUBTRACTOR & FULL

SUBTRACTOR

1.1 Objective 1.2 Apparatus required 1.3 Theory 1.4 Observation table 1.5 Calculation 1.6 Result
1.7 Discussion 1.8 Precautions 1.9 Pre-Requisite 1.10 Post- Requisite

OBJECTIVE: To design and construct half adder and half subtractor circuits and verify the truth
table using logic gates.

1.2 APPARATUS REQUIRED:

S. Name of Apparatus Range/ Quantity

No Rating
.
1 DIGITAL TRAINER KIT ……… 5

2 CONNECTING LEAD ……….. ………..

3 IC’s : AND-7408, OR-7432 10

EX-OR 7486,

NOT 7404

4 WIRE CUTTER, POWER As per

SUPPLY requirement

1.3 THEORY:

HALF SUBTRACTOR:

The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two
input and two outputs. The outputs are difference and borrow. The difference can be applied
using X-OR Gate, borrow output can be implemented using an AND Gate and an inverter.

FULL SUBTRACTOR:

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the
logic circuit should have three inputs and two outputs. The two half subtractor put together gives
a full subtractor .The first half subtractor will be C and A B. The output will be difference output of
full
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 LABMANUA

subtractor. The expression AB assembles the borrow output of the half subtractor and the second
term is the inverted difference output of first X-OR.

LOGIC DIAGRAM:

HALF SUBTRACTOR

TRUTH TABLE:
A B BORROW DIFFERENCE

0 0 0 0

0 1 1 1

1 0 0 1

1 1 0 0

K-Map for DIFFERENCE: K-Map for BORROW:

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 LABMANUA

DIFFERENCE = A’B + AB’ BORROW = A’B

FULL SUBTRACTOR:

TRUTH TABLE:

A B C BORROW DIFFERENCE

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 1 0

1 0 0 0 1

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

K-Map for Difference:

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 LABMANUA

Difference = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for Borrow:

Borrow = A’B + BC + A’C

RESULT: The half Subtractor and full Subtractor circuits are studied and verified.

PROCEEDURE:

Connections are given as per circuit diagram.

Logical inputs are given as per circuit diagram.

Observe the output and verify the truth table.

PRECAUTIONS:-

1. Connecting wires should be rubbed with sand papers so that there is no rust.

4. Make sure that the apparatus is switched off while placing ICs and connecting of wires.

5. The connections should be tights.

6. ICs are placed in a proper way in the breadboard. There should not be shorting of wires in
the same input.

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 LABMANUA

EXPERIMENT No. 4

Objective: To design and implement a binary to gray and gray to binary converter.

APPARATUS REQUIRED:

S. Name of Apparatus Range/ Quantity

No Rating
.
1 DIGITAL TRAINER KIT ……… 1

2 CONNECTING LEAD ……….. AS PER

REQUIREMENT
3 IC’s EXOR 7486 1

4 WIRE CUTTER, 01

POWER SUPPLY FROM TRAINER KIT

Theory:

The reflected binary code, also known as Gray code after Frank Gray, is a binary numeral system where two
successive values differ in only one bit. The reflected binary code was originally designed to prevent spurious
output from electromechanical switches. Today Gray codes are widely used to facilitate error correction in
digital communications such as digital terrestrial television and some cable TV systems.

Truth Table for Binary to Gray code converter

Decimal Binary Input Gray Output

Decimal B B B G2 G G
2 1 0 1 0
0 0 0 0 0 0 0

1 0 0 1 0 0 1

2 0 1 0 0 1 1

3 0 1 1 0 1 0

4 1 0 0 1 1 0

5 1 0 1 1 1 1

6 1 1 0 1 0 1

7 1 1 1 1 0 0
Logical Equations:
G = B2B1'B0' + B2B1'B1 + B2B1B0' +
2 B2B1B0
G = B2'B1B0' + B2'B1B0 + B2B1'B0' +
1 B2B1'B0
G = B2'B1'B0 + B2'B1B0' + B2B1'B0 +
0 B2B1B0'

Simplification:
G = B2B1'(B0' + B0) + B2B1(B0' +
2 B0)
= B2B1' + B2B1

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 LABMANUA
= B2(B1' +B1)
= B2

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 LABMANUA

G = B2'B1B0' + B2'B1B0 + B2B1'B0' +

1 B2B1'B0
= B2'B1(B0' + B0) + B2B1'(B0' + B0)
= B2'B1 + B2B1'
= B2 XOR B1
G = B2'B1'B0 + B2'B1B0' + B2B1'B0 +
0 B2B1B0'
= B2'(B1'B0 + B1B0') + B2(B1'B0 + B1B0')
= (B1'B0 + B1B0') (B2' + B2)
= (B1'B0 + B1B0')
= B1 XOR B0

Logic Design:

Gray to
Binary
Code
Conver
ter
Truth
Table
for
Binary
to Gray
code
convert
er

Logic Equations:

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 LABMANUA
Decimal Gray Input Binary Output
Decimal G G G B B B
2 1 0 2 1 0
0 0 0 0 0 0 0
1 0 0 1 0 0 1
2 0 1 0 0 1 1
3 0 1 1 0 1 0
4 1 0 0 1 1 1
5 1 0 1 1 1 0
6 1 1 0 1 0 0
7 1 1 1 1 0 1
B = G2G1G0' + G2G1G0 + G2G1'G0 + G2G1'G0'
2
B = G2'G1G0 + G2'G1G0' + G2G1'G0 + G2G1'G0'
1
B = G2'G1'G0 + G2'G1G0' + G2G1G0 + G2G1'G0'
0
Simplification:
B = G2G1G0' + G2G1G0 + G2G1'G0 + G2G1'G0'
2
= G2G1(G0' + G0) + G2G1'(G0 + G0')
= G2G1 + G2G1'
= G2(G1+G1')
= G2
B = G2'G1(G0 + G0') + G2G1'(G0 + G0')
1
= G2'G1 + G2G1'
= G2 XOR G1
B = G2'G1'G0 + G2'G1G0' + G2G1G0 +
0 G2G1'G0'

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 LABMANUA

= G2'(G1'G0 + G1G0') + G2(G1G0 + G1'G0')

= G2'(G1 XOR G0) + G2(G1 XNOR G0) this is of the form
A’B+AB’
= G2 XOR G1 XOR G0

Logic Diagram:

Preparation:

● Keep a IC pin diagram with you for proper usage of the IC 7486

● Insert IC 7486 in the Bread board slots

● Make connection as per logic diagram

Result: The circuit is tested and verified with the truth table.

Precaution:

● Use Proper power supply both rating and polarity

● Make correct connection on IC for the input and output

● Use diode with proper polarity, anode to + and cathod to ground

● Ensure power supply is switched off while making connection

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 LAB MANUAL

Experiment No: 5

STUDY OF

DECODERS

1.1 Objective 1.2 Apparatus required 1.3 Theory 1.4 Logic circuit 1.5 Observation table 1.6 Procedure
1.7 Precautions 1.8 Result

1.1 OBJECTIVE: - To design and set up the following circuit

1) To design and set up a 3:8 Decoders

1.2 APPARATUS REQUIRED:

S.N Name of Apparatus Range/ Quanti

o. Rating ty
1 DIGITAL TRAINER KIT ……… 5

2 CONNECTING LEAD ……….. ………..

3 IC’S 74138 or 74238 10

4 WIRE CUTTER, POWER As per requirement

SUPPLY
1.3 THEORY:

De-multiplexer circuit can also be realized using a decoder circuit with enable.

In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic
circuit that converts coded inputs into coded outputs, where the input and output codes are
different e.g. n-to-2n , binary-coded decimal decoders. Decoding is necessary in applications
such as data multiplexing, 7 segment display and memory address decoding. The example
decoder circuit would be an AND gate because the output of an AND gate is "High" (1) only
when all its inputs are "High." Such output is called as "active High output". If instead of AND
gate, the NAND gate is connected the output will be "Low" (0) only when all its inputs are
"High". Such output is called as "active low output.
3:8 Decoder

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3:8 IC Diagram

1.6 PROCEDURE:

• Check all the components for their working.

• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.

1.7 Precautions:-

1. Connecting wires should be rubbed with sand papers so that there is no rust.

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 LABMANUA

2. Make sure that the apparatus is switched off while placing ICs and connecting of wires.

3. The connections should be tights.

4. ICs are placed in a proper way in the breadboard. There is no short of current in the in same
inputs

1.8 RESULT: Multiplexer De-multiplexer and decoders are studied and verified.

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 LAB MANUAL

Experiment No: 6

STUDY OF
MULTIPLEXERS

1.1 Objective 1.2 Apparatus required 1.3 Theory 1.4 Logic circuit 1.5 Observation table 1.6 Procedure
1.7 Precautions 1.8 Result

1.1 OBJECTIVE: - To design and set up the following circuit

2) To design and set up a 4:1 Multiplexer (MUX)
3) To design and set up a 8:1 Multiplexer (MUX)

1.2 APPARATUS REQUIRED:

S.N Name of Apparatus Range/ Quanti

o. Rating ty
1 DIGITAL TRAINER KIT ……… 5

2 CONNECTING LEAD ……….. ………..

3 IC’S 74151, 74153, 74238 10

4 WIRE CUTTER, POWER As per requirement

SUPPLY
1.3 THEORY:

Multiplexers are very useful components in digital systems. They transfer a large number of
information units over a smaller number of channels, (usually one channel) under the control of
selection signals. Multiplexer means many to one. A multiplexer is a circuit with many inputs
but only one output. By using control signals (select lines) we can select any input to the
output. Multiplexer is also called as data selector because the output bit depends on the input
n
data bit that is selected. The general multiplexer circuit has 2 input signals, n control/select
signals and 1 output signal.

De-multiplexers perform the opposite function of multiplexers. They transfer a small number of
information units (usually one unit) over a larger number of channels under the control of
selection signals. The general de-multiplexer circuit has 1 input signal, n control/select signals
n
and 2 output signals.

4:1 Multiplexer

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4:1 Multiplexer using Logic Gates

4:1 Multiplexer IC Diagram

8:1 Multiplexers

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8:1 Multiplexer Using Logic Gates:

8:1 Multiplexer IC Diagram

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1.6 PROCEDURE:

• Check all the components for their working.

• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.

1.7 Precautions:-

1. Connecting wires should be rubbed with sand papers so that there is no rust.

3. Make sure that the apparatus is switched off while placing ICs and connecting of wires.

5. The connections should be tights.

6. ICs are placed in a proper way in the breadboard. There is no short of current in the in same
inputs

1.8 RESULT: Multiplexer De-multiplexer and decoders are studied and verified.

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 LAB
MANUAL

Experiment No: 7
STUDY OF FLIP-
FLOPS

1.1 Objective 1.2 Apparatus required 1.3 Theory 1.4 Observation table 1.5 Procedure 1.6 Precautions 1.7
Result.

1.1 Objective: - Verification of state tables

of: 1 . R-S flip-flop
2. J - K flip-flop
3. T Flip-Flop
4. D Flip-Flop
Using NAND and NOT Gate.
1.2 Apparatus: -

S. Name of Apparatus Range/ Quantity

No Rating
.
1 DIGITAL TRAINER KIT ……… 5

2 CONNECTING LEAD ……….. ……

…..
3 IC 7400, IC 7404 10

4 WIRE CUTTER, POWER As per

SUPPLY requirement
1.3 Theory: - In ca se of sequential circuits the effect of all previous inputs on the outputs is represented by
a state of the circuit. Thus, the output of the circuit at any time depends upon its current state and the input
. These also determine the next stat e of the circuits . the relations hip that exists among the inputs,
outputs, present states and next states can be specified by either the state table or the state diagram.
1.4 Observation Table(State Table): - The state table representation of a sequential circuit consists of three
sections labeled present state next state and output . The present state designates the state of flip-flops before
the occurrence of a clock pulse. The next state shows the states of flip-flops after the clock pulse, and output
section lists the value of the output variables during the present value.
Flip-Flop:-The basic one bit digital memory circuit is known as flip-flop. It can store either 0 or
1. Flip-flops are classifieds according to the number of inputs.
R-S Flip-Flop:- The circuit is similar to SR latch except enable signal is replaced by clock pulse.
Logic Diagram

Truth table for S-R flip flop

D Flip-Flop: -The modified clocked SR flip- flop is known as D-flip-flop. From the truth table of SR flip-flop we
see that the output of the SR flip-flop is in unpredictable state when the inputs are same and high. In many
practical applications, these input conditions are not required. These input conditions can be avoided by
making then complement of each other.
Logic Diagram

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 LABMANUA

Truth Table of D Flip-Flop

J-K Flip-Flop:- In a RS flip-flop the input R=S=1 leads to an indeterminate output. The RS flip-flop circuit may be
re-joined if both inputs are 1 than also the outputs are complement of each other.
Logic Diagram

Truth table for J-K flip flop

T Flip-Flop
Logic Diagram

Truth table for T flip flop

Excitation Table of all flip flops

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 LABMANUA

1.5 Procedure:-
1. Connections are made As per circuit diagram .
2. Verify truth-tables for various combinations of input.
1.6 RESULT: - Study and verified truth-tables of various flip-flops.
1.7 Precaution:-
1. All the IC’s should be checked before use the apparatus.
2. All LED’s should be checked.
3. All connections should be tight.
4. Always connect GROUND first and then Vcc
5. The circuit should be off before change the connections .
After completing the experiment switch off the supply to apparatus .

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 LAB
MANUAL

Experiment
No: 8 STUDY
OF ALU

1.1 Objective 1.2 Apparatus required 1.3 Theory 1.4 Observation table 1.5 Procedure 1.6 Precautions 1.7
Result.

1.1 Objective: - Verification and study of ALU.

1.2 Apparatus: -

S. Name of Apparatus Range/ Quantity

No Rating
.
1 DIGITAL TRAINER KIT ……… 5

2 CONNECTING LEAD ……….. ……

…..
3 IC 7400, IC 7404 10

4 WIRE CUTTER, POWER As per

SUPPLY requirement
1.3 Theory: - An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and
logic operations. It represents the fundamental building block of the central processing
unit (CPU) of a computer. Modern CPUs contain very powerful and complex ALUs.
4-bit Arithmetic Logic Unit (ALU) performs all the possible 16 logic operations on two
variables and a variety of arithmetic operations. An arithmetic logic unit (ALU) is at the
heart of a modern microprocessor, and the adder cell is the elementary unit of an ALU.
8 Bit ALU design is a combinational circuit which adds two binary numbers of 8 bit lengths.

Block Diagram

Truth table:

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 LAB MANUAL

1.5 Procedure:-
1. Connections are made as per circuit diagram.
2. Verify truth-tables for various combinations of input.
1.6 RESULT: - Study and verified truth-tables of 4 bit ALU.
1.7 Precaution:-
1. All the IC’s should be checked before use the apparatus.
2. All LED’s should be checked.
3. All connections should be tight.
4. Always connect GROUND first and then Vcc.
5. The circuit should be off before change the connections.
6. After completing the experiment switch off the supply to apparatus.

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