1 2 3 4 5 6 7 8

J1
1
+IN
2
-IN

A
Modified HPM7177-ADC-Board: A

-4 PCB-Layers instead of 6 if it doesnt impact EMI-susceptibility

Sheet: Input Section
-uses 3x Resistor Networks a 8 Rs each like TDP1603, TOMC, NOMC instead of 2 Vishay PRND-networks
-different LVDT-Drivers/Receivers were used due to component shortage
-different toplayer-shield
-added thermal jumpers (optionable)

Changes were made to:

File: Input Section.sch

Sheet: Voltage Reference -eliminate waiting time and cost for super special resistor networks "Vishay PRND"
-fit the PCBs in special rf aluminium cases that i got at low cost
-reduce costs if reasonable/specs arent degraded
B B

Lets hope the TDP1603 and 4 Layer PCB wont degrade the HPM7177-specs...
File: Voltage Reference.sch

Sheet: ADC
Why were the LTZ-> 5V divider and the frontend-divider used in the shown configuration?:

Limited by the max pos Ref-voltage range of the AD7177-2 (AVDD +0.3V, 5V-rail would need to be more like 5.5V)
the LTZ->5V divider is calculated to produce maximum 5.4V at assumed maximum 7.2V LTZ-raw voltage
7.2V / (333R + 1000R) * 1000R = 5.4V
File: ADC.sch
7 Resistors of the 8 available in the resistor network are used
Sheet: Connectors and Decoupling The ADC should be able to measure +-10V with no problems, 120% overrange like on a standard
DVM would be nice. With two resistor networks a 8 resistors the shown configuration gives
C C
a suitable overrange, in this case the combination 20k/5k give approximately +-10.3V...+-10.8V
input range depending on exact raw LTZ-voltage.

File: Connectors and Decoupling.sch

One could also use 30K/5k in the frontend giving 150% overrange, but then the supply voltages
would need to be changed as well as the Fullscale-Ref-provider ("10V Ref"), to allow for the OPs
and the analog switches to work with the +-15V input range.
OR
Use 3 resistor networks a 8 resistors to get a 120% overrange, but each additional network
degrades the TC-matching and drift-specs of the frontend.

Sheet: Input Section High Impedance with JFET-OP

D D

File: Input Section High Impedance with JFET-OP.sch

Sheet: Input Section High Impedance with 34401A-Frontend

E E
File: Input Section High Impedance with 34401A-Frontend.sch

Sheet: Input JFET Bootstrappped Protected

File: Input JFET Bootstrappped Protected.sch

Sheet: /
File: Resistance_Bridge.sch
Title:
Size: A3 Date: Rev:
KiCad E.D.A. kicad (5.1.6)-1 Id: 1/8
F F
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

G = 0.5 Vcm = 2.5V

Input Voltage Range
A A

+15V

7
U5 RN1A RN1C RN2A 10k
U3 2
ADG1408YRUZ

V+
- 10k 10k R22
ADG1419BRMZ 1 16
6
1 16 3 14

GND GND
2 4 8 3
SA S1 OUT +

V-
U7 3 14 1
1 5 RN2C 10k
D S2 OPA189IDGK

4
8 6
SB S3 C8
6 IN_CPL VCM 7
IN IN_CPL VCM S4
REF_10V 12 -15V
REF_10V S5
3 4 REF_5V 11 100p +7.5V
GND VDD +15V REF_5V S6
5 7 REF_7V 10 +5V
NC VSS -15V REF_7V S7
REF_GND 9
REF_GND S8

5
4

V+
7
1 of 8 Decoder - R24
GND 2 1

V+
A0_P 1 RN1E RN1G -
A0_P A0 6 3
10k 10k +

V-
A1_P 16 +15V 1
A1_P A1 3 U11
+

V-
A2_P 15 U9

2
B A2_P A2 5 12 7 10 AD8065ART-R2 B
2 OPA388IDGK

4
+2V5 EN 13
R4 R6 VDD C6

12

10
14 3
+IN GND VSS 100p RN2E RN2G
499 499 GND 10k 10k GND GND
R1

7
10M 2x10µH GND -15V
1 4
GND

C2 C3
47n 47n 2 3
R16
AIN+

1
R2 1
FL1 CM-adjust RV1 2
10M
R5 R7 10
R17

3
-IN C10
1
499 499 10n NP0

+15V

VCM
AIN-

7
U6 RN1B RN1D RN2B 10k
U4 2
ADG1408YRUZ

V+
- 10k 10k R23
ADG1419BRMZ 2 15
6
2 15 4 13

GND GND
C 2
SA
4
S1 OUT
8 3
+
C

V-
U8 4 13 1
1 5
D S2 OPA189IDGK RN2D 10k

4
8 6
SB S3 C9
6 IN_CPL VCM 7
IN IN_CPL VCM S4
REF_10V 12 -15V
REF_10V S5
3 4 REF_5V 11 100p +7.5V
GND VDD +15V REF_5V S6
5 7 REF_7V 10 +5V
NC VSS -15V REF_7V S7
REF_GND 9
REF_GND S8

5
4

V+
7
1 of 8 Decoder - R25
GND 2 1

V+
A0_N 1 RN1F RN1H -
A0_N A0 6 3
10k 10k +

V-
A1_N 16 +15V 1
A1_N A1 3 U12
+

V-
A2_N 15 U10

2
A2_N A2 6 11 8 9 AD8065ART-R2
2 OPA388IDGK

4
+2V5 EN 13
VDD C7

8
14 3 RN2F RN2H
GND VSS 100p
GND 10k 10k GND GND

11

9
GND -15V

D R18 D

1
1
RV2 2
CM-adjust 10
R19

3
1

VCM
Voltage Range of the various used ICs:

ADG1419BRMZ +-25Vmax, +-15V nominal

ADG1408YRUZ +-25Vmax, +-15V nominal
OPA189IDGK +-20Vmax, +-15V nominal
OPA388IDGK +6V/+-3Vmax
AD8065ART-R2 +26Vmax
ADA4522-1ARMZ +60Vmax, +55V / +-27.5V nominal
Common-mode bias: +2.5V from ADC internal Vref OPA2277U +36Vmax/+-18Vmax

R8

E E
1k

+5V
+5V C4
10n NP0
5

+2.5V
4
V+
7

- R9
2 1
V+

+2.5V from ADC - Vcm

6 3
+
V-

R3 10
3 U2
VCM_REFOUT +
V-

U1
2

AD8065ART-R2
100 OPA388IDGK
4

C1 C5
1µ 1µ

Sheet: /Input Section/

GND GND GND GND
File: Input Section.sch
Title:
Size: A3 Date: Rev:
KiCad E.D.A. kicad (5.1.6)-1 Id: 2/8
F F
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

A A

S102K need to be mounted sideways, due to case height limit!

+15V

LTZ 6.9...7.2V / 0.74 10V Ref Network

5.17V...5.40V Dissipation: 12.5mW

1
Missing Interdigitation
R35 3 One Resistor unused
100k Q2
B Dissipation: 22mWmax B
MMBF4392

2
R42
100
R26 D3
10 1N4148
REF_7V
R27
REF_5V
10 C15 RN6E RN6F RN6G RN6H
47n NP0
D2 R32 R34 R36 R37 5 12 6 11 7 10 8 9
1N4148 12k 70k 70k 0R1
1k 1k 1k 1k
S102K S102K S102K
+15V +15V
+15V C17
RN5A

16

15

10
100p NP0

5
R40
3 333R RN5B 4

V+

V+
7
+ - R47
1k 1 2 1

V+
1

7
R41 RN5G - REF_10V
2 6 3
- +

V-

V-
1k 1k 1k 100
1k U14A
1

3
3
+

V-
U13 U15

14
4

2
C OPA2277 C
ADA4522-1ARMZ AD8065ART-R2

16

4
RN5C C16 RN6A
-15V

3
1k
100p NP0

15 1
C14 1k
U16A
LTZ1000
47n NP0 RN6B

13

9
GND GND GND
1k
RN5D 1k 1k RN5H

14 2
GND

11 4

12 8
1k
U14B RN6C
U16B 1k
2

4
OPA2277 LTZ1000 1k 1k RN5E
RN5F

13 3
3

5
R28 +
Q1 7 RN6D
1 R30 R31
MMBT3904 6 1k
1k - R38

4
2

R29 S102K 120

1k 1k
GND_Sense
C12 R33 C13
D1
330k 47n NP0 1k 47n NP0 R39
1N4148
C11 S102K 0R1

D D
47n NP0
GND GND GND GND GND REF_GND

E E

Sheet: /Voltage Reference/

File: Voltage Reference.sch
Title:
Size: A3 Date: Rev:
KiCad E.D.A. kicad (5.1.6)-1 Id: 3/8
F F
1 2 3 4 5 6 7 8
 1 2 3 4 5 6

A A

+2V5

R50 R52 +2V5

10k 10k
U20 X1
R48 AD7177-2 16MHz
21 9 4 FB1
1k AIN+ AIN0 XTAL1 VDD
22 10 3
AIN- AIN1 XTAL2/CLKIO OUT

GND
+7.5V 23 1
GND AIN2 14 EN
+7.5V 24 CS CS C33 C34 C35
C18 GND AIN3 13
SCLK SCK 100n 10µ 100n

2
1
10n NP0 VCM AIN4 12
5

DIN DIN
4 11
V+
7

- R49 DOUT/RDY DOUT

B 2 1 3 15 GND GND GND GND B
V+

- REF+ SYNC/ERR SYNC

6 3 2
+ REF-
V-

10 R51
3 U19 4 19
VREF+ + VCM_REFOUT REFOUT GPIO0 GND SCK_FB
V-

U18
2

AD8065ART-R2 20
OPA388IDGK GPIO1 GND 10
4

C19 C20 5 18 to connectors

REGCAPA REGCAPD
47n 47n
C24 C26 C27 C29
1µ 100n 100n 1µ

+5V
GND GND GND GND
GND GND GND GND GND
C21 2.2µ +2V5
3 1 7
AVDD1
C30
2 C22 2.2µ 2.2µ
3 1 8 16 1 3
AVDD2 IOVDD
6 17
AVSS DGND
C23 C25 C28 C31 C32
2

2
100n 100n 100n 100n 10µ

GND GND GND GND GND GND GND GND GND GND
C C

Sheet: /ADC/
D File: ADC.sch D

Title:
Size: A4 Date: Rev:
KiCad E.D.A. kicad (5.1.6)-1 Id: 4/8
1 2 3 4 5 6
 1 2 3 4 5 6 7 8

U21
SN65LVDT2DBV +15V
C56
22n
3 CS_DIFF_P 3 1
5
CS D
C64

2
4 CS_DIFF_N
100n
A A
2 1 +2V5
GND VCC
C38 GND GND
FB4
100n -15V
C57
22n
GND U22 GND
3 1
SN65LVDT2DBV
C65

2
3 SCK_DIFF_P 100n
5
SCK D
4 SCP_DIFF_N GND GND
+5V
2 1 +2V5 C58
GND VCC
C39 22n
FB5 3 1
100n

C66

2
GND U23 GND 100n
SN65LVDT2DBV

GND GND
B 3 DIN_DIFF_P +7.5V B
5 C59
DIN D 22n
4 DIN_DIFF_N
3 1
2 1 +2V5
GND VCC
C67

2
C40
FB6 100n
100n
1
GND GND
GND GND 2
-2V5
3 C60
U24 4 22n
SN65LVDT2DBV
5 3 1
6
C68

2
3 SYNC_DIFF_P 7
5 8 100n
SYNC D
4 SYNC_DIFF_N 9
10 GND GND
2 1 +2V5 J3
GND VCC 11 +2V5
Conn_01x20
C41 12 C61
FB7
100n 13 22n
C 3 1 C
IN_CPL 14
GND GND 15
C69

2
16 100n
17
FB15 FB16 FB17 FB18 FB19 FB20
18
GND GND
19
U25 20
1
SN65LVDS1DBVT
2
GND
3
4 DOUT_DIFF_P 4
OUT+ FB8 GND
5 5
DOUT IN D IN_CPL
3 DOUT_DIFF_N 6
OUT- GND
FB9 7
+2V5 1 2
VDD GND A0_P 8
GND
C36 9
FB2 FB10
100n 10
A1_P GND J4
11
Conn_01x20
GND GND FB11 12
GND
A2_P 13
U26
D 14 D
SN65LVDS1DBVT FB12
15
A0_N
16
4 SCK_FB_DIFF_P
OUT+ FB13 17
5
SCK_FB IN D A1_N 18
3 SCK_FB_DIFF_N
OUT- 19
FB14
+2V5 1 2 20
VDD GND A2_N
TH1
C37
FB3

8
7
6
5

8
7
6
5
100n
RN3 RN4
C72 C74 C76 C78 C80 C82
PT1000 10k 10k
GND GND 100n 100n 100n 100n 100n 100n

1
2
3
4

1
2
3
4
GND GND GND GND GND GND
GND

+15V -15V +5V +7.5V +5V -2V5

E E

C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C62 C63 C70 C71 C73 C75 C77 C79 C81 C83 C84 C85
100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n

GND GND GND GND GND GND

J2 Sheet: /Connectors and Decoupling/

H1 H2 H3 H4 H5 H6 H7
Shield

RF_Shield_One_Piece
File: Connectors and Decoupling.sch
Title:
1

Size: A3 Date: Rev:

GND KiCad E.D.A. kicad (5.1.6)-1 Id: 5/8
GND
F F
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

R? G = 0.5 Vcm = 2.5V

Input Voltage Range
TBD
A A
+15V
+15V C?
TBD

7
RN?A RN?C RN?A 10k
2

V+
5
U? - R? 10k 10k R?
U? 4 6 1 16
ADG1408YRUZ

V+
ADG1419BRMZ -
1 3 1 16 3 14
+

V-
U? TBD 3 14 1

GND GND
2 4 8 3 RN?C 10k
SA S1 OUT +

V-
U? OPA189IDGK

4
1 5
D S2 OPA140AIDBVR C?

2
8 6
SB S3
6 IN_CPL VCM 7 -15V
IN IN_CPL VCM S4
REF_10V 12 -15V 100p +7.5V
REF_10V S5
3 4 REF_5V 11 +5V
GND VDD +15V REF_5V S6
5 7 REF_7V 10
NC VSS -15V REF_7V S7

5
REF_GND 9
REF_GND S8 4

V+
7
- R?
2 1

V+
1 of 8 Decoder RN?E RN?G -
GND 10k 10k 6 3
+

V-
A0_P 1 1
A0_P A0 3 U?
+

V-
A1_P 16 +15V U?

2
A1_P A1 5 12 7 10 AD8065ART-R2
A2_P 15 OPA388IDGK

4
B A2_P A2 B
R? R? C?

12

10
+2V5 2
EN 13
+IN VDD 100p RN?E RN?G
14 3
499 499 GND VSS GND 10k 10k GND GND
R?

7
10G 2x10µH
1 4
GND -15V
GND

C? C?
47n 47n 2 3
R?
AIN+

1
R? 1
FL? CM-adjust RV? 2
10G
R? R? R? 10
R?

3
-IN C?
1
499 499 TBD 10n NP0

+15V

VCM
+15V C?
AIN-
TBD

7
RN?B RN?D RN?B 10k
2

V+
5
U? - R? 10k 10k R?
U? 4 6 2 15
ADG1408YRUZ

V+
ADG1419BRMZ -
1 3 2 15 4 13
+

V-
U? TBD 4 13 1

GND GND
C 2
SA
4
S1 OUT
8 3
+
C

V-
U? OPA189IDGK RN?D 10k

4
1 5
D S2 OPA140AIDBVR C?

2
8 6
SB S3
6 IN_CPL VCM 7 -15V
IN IN_CPL VCM S4
REF_10V 12 -15V 100p +7.5V
REF_10V S5
3 4 REF_5V 11 +5V
GND VDD +15V REF_5V S6
5 7 REF_7V 10
NC VSS -15V REF_7V S7

5
REF_GND 9
REF_GND S8 4

V+
7
- R?
2 1

V+
1 of 8 Decoder RN?F RN?H -
GND 10k 10k 6 3
+

V-
A0_N 1 1
A0_N A0 3 U?
+

V-
A1_N 16 +15V U?

2
A1_N A1 6 11 8 9 AD8065ART-R2
A2_N 15 OPA388IDGK

4
A2_N A2
2 C?

8
+2V5 EN 13
VDD 100p RN?F RN?H
14 3 10k 10k
GND VSS GND GND GND

11

9
GND -15V
R?

1
D 1 D
RV? 2
CM-adjust 10
R?

3
1

VCM
Modifications:

HP 34401A-JFET-Frontend, Single Ended

Common-mode bias: +2.5V from ADC internal Vref
10G-input resistors instead of 10M as bias current path

-10V Ref for negative full scale calibration (missing on unipolar HPM7177)

As Muxes there are also alternatives:

R?
2x MUX36S08 with lower leakage or
many solid state switches like AQW210S or similar
E 1k E
In my opinion the temp stabilization and the auto-zero/fullscale makes a
+5V discrete JFET-frontend unnecessary.
+5V C?
10n NP0
5

+2.5V
4
V+
7

- R?
2 1
V+

+2.5V from ADC - Vcm

6 3
+
V-

R? 10
3 U?
VCM_REFOUT +
V-

U?
2

AD8065ART-R2
100 OPA388IDGK
4

C? C?
1µ 1µ

Sheet: /Input Section High Impedance with JFET-OP/

GND GND GND GND File: Input Section High Impedance with JFET-OP.sch
Title:
Size: A3 Date: Rev:
KiCad E.D.A. kicad (5.1.6)-1 Id: 6/8
F F
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

+18V
G = 0.5 Vcm = 2.5V

5
Input Voltage Range

1
4

V+
-
A 1 A
Q? 2 3 +15V
+

V-
U?

7
U? RN?A RN?C RN?A 10k
U? 2
ADG1408YRUZ

V+
- 10k 10k R?
ADG1419BRMZ 1 16

1
6
1 16 3 14

GND
2 4 8 3
SA S1 OUT +

V-
2 Q? Q? 2 U? 3 14 1
1 5 RN?C 10k
D S2 OPA189IDGK

4
3

3
8 6 U?
SB REF_-10V S3 3 C?

V-
6 IN_CPL VCM 7 +
IN IN_CPL VCM S4 1
REF_10V 12 -15V
REF_10V S5 4

V+
3 4 REF_5V 11 - 100p +7.5V
GND VDD +15V REF_5V S6
5 7 REF_7V 10 +5V

5
NC VSS -15V REF_7V S7
REF_GND 9
REF_GND S8

5
4

V+
7
1 of 8 Decoder - R?

2
GND 2 1

V+
A0_P 1 RN?E RN?G -
A0_P A0 Q? Q? 6 3
1 1 10k 10k +

V-
A1_P 16 +15V 1
A1_P A1 3 U?
+

V-
U?

3
A2_P 15

2
A2_P A2 5 12 7 10 AD8065ART-R2
2 OPA388IDGK

4
B +2V5 EN 13 Q? Q? B
R? R? VDD 1 1 C?

12

10
14 3
+IN GND VSS 100p RN?E RN?G

3
499 499 R? R? GND 10k 10k GND GND
R?

7
10G 2x10µH GND -15V
1 4
GND

C? C?

5
47n 47n 2 3 4 4

V+

V+
- - R?
1 1 AIN+

1
R? 1
FL? 3 R? R? 3 CM-adjust RV? 2
+ +

V-

V-
10G
R? R? U? U? 10
GND R?

3
-IN C?
1
499 499 10n NP0

+15V

VCM
R? R?
AIN-

7
RN?B RN?D RN?B 10k
2

V+
- 10k 10k R?
6 2 15

5
R?
4 3 2 15 4 13

V+
+10V_Ref - +

V-
U? 4 13 1
C 1 C
OPA189IDGK RN?D 10k

4
3
+

V-
C?
U? GND

2
-15V
GND 100p +7.5V
+5V

5
4

V+
7
- R?
2 1

V+
RN?F RN?H -
10k 10k 6 3
+

V-
1
3 U?
+

V-
U?

2
6 11 8 9 AD8065ART-R2
OPA388IDGK

4
C?

8
100p RN?F RN?H
GND 10k 10k GND GND

11

9
R?

1
D 1 D
RV? 2
CM-adjust 10
R?

3
1

VCM
Modifications:

HP 34401A-JFET-Frontend, Single Ended

Common-mode bias: +2.5V from ADC internal Vref
10G-input resistors instead of 10M as bias current path

-10V Ref for negative full scale calibration (missing on unipolar HPM7177)

As Muxes there are also alternatives:

R?
2x MUX36S08 with lower leakage or
many solid state switches like AQW210S or similar
E 1k E
In my opinion the temp stabilization and the auto-zero/fullscale makes a
+5V discrete JFET-frontend unnecessary.
+5V C?
10n NP0
5

+2.5V
4
V+
7

- R?
2 1
V+

+2.5V from ADC - Vcm

6 3
+
V-

R? 10
3 U?
VCM_REFOUT +
V-

U?
2

AD8065ART-R2
100 OPA388IDGK
4

C? C?
1µ 1µ

Sheet: /Input Section High Impedance with 34401A-Frontend/

GND GND GND GND File: Input Section High Impedance with 34401A-Frontend.sch
Title:
Size: A3 Date: Rev:
KiCad E.D.A. kicad (5.1.6)-1 Id: 7/8
F F
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8 9 10 11

OPA140 = Low Bias current, good Voltage/Current-noise, etc.

needs CMRR/AVOL-boost
-15V -bootstrapping improves CMRR
A -adding AD8065 improves open loop gain and therefore closed loop INL A
-AD8065 is necessarily faster than OPA140, but handles only +-24V
-gain/phase-compensation not included in the schematic

2
OPA140AIDBVR
3 -see "Bootstrapping your op amp yields wide voltage swings, Figure 8" for

V-
+ U? bootstrapping circuit or Linear Appnote 67 page 58
1
4

V+
- +15V

5
+15V

+13V
R?

2
28k
R? R? Q? G = 0.5 Vcm = 2.5V
TBD 1 Input Voltage Range
TBD TBD

3
Q?

3
TBD U?
2 1 U? TMUX6119 D?
TMUX6119 TBD
7
SA
7 6 C?

5
10k is enough for basic protection SA D R? R? RN?A RN?C RN?A 10k
together with the low leakage JFETS 6 5 4 100p

V+
5
D SB U? - 10k TBD 10k 10k R?

3
1 1 16
Q? 5 EN MUX36S08 4 1

V+
SB 1 8 -
B TBD EN SEL 1 3 1 16 3 14 B
+15V +

V-
2 1 8 R? R? 3 14 1
+15V SEL PRECHARGE_P 4 8 3
S1 OUT + 10k RN?C 10k

V-
U? U?

2
2 5
VDD S2 499 OPA140AIDBVR AD8065ART-R2 C?

2
GND
2 3 6 D?
VDD GND GND S3
TBD

GND
-13V
3 4 REF_7V 7
GND VSS REF_7V S4
4 U? 12 C? 100p +7.5V
VSS R? 1k S5
47n

2
MUX36S08 11 +5V
-15V S6
+-16.5V 10 Q?
-15V S7

5
6.4pF On-C VCM 4 8 9 TBD 1
0.5pA Leakage VCM S1 OUT S8 R? 4

V+
7
- R?

3
REF_10V 5 28k
0.2pC REF_10V S2 2 1

V+
REF_5V 6 1 of 8 Decoder GND RN?E RN?G -
120R RDSon REF_5V S3 6 3
10k 10k +

V-
68ns switch time REF_GND 7 1 1
REF_GND S4 A0 3 U?
+

V-
12 16 U?

2
GND S5 A1 5 12 7 10 AD8065ART-R2
+15V OPA388IDGK
REF_7V 11 15

4
REF_7V S6 A2 -15V C?

12

10
10 +2V5 2
R? 1k S7 EN 13
9 VDD 100p RN?E RN?G
S8 14 3
GND VSS GND 10k 10k GND GND

7
L? 1 of 8 Decoder
68µ R? R? 1 -15V
A0 GND
+IN_0 16
C A1 +15V C
5k 5k 15
A2 R?
1

R? 2

1
U? +2V5 EN 13 1
THJP 2x10µH VDD CM-adjust RV? 2
GDT 1 4 14 3
GND U? VSS 10
R?
GND

C? C? C? C?

3
GND
47p 47p MUX36S08 1
2 3
4.7n 4.7n 14 3
R? GND VSS
D? R? FL? 13 -15V
THJP VDD

VCM
150V 1M +2V5 2
EN
R? R? 15 AIN+
A2
-IN_0 16 +15V C?
A1
5k 5k 1 GND 10n NP0
A0 -15V AIN-
1 of 8 Decoder +15V
14 3
9 GND VSS
S8 13
10 2 VDD
S7 EN
11 15
S6 A2
12 16 +15V R?
S5 A1

2
REF_GND 7 1 28k
REF_GND S4 A0 Q?
REF_5V 6 TBD 1
REF_5V S3
REF_10V 5 1 of 8 Decoder
D REF_10V S2 D

3
VCM 4 8 9
VCM S1 OUT S8
10 D?
S7
11 TBD
1k S6
12 C?
+13V

5
R? S5 R? R? RN?B RN?D RN?B 10k
REF_7V 7 4 100p

V+
5
REF_7V S4 - 10k TBD 10k 10k R?
6 4 1 2 15

V+
GND S3 -
5 1 3 2 15 4 13
S2 +

V-
R? R? 1
3

Q? PRECHARGE_N 4 8 3 4 13
S1 OUT + 10k

V-
U? U? RN?D 10k

2
TBD U?
TMUX6119 499 OPA140AIDBVR AD8065ART-R2 C?

2
2 1 U? D?
TMUX6119 MUX36S08 TBD
7
SA U?
7 6 C? 100p +7.5V
SA D
47n

2
6 5 +5V
D SB
3

1
Q? 5 EN Q?
SB 1 8

5
TBD EN SEL TBD 1
+15V R?
8 4

V+
7
2 1 SEL - R?

3
+15V 28k 2 1

V+
2 GND RN?F RN?H -
VDD 6 3
10k 10k
GND

V-
2 3 1
VDD GND 3 U?
GND

V-
U?
-13V

3 4

2
GND VSS 6 11 8 9 AD8065ART-R2
E 4 OPA388IDGK E

4
VSS TBD -15V
TBD C?

8
-15V R?
R? 100p RN?F RN?H
-15V 10k 10k
GND GND GND

11

9
+15V
R?

1
1
5

RV? 2
4 CM-adjust
V+

- 10
1 R?

3
3 Modifications on this page: 1
+
V-

U?
OPA140AIDBVR -back again to just one input to make it simple
2

-TMUX6119 instead of SSRs like AQW210S: the AQWs take 200µs/500µs turn on/off time

VCM
and have higher capacitive coupling 50-8pF depending on applied signal voltage
-15V -protection jfets limiting at +-13V, protected by input resistors
-so far no switch off-overvoltage protection, i dont plan on applying more than 15V to it so far
-first MUX shunts high frequency content to ground during selfcal-routine
-precharge this time hopefully better
-leakage protected traces, later necessary, this time just for the looks :)
-negative side without protected traces so far
F F

VCC

G G

A
R?
Common-mode bias: +2.5V from ADC internal Vref 28k
U?B
LM393 R?
Chan_0 TBD

3
28k
Q?
1

5
+
7 U?B
R? Q? 1 2
R? 3 LM393
6
_ TBD
2

2 1 5
TBD +
1k 7
Q?

3
+15V

3
Q? 6
+5V GND R? TBD _
D? TBD
+5V
8

C? TBD 2 1
R? TBD
V+
VCC

10n NP0

3
5

+2.5V 28k U?C Q?

4
V+
7

- R? LM393 TBD

B
V-

2 1
V+

- Vcm 1 2
2

+2.5V from ADC R?

6 3 D?
4

+ 28k U?A
V-

R? 10 Q? Q? R?
3 U? +13V -13V TBD LM393
VCM_REFOUT + 1 TBD 1 TBD 28k
V-

U? U?A
2

8
AD8065ART-R2
100 OPA388IDGK
3

H LM393 R? 3 H

V+
4

GND R? R? VI VI +
C? C? R? 28k 1 U?C
A B
1

1µ 1µ 2 LM393
- 2
REG29 -

V-
TBD 499 1
TBD 3 Q? Sheet: /Input JFET Bootstrappped Protected/
3

4
+ TBD File: Input JFET Bootstrappped Protected.sch
2

GND GND GND GND

Title:
GND Size: A2 Date: Rev:
KiCad E.D.A. kicad (5.1.6)-1 Id: 8/8
1 2 3 4 5 6 7 8 9 10 11