Xilinx Based Real Time Clock

PROJECT REPORT

SUBMITTED BY

Nishtha (22001015042)

Muskan (22001015038)

Electronics and Computer Engineering Under the supervision of

DR. Nitin Sachdeva

Department of Electronics Engineering

Faculty of Engineering and Technology

J.C Bose University of Science and Technology,YMCA,Faridabad

 CONTENTS

• Candidate’s Declaration

• Certificate

• Introduction

• Technology used
1. Software Requirements

2. Introduction to Technologies Used

• Screenshots
1. Initiating the project

2. Home webpage

3. Open file

• References
 DECLARATION

We hereby certify that the work which is being presented in this project report
entitled “Xilinx Based Real Time Project”, in partial fulfilment of requirements for
the 4th semester of degree of BACHELOR OF TECHNOLOGY in Electronics And
Computer Engineering, submitted to the Department of electronics Engineering,
Faculty of Engineering and Technology, J.C. Bose University of Science and
Technology, YMCA, Faridabad, Haryana-121006 is an authentic record of our work
carried out during period from January 2024 to June 2024 under the supervision
of Dr. Nitin Sachdeva. The content presented in this project report, we have
not submitted to any other University/Institute for the award of B.Tech. or any
degree or diploma.

Nishtha
22001015042

Muskan
22001015038
 CERTIFICATE

This is to certify that the project entitled “Xilinx Based Real Time Clock”,
submitted to Department of Electronics And Computer Engineering, Faculty of
Engineering and Technology, J.C. Bose University of Science and Technology,
YMCA, Faridabad, Haryana-121006 in partial fulfillment of the requirement for
the 4th semester of degree of BACHELOR OF TECHNOLOGY in Electronics And
Computer Engineering, is a bonafide work carried out by them under my
supervision and guidance. This project work comprises of original work and has
not been submitted anywhere else for any other degree to the best of my
knowledge.

Dr. Nitin Sachdeva

Department of Electronics Engineering

J.C.Bose University of Science and Technology
YMCA, Faridabad
ABSTRACT

This project designs a simple system that can include electronic real time clock
based on FPGA (Field Programmable Gate Array) and VHDL (Very-High-Speed
Integrated Circuit Hardware Description Language). The first chapter briefly
introduces the research background. The second chapter introduces the
theoretical basis of digital circuits and the hardware and software platform
used in this paper. In the third chapter, the design of each submodule of the
system and the overall design of the system are carried out. This chapter is the
core chapter of this article, which describes the functions of the module and
explains the input and output ports. In this chapter, a core point of digital
circuit design is reflected: combining modules that realize simple functions into
modules that can realize complex functions. And integrate sub-modules that
realize similar functions into a top-level module. The fourth chapter is the logic
synthesis of the circuit. The fourth chapter shows the simulation of the core
module function and the simulation of the system output. The conclusion
section summarizes the interesting parts of the design of this paper.

Keywords : HDL,XILINX,RTC ,FPGA.

INTRODUCTION

Since FPGAs(Field Programmable Gate Array) first appeared, their flexibility has
been widely favoured by developers. FPGA is now widely used as a chip
verification tool to test the logic function and reliability of the chip. As the
simplest entry-level tool for digital circuits, this paper uses FPGA as the
hardware platform and Vivado as the software platform to design a simple
system that integrates electronic stopwatch and electronic clock functions.

The second chapter introduces the theoretical basis needed for this paper.
Binary signals are generally used in digital circuits, and each digit has only two
values of 0 and 1, so as long as the circuit can correctly distinguish two
different states, a certain deviation is allowed. For the specific functions
realized, the design of the system sub-modules is completed and the functions
and ports to be realized by the sub-modules are explained in detail.

The innovative design of some modules can save hardware overhead.

Specifically, it is to achieve as many functions as possible with as few modules
as possible. Then, the fourth chapter conducts a simple simulation of the
important modules and the functions of the system. The correctness of the
functions of the sub-modules and the correctness of the interconnection of the
sub-modules of the system are verified. Finally, the highlights and design
deficiencies of this paper are summarized.
Working of Real Time Clock

In the clock mode, the frequency divider divides the frequency of the system
clock signal to obtain signals of different frequencies for use by each module.
The 1Hz signal is sent to the counter as a counting signal, and the 1kHz signal is
sent to the scanning display module for dynamic display by the digital tube.

The counter completes the counting of hours, minutes, and seconds and has
the correct carry logic relationship, and the output is the BCD code of hours,
minutes, and seconds. The output data selector will select the data from the
counter, and will send different data to the display module in different modes.

When the frequency is high, the human eye cannot tell whether the digital
tubes are lit at the same time or sequentially.
In the setting mode, the pulse signal input by the button will be debounced
and sent directly to the counter as a count, indicating that it counts once. At
this moment, the 1Hz counting signal of the frequency divider should be set
inactive. The set time will be saved to the storage module.
When the real time clock is turned on, the current time and the time saved by
the storage module will be judged.

If stored multiple times, the previously stored data will be overwritten. This
function of the memory is performed by a shift register. The storage signal
pulse is sent to the memory module as a storage enable signal.
Both the data of the memory and the data of the counter will be sent to the
output data selection module. Under different working conditions, the module
will select different data for display.
Flowchart for implementation of RTC

Fig 1: Flow Chart of Proposed RTC

 Description of Signals used in implementation

S no. SIGNAL SIGNAL INPUT DESCRIPTION

1 clk input Default clock is applied
as input to the system.
2 reset input It is active high signal
which when enable
then the reset process
begins
3 seconds output This shows the value of
current seconds
4 minutes output This shows the value of
current minutes
5 hours output This shows the value of
current hours
VHDL Code for RTC

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RealTimeClock is
Port (
clk : in STD_LOGIC; -- System clock input
reset : in STD_LOGIC; -- Reset signal input
seconds : out INTEGER range 0 to 59; -- Output for seconds (0-59)
minutes : out INTEGER range 0 to 59; -- Output for minutes (0-59)
hours : out INTEGER range 0 to 23 -- Output for hours (0-23)
);
end RealTimeClock;
architecture Behavioral of RealTimeClock is
signal counter : INTEGER range 0 to 999999; -- Counter for clock ticks
signal sec_reg, min_reg, hour_reg : INTEGER range 0 to 59; -- Registers
begin
process(clk, reset)
begin
if reset = '1' then
counter <= 0;
sec_reg <= 0;
min_reg <= 0;
hour_reg <= 0;
 elsif rising_edge(clk) then
if counter = 1000000 then
counter <= 0;
sec_reg <= sec_reg + 1;
if sec_reg = 60 then
sec_reg <= 0;
min_reg <= min_reg + 1;
if min_reg = 60 then
min_reg <= 0;
hour_reg <= hour_reg + 1;
if hour_reg = 24 then
hour_reg <= 0;
end if;
end if;
end if;
else
counter <= counter + 1;
end if;
end if;
end process;
-- Output signals
seconds <= sec_reg;
minutes <= min_reg;
hours <= hour_reg;
end Behavioral;
Model Simulation

RTL Schematic
CONCLUSION

In this paper, the FPGA development board is used as the hardware platform,
and the Xilinx software is used as the software platform. A simple system that
can simultaneously run an electronic stopwatch and an electronic clock is built.
Its functions are often used in daily life. There are two biggest innovations in
this paper. The first is that when setting the clock, the state of the counter can
be directly changed through the key pulse. This greatly saves hardware
overhead. At the same time, a key technical problem of the setting of addition
and subtraction is solved. The same pulse will be sent to the counter as the
addition and subtraction judgment signal and counting clock signal. There
needs to be a small delay between these two signals. That is, the remaining
judgment signals should be prepared in advance before the rising edge of the
clock arrives. The second is to design an audio signal as the driver of the
buzzer. Because the system crystal oscillator can only generate square wave
signals but not sine wave signals. So, we can only produce a "not perfect"
audio. So far, the boring FPGA has been played with new tricks based on the
knowledge of the second-year undergraduate.
Due to the characteristics of FPGA - data loss when power loss, developers
will generally not use FPGA to develop systems that need to implement specific
functions. Due to the flexibility of FPGA, FPGA is currently mainly used as a
verification tool for special-purpose chips and general-purpose chips. At
present, the main force in the fields of deep learning and AI algorithms is GPU-
its powerful computing power provides a good platform for deep learning.
However, as a general-purpose graphics processing chip, GPU is far less flexible
than FPGA. In the future, FPGA will also play a huge role in similar fields such as
AI acceleration and accelerated algorithms.