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WEDNESDAY, OCTOBER 5, 2022

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AXI Protocol Quiz assembly (7)
concepts (6)
ARM AXI Protocol is widely used in the industry as a high performance protocol for communication on System on
design (2)
chips (SoC).
perl (3)
Here are a few quiz questions to test your knowledge on the AXI4 Protocol.
These concepts are useful to crack interview questions as well. questions (3)
quiz (2)
QUIZ systemverilog (2)
tools (8)
Question 1:
tutorial (6)
Consider that I am using a data bus width of 64-bits.
What are all the possible values that can be taken by AxSIZE? verilog (21)

Question 2: POPULAR POSTS

Consider the following scenario on a 32-bit data bus:
Booth Multiplier
AWADDR = 0x100
Verilog Code
AWBURST = 1 Booth's
AWLEN = 3 Multiplication
AWSIZE = 1 Algorithm is a
commonly used algorithm for
multiplication of two signed
a) Calculate number of beats in the burst. numbers. Let us see how to write
b) Calculate number of bytes transferred in each beat of the burst. a Verilo...
c) Calculate total number of bytes transferred in the burst.
3-Bit Up Counter
d) What will be the width of WSTRB signal? Verilog Code
e) For above transfer, write the pattern of WSTRB signal values for each beat. Is this a full transfer or a narrow A counter is
transfer? necessary for any
timing operation in a
f) Assume that the AWADDR is changed to 0x102 with other parameters remaining same. design. Let us see how to design
Is this an aligned or unaligned transfer with respect to (i) AWSIZE (ii) Bus width? a 3-bit counter and then
In this case, write the pattern of WSTRB signal values for each beat. parametrize it to obtain a...

g) Repeat subdivision f) if the AWADDR is 0x101.

Synchronous FIFO
Verilog Code
Question 3: The First In First
Consider the following transfer which is initiated to a memory. Out (FIFO) is a data
arrangement
structure in which the data that
enters first is the one that is
removed first. Let us...

Stack or LIFO
Verilog Code
The Last In First
Out (LIFO) or Stack
is a data
arrangement structure in which
a) What is the total number of bytes transferred in the burst? the data that enters the last is the
one that is removed fi...
b) Write down the address values to which each beat of the burst gets written.
c) Is this a narrow transfer or full transfer? Restoring Division
d) Can I initiate above transfer if (i) awaddr is 0x007BC812 (ii) awlen is 31? Verilog Code
e) Assume that the above write transfer needs to be done to a memory whose address range is from Restoring Division
Algorithm is one of
32’h00000000 to 32’h003FFFFF. What will happen? the division
f) Calculate the size of the memory mentioned in subdivision e) in units of MBits algorithms used for performing
division in digital systems. Let us
Question 4: see how to write the...

Consider the following memory containing the following data at the mentioned address locations:
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HI READER
If you find any content issues or
For this memory, read transfer is initiated with the following values (assume 32-bit data bus) code bugs in this blog, add a
comment or notify me using the
ARADDR = 0x102 contact form in the About page.
ARBURST = 1 Any other suggestions are also
ARLEN = 2 welcome!
ARSIZE = 1

a) How many beats of RDATA will I have?

b) What is the value of RDATA in each beat? Byte locations with don’t care data can be marked as ‘x’.

Scroll down for solutions.

It is recommended to attempt all the questions before scrolling down to check your answers!

SOLUTIONS:
Answer 1:
For a data-bus width of 64-bits (8-bytes), we can have AxSIZE values upto 8 bytes.
Possible values are: 3'b000, 3'b001, 3'b010, 3'b011

Answer 2:
a) AWLEN = 3. It means there are 4 beats in the burst.
b) AWSIZE = 1. It means 2^1 = 2 bytes are transferred in each beat of the burst.
c) Total number of bytes transferred in the burst = 4 * 2 = 8 bytes
d) For a 32-bit/4-byte data bus, width of WSTRB signal would be 4-bits.
e) WSTRB values for each beat: 4'b0011, 4'b1100, 4'b0011, 4'b1100.
Since size of each beat is less than the bus width, it is a narrow transfer.
f) Address 0x102 is aligned with respect to AWSIZE (2-byte aligned) but not with respect to bus width (not 4-byte
aligned)
g) AWADDR = 0x101.
In this case, the address is unaligned with respect to AWSIZE as well as bus width.
WSTRB values for each beat: 4'b0010, 4'b1100, 4'b0011, 4'b1100.

Answer 3:
a) AWLEN = 7 and AWSIZE = 2. It means (7+1)*(2^2) = 32 bytes are transferred.
b) First address is 0x007BC810. It is a wrap-32 transfer.
The remaining addresses are: 0x007BC814, 0x007BC818, 0x007BC81C, 0x007BC800,
0x007BC804, 0x007BC808, 0x007BC80C.
c) 4-bytes of data is transferred per beat, and it covers the full data-bus width. Hence it is a full transfer.
d) (i) Not possible, since according to AXI4 protocol, address must be aligned to the size for wrap transfers.
(ii) Not possible, since awlen = 15 is the maximum allowed value for wrap transfers.
e) We find that the initiated address 0x007BC810 is above the highest address 0x003FFFFF.
This wil result in a decoder error.
f) Top address = 0x003FFFFF
Number of bits used = 22
Total size of memory = 2^22 MBytes = 4MBytes = 32MBits

Answer 4:
a) Number of beats of RDATA = ARLEN + 1 = 3
b) Size of each beat = 2^1 = 2 bytes.
RDATA values = 32'h4433xxxx, 32'hxxxx6655, 32'h8877xxxx

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