Register

Organization
General Register Organization
• Example: RI
To perform the above operation, the control must provide binary
selection variables to the following selector inputs:
1. MUX A selector (SELA): to place the content of R2 into bus A.
2. MUX B selector (SELB): to place the content of R3 into bus B.
3. ALU operation selector (OPR): to provide the arithmetic addition
A

4. Decoder destination selector (SELD): to transfer the content of the

output bus into RI.
• Control Word:
SELA SELB SELD OPR

General Register Organization

 OPR Operation Symbo
00000
Select Transfer A TSFA
l
00001 Increment A
NCA 001 AD
RI RI RI 00010 D
010
00101
SUB
011
00110 Decrement A DECA
IOO
01000 A and B AND
101
01010 A or B OR
11001100 Axor B XOR

11101110 Complement A COMA

Encoding of Register Selection Fields 10000 Shift right A SHR
A
11000 Shift left A
 Encoding of ALU Operations

Stack
Organization
Stack Organization
A stack is a storage device that stores information in such a
manner that the item stored last is the first item retrieved (LIFO).
The register that holds the address for the stack is called a stack
pointer (SP) because its va ue always points at the top item in the
stack.
The physical registers of a stack are always available for reading
or writing. It is the content of the word that is inserted or deleted.
There are two types of stack organization
1. Register stack— built using registers
2. Memory stack— logical part of memory allocated as stack
Register Stack
63

Ad dress
 Register Stack
DR
• A stack can be placed in a portion of a large memory or it can be organized
as a collection of a finite number of memory words or registers. Figure
shows the organization of a 64-word register stack. The stack pointer
register SP contains a binary number whose value is equal to the address of
the word that is currently on top of the stack.
• In a 64-word stack, the stack pointer contains 6 bits because 26 = 64.
• Since SP has only six bits, it cannot exceed a number greater than 63

• The one-bit register FULL is set to 1 when the stack is full, and the
onebit register EMTY is set to 1 when the stack is empty of items.
 Register Stack
• DR is the data register that holds the binary data to be written into or
read out of the stack,
• PUSH Operation IF (sp= O) then
(EMTY f- 1)
M[SP] 4- DR FULL — o
IF (sp= O) then (FULL
+- 1) EMTY O
• POP Operation
DR 4- M[SP]
 Stack
Memory
Address
 Stack
DR

Memory
• The implementation of a stack in the CPU is done by assigning a portion
of memory to a stack operation and using a processor register as a stack
pointer.
• Figure shows a portion of computer memory partitioned into three
segments: program, data, and stack.
• The program counter PC points at the address of the next instruction in
the program which is used during the fetch phase to read an instruction.
• The address registers AR points at an array of data which is used
during the execute phase to read an operand.
 Stack
• The stack pointer SP points at the top of the stack which is used to
push or pop items into or from the stack.
• We assume that the items in the stack communicate with a data register
DR.
Memory
PUSH Operation • POP Operation
DR M[SP]
M[SP] DR
Reverse Polish Notation
The common mathematical method of writing arithmetic
expressions imposes difficulties when evaluated by a computer. The
Polish mathematician Lukasiewicz showed that arithmetic
expressions can be represented in prefix notation as well as postfix
notation.

Infix Prefix or Polish Postfix or reverse Polish

AB +
Reverse Polish
Evaluation of Arithmetic Expression
42
 Instruction
Formats
Instruction Formats
Instructions are categorized into different formats with respect to
the operand fields in the instructions.
1. Three Address Instructions
2. Two Address Instruction
3. One Address Instruction
4. Zero Address Instruction
5. RISC Instructions
 Address Instruction
Three
Computers with three-address instruction formats can use each address
field to specify either a processor register or a memory operand.
The program in assembly language that evaluates X (A + B) * (C +
D) is shown below.

ÄDD R2, c, n
MUL X, RI, R2
The advantage of three-address format is that it results in short
programs when evaluating arithmetic expressions.
 Address Instruction
The disadvantage is that the binary-coded instructions require too
many bits to specify three addresses.
Two
Two address instructions are the most common in commercial
computers. Here again each address field can specify either a
processor register or a memory word.
The program to evaluate X = (A + B) * (C + D) is as follows:
MOV RI,

MCV R2r c
ADD R2r
 Address Instruction
MUL R2 MOV x, RI

One
• One address instructions use an implied accumulator (AC)
register for all data manipulation.
• For multiplication and division these is a need for a second
register.
• However, here we will neglect the second register and assume
that the AC contains the result of all operations.
• The program to evaluate X = (A + B) * (C + D) is
LOAD
 Address Instruction
ADD Ace- AC+M [B]
STORE
LOAD c
ADD ÄC+M [D]
MUL AC— AC*M [T)
STORE x

Zero
• A stack-organized computer does not use an address field for the instructions ADD
and MUL.
• The PUSH and POP instructions, however, need an address field to specify the
operand that communicates with the stack.
 Address Instruction
• The program to evaluate X = (A + B) * (C + D) will be written for a stackorganized
computer.

• To evaluate arithmetic expressions in a stack computer, it is necessary to convert the

expression into reverse polish notation
PUSH TOS— M
[A]
PUSH TOS— M
[B]
ADD TOS— (Ä+B)
PUSH c
PUSH TOS— M
ros— (C+D) ros
— (C+D) *
(A+B)
 Address Instruction
POP MIX '—TOS
RISC Instruction
The instruction set of a typical RISC processor is restricted to the use of
load and store instructions when communicating between memory and CPU
All other instructions are executed within the registers of the CPU without
referring to memory.
A program for a RISC type CPU consists of LOAD and STORE
instructions that have one memory and one register address, and
computational-type instructions that have three addresses with all three
specifying processor registers.
The following is a program to evaluate X — (A + B) * (C + D)
LOAD
ADD RI,
ADD R3,
MUL RI, RI,
STORE x, RI

Addressing
Modes
 Modes
Addressing
The addressing mode specifies a rule for interpreting or
modifying the address field of the instruction before the operand
is actually referenced,
Computers use addressing mode techniques for the purpose of
accommodating one or both of the following provisions:
1. To give programming versatility to the user by providing such
facilities as pointers to memory, counters for loop control, indexing of
data, and program relocation.
2. To reduce the number of bits in the addressing field of the instruction.
There are basic 10 addressing modes supported by the
computer.
 Modes
Addressing
1. Implied Mode
2. Immediate Mode
3. Register Mode
4. Register Indirect Mode
5. Autoincrement or Autodecrement Mode
6. Direct Address Mode
7. Indirect Address Mode
1. Mode
8. Relative Address Mode
9. Indexed Addressing Mode
10. Base Register Addressing Mode
Implied
Operands are specified implicitly in the definition of the
instruction.
For example, the instruction "complement accumulator (CMA)"
is an implied-mode instruction because the operand in the
accumulator register is implied in the definition of the
instruction. In fact, all register reference instructions that use an
2. Mode
accumulator and zero address instructions are implied mode
instructions.
Immediate
Operand is specified in the instruction itself.
In other words, an immediate-mode instruction has an operand field
rather than an address field.
The operand field contains the actual operand to be used In
conjunction with the operation specified in the instruction.
Immediate mode of instructions is useful for Initializing register to
constant va ue.
3. Mode
E.g. MOV RI, 05H instruction copies immediate
number 05H to RI register.
Register
Operands are in registers that reside within the CPU.
The particular register is selected from a register field in the
instruction.
E.g. MOV AX, BX move value
from BX to AX register
4.
Register Indirect Mode
In this mode the instruction specifies a register in the CPU whose
contents give the address of the operand in memory.
Before using a register indirect mode instruction, the programmer
must ensure that the memory address of the operand IS placed in
the processor register with a previous instruction.
The advantage of this mode is that address field of the Instruction
uses fewer bits to select a register than would have been requ•red
to specify a memory address directly.
5.
E.g. MOV [RI], R2 value of R2 is moved to the memory location
specified in RI.
Autoincrement or Autodecrement Mode
This is similar to the register indirect mode expect that the
register is incremented or decremented after (or before) its value
is used to access memory.
When the address stored in the register refers to a table of data In
memory, it IS necessary to increment or decrement the register
6. Address
after every access to the table. This can be achieved by using the
increment or decrement instruction.
Direct Mode
In this mode the effective address is equal to the address part of
the instruction.
The operand resides in memory and its address is given directly
by the address field of the instruction.
E.g. ADD 457
7. Address
Indirect Mode
In this mode the address field of the instruction gives the address
where the effective address is stored in memory.
Control fetches the instruction from memory and uses its address part
to access memory again to read the effective address.
The effective address in this mode is obtained from the following
computational:
8. Address
Effective address = address part of instruction + content of CPU
register
Relative Mode
In this mode the content of the program counter is added to the
address part of the instruction in order to obtain the effective
address.
The address part of the instruction is usually a signed number
which can be either positive or negative.
9.
Effective address = address part of instruction + content of PC
Indexed Addressing Mode
In this mode the content of an index register is added to the
address part of the instruction to obtain the effective address. The
indexed register is a special CPU register that contain an index
value.
The address field of the instruction defines the beginning address
of a data array in memory.
10. Address
Each operand In the array is stored in memory relative to the begging
address.
Effective address = address part of instruction + content of index
register
11.
Base Register Addressing Mode
In this mode the content of a base register is added to the address
part of the instruction to obtain the effective address.
A base register is assumed to hold a base address and the address
field of the instruction gives a displacement relative to this base
address.
The base register addressing mode is used in computers to
facilitate the relocation of programs in memory.
Effective address = address part of instruction + content of base
register
Addressing Modes (Example)
Address Memory
Load to AC Mode
200 PC - 200 Address = 500
201
Next instruction
202

450
700

800

900

325

300
 1
RI =

XR - 100

500

702

1
AC
Data transfer &
manipulation
instructions
 Instructions
Data transfer
• Data transfer instructions move data from one place in the computer to
another without changing the data content.
• The most common transfers are between memory and processor registers,
between processor registers and input or output, and between the
processor registers themselves.
Name
Load LD
Store ST
MO
Move
V
Exchange XCH
n put IN
Output OUT
 PUS
Push
H
Pop POP
Data manipulation instructions
Data manipulation instructions perform operations on data and
provide the computational capabilities for the computer.
The data manipulation instructions in a typical computer are
usually divided into three basic types:
1. Arith metic instructions
2. Logical and bit manipulation instructions
3. Shift instructions
1. Instructions
Arithmetic

Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
MU
Multiply
L
Divide DIV
Add with carry ADD
2.
C
SUB
Subtract with borrow
B
Negate (2's complement) NEG
Logical & Bit Manipulation Instructions
Name

Clear CLR
Complement COM
AND AND
OR OR
Exclusive-OR XOR
3. Instructions
CIR
Clear carry
C
Set carry SETC
COM
Complement carry C
Enable interrupt
Disable interrupt

Shift
Logical shift right SHR
Logical shift left SHI
4.
SHR
Arithmetic shift right
A
SHL
Arithmetic shift left
A
Rotate right ROR
Rotate left ROL
ROR
Rotate right through carry
C
ROL
Rotate left through carry C
 Program
Program Control
Control
• A program control type of instruction, when executed, may change
the address value in the program counter and cause the flow of control
to be altered.
• The change in value of the program counter as a result of the execution
of a program control instruction causes a break in the sequence of
instruction execution.
Name
Branch BUN
Jump JMP
Skip SO
Call CALL
Return RET
Compare (by subtraction) CMP
Test (by ANQi.ng) TST
Status Bit Conditions
Output F
Status Bit Conditions
Bit C (carry) is set to 1 if the end carry Ca is 1. It is cleared to O if
the carry is O.
Bit S (sign) is set to 1 if the highest-order bit F7 is 1. It is set to O
if the bit is O.
Bit Z (zero) is set to 1 if the output is zero and Z = O if the output
is not zero.
Bit V (overflow) is set to 1 if the exclusive-OR of the last two
carries is equal to 1, and ceared to O otherwise. This is the
condition for an overflow when negative numbers are in 2's
complement.
Conditional Branch Instructions

S0

BV Branch if overflow
BNV Branch if no overflow
Unsigned compare conditions (A — B)
BHI Branch if higher
BHE Branch if higher or equal A > B
BLO Branch if lower
 Conditional Branch Instructions

BN Branch if not equal

Signed compare conditions (A—B
BGT Branch if greater than
BGE Branch if greater or equal A 2 B
BLT Branch if less than
BLE Branch if less or equal
BE Branch if equal Branch if not equal

Program Interrupt
The interrupt procedure is, in principle, quite similar to a
subroutine call except for three variations:
1. The interrupt is usually initiated by an internal or external signal rather than
from the execution of an instruction
2. The address of the interrupt service program is determined by the hardware
rather than from the address field of an instruction
3. An interrupt procedure usually stores all the information
necessary to define the state of the CPU rather than storing only
the program counter. After a program has been interrupted and
the service routine been executed, the CPU must return to exactly
the same state that it was when the interrupt occurred. Only if
this happens will the interrupted program be able to resume
exactly as if nothing had happened.
 Program Interrupt
The state of the CPU at the end of the execute cyce (when the
interrupt is recognized) is determined from:
1. The content of the program counter
2. The content of all processor registers
3. The content of certain status conditions

Program Status Word (PSW)

The collection of all status bit conditions in the CPU is
sometimes called a program status word or PSW.
 The PSW is stored in a separate hardware register and contains the
status information that characterizes the state of the CPU.
Types of interrupts
There are three major types of interrupts that cause a break in the
normal execution of a program. They can be classified as:
1. External interrupts
2. Internal interrupts
3. Software interrupts
1.
External Interrupt
External interrupts come from
• Input-output (I/O) devices
• Timing device
• Circuit monitoring the power supply
• Any other external source
Examples that cause external interrupts are
• I/O device requesting transfer of data
• I/O device finished transfer of data
• E apsed time of an event
• Power failure
External interrupts are asynchronous.
2.
External interrupts depend on external conditions that are
independent of the program being executed at the time.
Internal interrupts (Traps)
Internal interrupts arise from
Il egal or erroneous use of an instruction or data.
Examples of interrupts caused by internal error conditions like
Register overflow
Attempt to divide by zero
invalid operation code
stack overflow protection violation
These error conditions usually occur as a result of a
premature termination of the instruction execution.
3.
Internal interrupts are synchronous with the program. If the
program is rerun, the internal interrupts will occur in the same
place each time.
Software Interrupts
A software interrupt is a special call instruction that behaves like an
interrupt rather than a subroutine cal
The most common use of software interrupt is associated with a
supervisor call instruction, This instruction provides means for
switching from a CPU user mode to the supervisor mode.
When an input or output transfer is required, the supervisor mode
is requested by means of a supervisor call instruction. This
instruction causes a software interrupt that stores the old CPU
4.
state and brings in a new PSW that belongs to the supervisor
mode.
The calling program must pass information to the operating system
in order to specify the particular task requested.
 Reduced
Instruction Set
Computer
 (RISC)
Reduced Instruction Set Computer (RISC)
Characteristics of RISC are as follows:
Relatively few instructions
Relatively few addressing modes
Memory access limited to load and store instructions
All operations done within the registers of the CPU
Fixed-length, easily decoded instruction format
Single-cycle instruction execution
Hardwired rather than microprogrammed control
A relatively large number of registers in the processor unit
Use of overlapped register windows to speed-up procedure call and return
Efficient instruction pipeline
Compiler support for efficient translation of high-level language programs into
machine language programs

Complex
Instruction Set
Computer
 (CISC)
Complex Instruction Set Computer (CISC)
Characteristics of CISC are as follows:
A larger number of instructions —typically from 100 to 250 instructions
Some instructions that perform specialized tasks and are used infrequently
A large variety of addressing modes —typically from 5 to 20 different
modes
Variable-length instruction formats
Instructions that manipulate operands in memory
Overlapped Register Window
A characteristic of some RISC processors is their use of
overlapped register windows to provide the passing of
parameters and avoid the need for saving and restoring register
values.
Each procedure call results in the allocation of a new window
consisting of a set of registers from the register file for use by
the new procedure.
Windows for adjacent procedures have overlapping registers
that are shared to provide the passing of parameters and results.
Overlapped Register Window

R47
Common to Band C
R42
Window size - L + 2C G
Register file = (L + C) W + G
Overlapped Register Window
Common to A and B

Common ta allLocal to A
procedures
RIS
Common to A and D
Global
RIO

registers Proc A
Suppose that procedure A calls procedure B.
Overlapped Register Window
• Registers R26 through R31 are common to both procedures, and
therefore procedure A stores the parameters for procedure B in these
registers.
• Procedure B uses local registers R32 through R41 for local variable
storage.
• If procedure B calls procedure C, it will pass the parameters through
registers R42 through R47,
• When procedure B is ready to return at the end of its computation, the
program stores results of the computation in registers R26 through
R31 and transfers back to the register window of procedure A.
Overlapped Register Window
• Note that registers RIO through R15 are common to procedures A and
D because the four windows have a circular organization with A being
adjacent to D.