LAKIREDDY BALI REDDY COLLEGE OF ENGINEERING (AUTONOMOUS)

Microprocessors & Microcontrollers

Assignment - 2

1. Pin configuration of 8086 µ Processor

Signal description of 8086:

 The 8086 is a 16-bit microprocessor. This microprocessor operates in single

processor or multiprocessor configurations to achieve high performance.
 The pin configuration of 8086 is shown in the figure. Some of the pins serve a particular
function in minimum mode (single processor mode) and others function in maximum
mode (multiprocessor mode).
The 8086 signals are categorized into 3 types:
1. Common signals for both minimum mode and maximum mode.
2. Special signals which are meant only for minimum mode
3. Special signals which are meant only for maximum mode
Common Signals for both Minimum mode and Maximum mode:
AD7 ↔ AD0 : The address/ data bus lines are the multiplexed address data bus and contain
the right most eight bit of memory address or data. The address and data bits are separated by
using ALE signal.
AD15 ↔ AD8 : The address/data bus lines compose the upper multiplexed address/data bus.
This lines contain address bit
A15 ↔ A8 or data bus D15 ↔ D8 . The address and data bits are separated by using ALE signal.
A19 / S6 ↔ A18 / S3 The address/status bus bits are multiplexed to provide address signals
A19 ↔ A16 and also status bits
S6 ↔ S3 : The address bits are separated from the status bits using the ALE signals. The
status bit S6 is always a logic 0, bit S5 indicates the condition of the interrupt flag bit. The S4
and S3 indicate which segment register is presently being used for memory access.

S4 S3 Type of segment register used

0 0 Extra segment
0 1 Stack segment
1 0 Code or no segment
1 1 Data Segment

BHE / S7 : The bus high enable (BHE) signal is used to indicate the transfer of data over the higher

order D15 ↔ D8 data bus. It goes low for the data transfer over D15 ↔ D8 and is used to derive
chip select of odd address memory bank or peripherals.

BHE A0 Indication
0 0 Whole word
0 1 Upper byte from or to odd address
1 0 Lower byte from or to even address
1 1 None

RD : Read: whenever the read signal is at logic 0, the data bus receives the data from the
memory or I/O devices connected to the system
READY: This is the acknowledgement from the slow devices or memory that they have completed
the data transfer operation. This signal is active high.
INTR: Interrupt Request: Interrupt request is used to request a hardware interrupt of INTR is
held high when interrupt enable flag is set, the 8086 enters an interrupt acknowledgement
cycle after the current instruction has completed its execution.
TEST : This input is tested by “WAIT” instruction. If the TEST input goes low; execution will

continue. Else the processor remains in an idle state.

NMI: Non-maskable Interrupt: The non-maskable interrupt input is similar to INTR except that
the NMI interrupt does not check for interrupt enable flag is at logic 1, i.e, NMI is not maskable
internally by software. If NMI is activated, the interrupt input uses interrupt vector 2.
RESET: The reset input causes the microprocessor to reset itself. When 8086 reset, it restarts
the execution from memory location FFFF0H. The reset signal is active high and must be active
for at least four clock cycles.
CLK: Clock input: The clock input signal provides the basic timing input signal for processor
and bus control operation. It is asymmetric square wave with 33% duty cycle.
VCC (+5V): Power supply for the operation of the internal circuit
GND: Ground for the internal circuit
MN / MX : The minimum/maximum mode signal to select the mode of operation either in
minimum or maximum mode configuration. Logic 1 indicates minimum mode.
Minimum mode Signals: The following signals are for minimum mode operation of 8086.

M / IO : Memory/IO - M / IO signal selects either memory operation or I/O operation. This line
indicates that the microprocessor address bus contains either a memory address or an I/O port
address. Signal high at this pin indicates a memory operation. This line is logically equivalent to
S 2 in maximum mode.

INTA : Interrupt acknowledge: The interrupt acknowledge signal is a response to the INTR input

signal. The INTA signal is normally used to gate the interrupt vector number onto the data bus
in response to an interrupt request.
ALE- Address Latch Enable: This output signal indicates the availability of valid address on the
address/data bus, and is connected to latch enable input of latches.
DT / R :Data transmit/Receive: This output signal is used to decide the direction of date flow

through the bidirectional buffer. DT / R =1 Indicates transmitting and DT / R = 0 indicates

receiving the data.

DEN : Data Enable: Data bus enable signal indicates the availability of valid data over the
address/data lines.
WR : Write: whenever the write signal is at logic 0, the data bus transmits the data to the memory
or I/O devices connected to the system.

HOLD: The hold input request a direct memory access (DMA). If the hold signal is at logic 1, the
micro process stops its normal execution and places its address, data and control bus at the
high impedance state.
HLDA: Hold acknowledgement indicates that 8086 has entered into the hold state.
Maximum mode signal: The following signals are for maximum mode operation of 8086.
S 2 , S 1 , S 0 : Status lines: These are the status lines that reflect the type of operation being carried
out by the processor.

These status lines are encoded as follows

These status lines are encoded as follows
S2 S1 S0 Function
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive (In active)
 LOCK : The lock output is used to lock peripherals off the system, i.e, the other system bus
masters will be prevented from gaining the system bus.

QS1 and QS0 - Queue status: The queue status bits shows the status of the internal instruction
queue. The encoding of these signals is as follows

QS1 QS0 Function

0 0 No operation, queue is idle

0 1 First byte of opcode
1 0 Queue is empty
1 1 Subsequent byte of opcode

RQ / GT1and RQ / GT 0 : request/Grant: The request/grant pins are used by other local bus
masters to force the processor to release the local bus at the end of the processors current bus
cycle. These lines are bidirectional and are used to both request and grant a DMA operation.
RQ / GT 0 is having higher priority than RQ / GT1

2. Operation of 8086 in Minimum mode operation with Read/ Write Timing diagrams.

The microprocessor 8086 is operated in minimum mode by strapping its MN / MX pin to

logic1. In this mode, all the control signals are given out by the microprocessor chip itself. There
is a single microprocessor in the minimum mode system. The remaining components in the
system are latches, transreceivers, clock generator, memory and I/O devices. Some type of chip
selection logic may be required for selecting memory or I/O devices, depending upon the address
map of the system.

The latches are generally buffered output D-type flip-flops, like, 74LS373 or 8282. They are
used for separating the valid address from the multiplexed address/data signals and are
controlled by the ALE signal generated by 8086. Since it has 20 address lines and 16 data lines,
the 8086 CPU requires three octal address latches and two octal data buffers for the complete
address and data separation.

Transreceivers are the bidirectional buffers and sometimes they are called as data
amplifiers. They are required to separate the valid data from the time multiplexed address/data

signal. They are controlled by two signals, namely, DEN and DT / R . The DEN signal indicates

that the valid data is available on the data bus, while DT / R indicates the direction of data, i.e.
from or to the processor.

The system contains memory for the monitor and users program storage. Usually, EPROMS
are used for monitor storage, while RAMs for users program storage. A system may contain I/O
devices for communication with the processor as well as some special purpose I/O devices.
 The clock generator generates the clock from the crystal oscillator and then shapes it and
divides to make it more precise so that it can be used as an accurate timing reference for the
system. The clock generator also synchronizes some external signals with the system clock.

The working of the minimum mode configuration system described in terms of the timing
diagrams. The timing diagram can be categorized in two parts, the

first is the timing diagram for read cycle and the second is the timing diagram for write cycle.

Read Cycle Timing Diagram:

 The read cycle begins in T1 with the assertion of the address latch enable (ALE) signal and
also M/IO’ signal. During the negative going edge of this signal, the valid address is latched on
the local bus. The BHE and A0 signals address low, high or both bytes. From T1 to T4, the
M / IO signal indicates a memory or I/O operation. At T2, the address is removed from the local
bus and is sent to the output. The bus is then tri-stated. The read ( RD ) control signal is also
activated in T2. The read RD signal causes the addressed device to enable its data bus drivers.
After RD goes low, the valid data is available on the data bus. The addressed device will drive the
READY line high. When the processor returns the read signal to high level, the addressed device
will again tri-state its bus drivers.

Write Cycle Timing Diagram:

A write cycle also begins with the assertion of ALE and the emission of the address. The
M / IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the
address in T1, the processor sends the data to be written to the addressed location. The data
remains on the bus until middle of T4 state. The WR becomes active at the beginning of T2
(unlike RD is somewhat delayed in T2 to provide time for floating). The BHE and A0 signals are
used to select the proper byte or bytes of memory or I/O word to be read or written. The M / IO ,
RD and WR signals indicate the types of data transfer as specified in Table
3. Operation of 8086 in Maximum mode operation with Read/ Write Timing diagrams.

In the maximum mode, the 8086 is operated by strapping the MN / MX pin to ground. In
this mode, the processor derives the status signals S 2 , S 1 , S 0 . Another chip called bus controller
derives the control signals using this status information. In the maximum mode, there may be
more than one microprocessor in the system configuration. The other components in the system
are the same as in the minimum mode system. The general system organization is as shown in
the below figure.

The basic functions of the bus controller chip IC8288, is to derive control signals like RD
and WR (for memory and I/O devices), DEN, DT / R , ALE, etc. using the information made
available by the processor on the status lines. The bus controller chip has input lines S 2 , S 1 , S 0
and CLK. These inputs to 8288 are driven by the CPU. It derives the outputs ALE, DEN, DT / R ,
MWTC, MRDC , IORC , IOWC and INTA. INTA pin is used to issue two interrupt acknowledge
pulses to the interrupt controller or to an interrupting device.

IORC*, IOWC* are I/O read command and I/O write command signals respectively. These
signals enable an IO interface to read or write the data from or to the addressed port. The
MRDC*, MWTC* are memory read command and memory write command signals respectively
and may be used as memory read and write signals. All these command signals instruct the
memory to accept or send data from or to the bus. The maximum mode system timing diagrams
are also divided in two portions as read (input) and write (output) timing diagrams. The
address/data and address/status timings are similar to the minimum mode. ALE is asserted in
T1, just like minimum mode. The only difference lies in the status signals used and the available
control and advanced command signals.
Memory Read Timing Diagram:

Memory Write Timing Diagram:

4. Interrupt vector table and Types of interrupts.
 In an 8086 system the first 1 Kb of memory from 00000H to 003FFH is reserved for storing the starting addresses of interrupt service routines.
 This block of memory is often called the INTERRUPT VECTOR TABLE or the INTERRUPT POINTER TABLE.
 Since 4 bytes are required to store the CS and IP values for each interrupt service procedure, the table can hold the starting addresses for 256 interrupt
service routines.

 Each interrupt type is given a number between 0 to 255 and the address of each interrupt is found by multiplying the type by 4 e.g. for type 11,
interrupt address is 11×4=4410=0002CH
 Only the first five types have explicit definitions.
 The next 27 interrupt types, from 5 to 31, are reserved by Intel for use in future microprocessors.
 The upper 224 interrupt types, from 32 to 255, available for user for hardware or software interrupts.
 When 8086 responds to an interrupt, it automatically goes to specified location in the interrupt vector table to get the starting address of
interrupt service routine.

8086 Interrupts Types:

1. Divide by Zero Interrupt (Type 0):
When the quotient from either a DIV or IDIV instruction is too large to fit in the result register; 8086 will automatically execute type 0 interrupt.
2. Single Step Interrupt (Type 1):
The type 1 interrupt is single step trap. In the single step mode, system will execute one instruction and wait for further direction from user. The user
can examine the contents of registers and memory locations and if they are correct, user can tell the system to execute the next instruction. This
feature is useful for debugging assembly language programs.
3. Non Maskable Interrupt (Type 2):
As the name suggests, this interrupt cannot be disabled by any software instruction. This interrupt is activated by low to high transition on 8086 NMI
input pin. In response, 8086 will do a type 2 interrupt.
4. Break Point Interrupt (Type 3):
The type 3 interrupt is used to implement breakpoint function in the system. The type 3 interrupt is produced by execution of the INT 3 instruction.
Breakpoint function is often used as debugging aids in cases where single stepping provides more details than wanted.
5. Overflow Interrupt (Type 4):
The type 4 interrupt is used to check overflow condition after any signed arithmetic operation in the system. The 8086 overflow flag, OF, will be
represented in the destination register or memory location.
5. Interrupt, Interrupt Service Routine and steps involved, if an interrupt is initiated
in 8086 Microprocessor.
 If an interrupt has been requested, the 8086 responds to interrupt by stepping through the following series of major steps:

1. It decrements the stack pointer by 2 pushes the flag register on the stack.

2. It disables the 8086 INTR interrupt input by clearing the interrupt flag(IF) in the flag register.

3. It resets the trap flag (TF) in the flag register.

4. It decrements the stack pointer by 2 and pushes the current code segment register contents on the stack.

5. It decrements the stack pointer again by 2 and pushes the current instruction pointer contents on the stack.

6. It does an indirect far jump to start of the procedure by loading the CS and IP values for the start of the interrupt service routine.

 An IRET instruction at the end of the interrupt service routine returns execution to main program.

 The 8086 gets the new values of CS and IP register from four memory addresses.

 When it responds to an interrupt, the 8086 goes to memory locations to get the CS an IP values to start of the interrupt service routine.

6. DOS and BIOS interrupts

DOS BIOS
S.No
1. DOS is loaded from the bootable BIOS is located in an 8 Kbyte ROM.
diskette.
The programs within the ROM-BIOS
DOS program offer different degree of provide the most direct, lowest level
2. flexibility, portability and hardware interaction with the various devices in
independence. the system. Using these programs
require hardware knowledge.
DOS has ability to load and execute ROM-BIOS does not have ability to load and
3. programs directly. execute programs directly.
DOS can store data on the ROM-BIOS cannot store data on the diskette
4. diskette organized as a logical organized as a logical files.
files.
DOS has command interpreter to allow ROM-BIOS have no command interpreter to
5. us to copy files, print files and delete allow us to copy files, print files and delete
files. files.
7. Design an 8086 based system with the following specifications
i.8086 in minimum mode
ii.64Kb EPROM
iii.64Kb RAM
Draw the complete schematic of the design indicating address map
8. Design an 8086 based system with the following specifications
i.8086 in maximum mode
ii.64Kb EPROM
iii.64Kb RAM
Draw the complete schematic of the design indicating address map