LAKIREDDY BALI REDDY COLLEGE OF ENGINEERING (AUTONOMOUS)

Microprocessors & Microcontrollers

Assignment - 1
1. Register organization of 8086 Microprocessors and their special functions
Register organization:
The 8086 has a powerful set of registers known as general purpose registers and special purpose
registers. All of them are 16-bit registers.
General purpose registers:
These registers can be used as either 8-bit registers or 16-bit registers. They may be either used for
holding data, variables and intermediate results temporarily or for other purposes like a counter or for
storing offset address for some particular addressing modes etc.
Special purpose registers:
These registers are used as segment registers, pointers, index registers or as offset storage registers for
particular addressing modes.
The 8086 registers are classified into the following types:
i. General Data Registers
ii. Segment Registers
iii. Pointers and Index Registers
iv. Flag Register
General Data Registers:
The registers AX, BX, CX and DX are the general purpose 16-bit registers. AX is used as 16-bit
accumulator. The lower 8-bit is designated as AL and higher 8-bit is designated as AH. AL can be used
as an 8-bit accumulator for 8-bit operation. All data register can be used as either 16 bit or 8 bit. BX is
a 16 bit register; BL indicates the lower 8-bit of BX and BH indicates the higher 8-bit of BX. The register
BX is used as offset storage for forming physical address in case of certain addressing modes. The
register CX is used default counter in case of string and loop instructions. DX register is a general
purpose register which may be used as an implicit operand or destination in case of a few instructions.
Segment Registers: There are 4 segment registers. They are: Code Segment Register(CS), Data
Segment Register(DS), Extra Segment Register(ES), Stack Segment Register(SS).
The 8086 architecture uses the concept of segmented memory. 8086 able to address a memory
capacity of 1 megabyte and it is byte organized. This 1 megabyte memory is divided into 16 logical
segments. Each segment contains 64 K bytes of memory.
Code segment register (CS): is used for addressing memory location in the code segment of the memory,
where the executable program is stored.
Data segment register (DS): points to the data segment of the memory where the data is stored.
Extra Segment Register (ES) : also refers to a segment in the memory which is another data segment in
the memory.
Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack segment is
that segment of memory which is used to store stack data.
While addressing any location in the memory bank, the physical address is calculated from two parts:
Physical address= segment address + offset address
The first is segment address, the segment registers contain 16-bit segment base addresses, related to
different segment.
The second part is the offset value in that segment.
 Pointers and Index Registers:
The index and pointer registers are given below:
IP—Instruction pointer-store memory location of next instruction to be executed
BP—Base pointer
SP—Stack pointer
SI—Source index
DI—Destination index
The pointers registers contain offset within the particular segments. The pointer register IP contains
offset within the code segment. The pointer register BP contains offset within the data segment. Thee
pointer register SP contains offset within the stack segment. The index registers are used as general
purpose registers as well as for offset storage in case of indexed, base indexed and relative base indexed
addressing modes. The register SI is used to store the offset of source data in data segment. The
register DI is used to store the offset of destination in data or extra segment. The index registers are
particularly useful for string manipulation.
8086 flag register
The 8086 flag register contents indicate the results of computation in the ALU. It also contains some
flag bits to control the CPU operations. A 16 bit flag register is used in 8086. It is divided into two parts
.
i. Condition code or status flags
ii. Machine control flags
The condition code flag register is the lower byte of the 16-bit flag register. The condition code flag
register is identical to 8085 flag register, with an additional overflow flag.
The control flag register is the higher byte of the flag register. It contains three flags namely direction
flag (D), interrupt flag (I) and trap flag (T).
2. Flag register of 8086 Microprocessor and functionality of each flag bit.
The 8086 flag register contents indicate the results of computation in the ALU. It also contains some
flag bits to control the CPU operations.
A 16 bit flag register is used in 8086. It is divided into two parts .
i. Condition code or status flags
ii. Machine control flags
The condition code flag register is the lower byte of the 16-bit flag register. The condition code flag
register is identical to 8085 flag register, with an additional overflow flag. The control flag register is the
higher byte of the flag register. It contains three flags namely direction flag (D), interrupt flag (I) and
trap flag (T).

Flag Register of 8086 Microprocessor

Description of each flag bit:
SF- Sign Flag: This flag is set, when the result of any computation is negative. For signed computations
the sign flag equals the MSB of the result.
ZF- Zero Flag: This flag is set, if the result of the computation or comparison performed by the previous
instruction is zero.
PF- Parity Flag: This flag is set to 1, if the lower byte of the result contains even number of 1’s.
CF- Carry Flag: This flag is set, when there is a carry out of MSB in case of addition or a borrow in case
of subtraction.
AF-Auxilary Carry Flag: This is set, if there is a carry from the lowest nibble, i.e, bit three during
addition, or borrow for the lowest nibble, i.e, bit three, during subtraction.
OF- Over flow Flag: This flag is set, if an overflow occurs, i.e, if the result of a signed operation is large
enough to accommodate in a destination register. The result is of more than 7-bits in size in case of 8-
bit signed operation and more than 15-bits in size in case of 16-bit sign operations, and then the
overflow will be set.
TF- Tarp Flag: If this flag is set, the processor enters the single step execution mode. The processor
executes the current instruction and the control is transferred to the Trap interrupt service routine.
IF- Interrupt Flag: If this flag is set, the mask able interrupts are recognized by the CPU, otherwise they
are ignored.
D- Direction Flag: This is used by string manipulation instructions. If this flag bit is ‘0’, the string is
processed beginning from the lowest address to the highest address, i.e., auto incrementing mode.
Otherwise, the string is processed from the highest address towards the lowest address, i.e., auto
decrementing mode.
3. Architecture of 8086 Microprocessor and advantage of dividing the architecture in to two
functional blocks BIU and EU

Architecture of 8086 microprocessor:

As shown in the figure, the 8086 CPU is divided into two independent functional parts
 Bus Interface Unit(BIU)
 Execution Unit(EU)
Dividing the work between these two units’ speeds up processing.
8086 HAS PIPELINING ARCHITECTURE:
 While the EU is decoding an instruction or executing an instruction, which does not require use of
the buses, the BIU fetches up to six instruction bytes for the following instructions.
 The BIU stores these pre-fetched bytes in a first-in-first-out register set called a queue.
 When the EU is ready for its next instruction from the queue in the BIU. This is much faster than
sending out an address to the system
 memory and waiting for memory to send back the next instruction byte or bytes.
 Except in the case of JMP and CALL instructions, where the queue must be dumped and then
reloaded starting from a new address, this pre-fetch and queue scheme greatly speeds up
processing.
 Fetching the next instruction while the current instruction executes is called pipelining.
Execution Unit (EU):
The execution unit of the 8086 tells the BIU where to fetch instructions or data from, decodes
instructions, and executes instructions. The EU contains control circuitry, which directs internal
operations. A decoder in the EU translates instructions fetched from memory into a series of actions,
which the EU carries out. The EU has a 16-bit arithmetic logic unit (ALU) which can add, subtract,
AND, OR, XOR, increment, decrement, complement or shift binary numbers.
 The main functions of EU are:
 Decoding of Instructions
 Execution of instructions
Steps involved in Execution:
(i). EU extracts instructions from top of queue in BIU
(ii). Decode the instructions
(iii). Generates operands if necessary Passes operands to BIU & requests it to perform
read or write bus cycles to memory or I/O
(iv). Perform the operation specified by the instruction on operands
Bus Interface Unit (BIU):
The BIU sends out addresses, fetches instructions from memory, reads data from ports and memory,
and writes data to ports and memory. In simple words, the BIU handles all transfers of data and
addresses on the buses for the execution unit.
4. Addressing modes of 8086 Microprocessor
Addressing mode indicates a way of locating data or operands.
The addressing modes describe the types of operands and the way they are accessed for executing an
instruction. According to the flow of instruction execution, the instructions may be categorized as
i) Sequential control flow instructions and
ii) Control transfer instructions
Sequential control flow instructions are the instructions, which after execution, transfer control to the
next instruction appearing immediately after it (in the sequence) in the program. For example, the
arithmetic, logic, data transfer and processor control instructions are sequential control flow
instructions. The control transfer instructions, on the other hand, transfer control to some predefined
address or the address somehow specified in the instruction, after their execution. For example, INT,
CALL, RET and JUMP instructions fall under this category.
The addressing modes for sequential control transfer instructions are:
1. Immediate: In this type of addressing, immediate data is a part of instruction and appears in the
form of successive byte or bytes.
Ex: MOV AX, 0005H
In the above example, 0005H is the immediate data. The immediate data may be 8-bit or 16-bit in size.
2. Direct: In the direct addressing mode a 16-bit memory address (offset) is directly specified in the
instruction as a part of it.
Ex: MOV AX, [5000H]
Here, data resides in a memory location in the data segment, whose effective address may be completed
using 5000H as the offset address and content of DS as segment address. The effective address here, is
10H * DS + 5000H.
3. Register: In register addressing mode, the data is stored in a register and is referred using the
particular register. All the registers, except IP, may be used in this mode.
Ex: MOV BX, AX
4. Register Indirect: Sometimes, the address of the memory location, which contains data or operand,
is determined in an indirect way, using the offset register. This mode of addressing is known as register
indirect mode. In this addressing mode, the offset address of data is in either BX or SI or DI register.
The default segment is either DS or ES. The data is supposed to be available at the address pointed to
by the content of any of the above registers in the default data segment.
Ex: MOV AX, [BX]
Here, data is present in a memory location in DS whose offset address is in BX. The effective address of
the data is given as 10H * DS+[BX].
5. Indexed: In this addressing mode, offset of the operand is stored in one of the index registers. DS
and ES are the default segments for index registers, SI and DI respectively. This is a special case of
register indirect addressing mode.
Ex: MOV AX, [SI]
Here, data is available at an offset address stored in SI in DS. The effective address, in this case, is
computed as 10*DS+[SI].
6. Register Relative: In this addressing mode, the data is available at an effective address formed by
adding an 8-bit or 16-bit displacement with the content of any one of the registers BX, BP, SI and DI in
the default (either DS or ES) segment.
Ex: MOV AX, 50H[BX]
Here, the effective address is given as 10H *DS+50H+[BX]
7. Based Indexed: The effective address of data is formed, in this addressing mode, by adding content
of a base register (any one of BX or BP) to the content of an index register (any one of SI or DI). The
default segment register may be ES or DS.
Ex: MOV AX, [BX][SI]
Here, BX is the base register and SI is the index register the effective address is computed as 10H * DS
+ [BX] + [SI].
8. Relative Based Indexed: The effective address is formed by adding an 8 or 16-bit displacement with
the sum of the contents of any one of the base register (BX or BP) and any one of the index register, in
a default segment.
Ex: MOV AX, 50H [BX] [SI]
Here, 50H is an immediate displacement, BX is base register and SI is an index register the effective
address of data is computed as 10H * DS + [BX] + [SI] + 50H
For control transfer instructions, the addressing modes depend upon whether the destination is within
the same segment or different one. It also depends upon the method of passing the destination address
to the processor. Basically, there are two addressing modes for the control transfer instructions,
intersegment addressing and
Intra-segment addressing modes. If the location to which the control is to be transferred lies in a
different segment other than the current one, the mode is called intersegment mode. If the destination
location lies in the same segment, the mode is called intra-segment mode.

Addressing modes for Control Transfer Instructions

9. Intra-segment Direct Mode: In this mode, the address to which the control is to be transferred lies
in the same segment in which the control transfer instruction lies and appears directly in the
instruction as an immediate displacement value. In this addressing mode, the displacement is
computed relative to the content of the instruction pointer IP. The effective address to which the control
 will be transferred is given by the sum of 8 or 16-bit displacement and current content of IP. In the
case of jump instruction, if the signed displacement (d) is of 8-bits (i.e –128<d<+128) we
term it as short jump and if it is of 16-bits (i.e-32, 768<d<+32,768) it is termed as long jump.
10. Intra-segment Indirect Mode: In this mode, the displacement to which the control is to be
transferred, is in the same segment in which the control transfer instruction lies, but it is passed to the
instruction indirectly. Here, the
branch address is found as the content of a register or a memory location. This addressing mode may
be used in unconditional branch instructions.
11. Inter-segment Direct: In this mode, the address to which the control is to be transferred is in a
different segment. This addressing mode provides a means of branching from one code segment to
another code segment. Here, the CS
and IP of the destination address are specified directly in the instruction.
12. Inter-segment Indirect: In this mode, the address to which the control is to be transferred lies in
a different segment and it is passed to the instruction indirectly, i.e contents of a memory block
containing four bytes, i.e IP (LSB), IP(MSB), CS(LSB) and CS (MSB) sequentially. The starting address of
the memory block may be referred using any of the addressing modes, except immediate mode.
5. The contents of different registers are given below.
Offset (displacement)=5000H; [AX]=1000H, [BX]=2000H, [SI]=3000H, [DI]=4000H, [BP]=5000H,
[SP]=6000H, [CS]=0000H, [DS]=1000H, [SS]-2000H, [IP]=7000H
Calculate the effective addresses for the following addressing modes.
(i).Direct addressing mode
(ii). Register indirect
(iii).Register relative
(iv).Based indexed
(v).Relative based index
Forming the effective Addresses:
The following examples explain forming of the effective addresses in the different modes.
Ex: 1. The contents of different registers are given below. Form effective addresses for different
addressing modes. Offset (displacement)=5000H
[AX]-1000H, [BX]- 2000H, [SI]-3000H, [DI]-4000H, [BP]-5000H, [SP]-6000H,[CS]-0000H, [DS]-1000H,
[SS]-2000H, [IP]-7000H
Shifting segment address four bits to the left is equivalent to multiplying it by 16D or 10H
i. Direct addressing mode: ii. Register indirect:
MOV AX,[5000H] MOV AX, [BX]
DS : OFFSET ↔ 1000H : 5000H DS: BX ↔ 1000H: 2000H
10H*DS ↔ 10000—segment address 10H*DS↔ 10000—segment address
offset ↔ +5000---offset address [BX] ↔ +2000---offset address
_______ ________
15000H – Effective address 12000H – Effective address
_______ ________
iii. Register relative: iv. Based indexed:
MOV AX, 5000 [BX] MOV AX, [BX] [SI]
DS : [5000+BX]
10H*DS ↔ 10000 DS : [BX + SI]
offset ↔ +5000 10H*DS ↔ 10000
[BX] ↔ +2000 [BX] ↔ +2000
_______
17000H – Effective address [SI] ↔ +3000
________ _______
15000H – Effective address
_______
v. Relative based index:
MOV AX, 5000[BX][SI]
DS : [BX+SI+5000]
10H*DS ↔ 10000
[BX] ↔ +2000
[SI] ↔ +3000
+5000
___________
1A000H – Effective address
___________
6. Memory Segmentation and organization in 8086 Microprocessor
The memory in an 8086 based system is organized as segmented memory. The CPU 8086 is able to

access 1MB of physical memory. The complete 1MB of memory can be divided into 16 segments, each

of 64KB size and is addressed by one of the segment register. The 16-bit contents of the segment

register actually point to the starting location of a particular segment. The address of the segments may

be assigned as 0000H to F000h respectively. To address a specific memory location within a segment,

we need an offset address. The offset address values are from 0000H to FFFFH so that the physical

addresses range from 00000H to FFFFFH.

Physical address is calculated as below:

Ex: Segment address ---------------------------------------------------------1005H

Offset address -----------------------------------------------------------------5555H

Segment address ----------------------1005H --------- 0001 0000 0000 0101

Shifted left by 4 Positions------------------------ 0001 0000 0000 0101 0000

Offset address ------------------------- 5555H --------- 0101 0101 0101 0101

Physical address ---------------------155A5H 0001 0101 0101 1010 0101

Physical address = Segment address * 10H + Offset address.

The main advantages of the segmented memory scheme are as follows:

1. Allows the memory capacity to be 1MB although the actual addresses to be handled are of 16-bit

size.

2. Allows the placing of code, data and stack portions of the same program in different parts (segments)

of memory, for data and code protection.

3. Permits a program and/or its data to be put into different areas of memory each time the program is

executed, i.e., provision for relocation is done.

Overlapping and Non-overlapping Memory segments:

In the overlapping area locations physical address = CS1+IP1 = CS2+IP2. Where ‘+’ indicates the

procedure of physical address formation.

7. Instruction Set of 8086 Microprocessor
The 8086 instructions are categorized into the following main types
(i) Data copy /transfer instructions: These type of instructions are used to transfer data from
source operand to destination operand. All the store, load, move, exchange input and output
instructions belong to this category.
(ii) Arithmetic and Logical instructions: All the instructions performing arithmetic, logical,
increment, decrement, compare and ASCII instructions belong to this category.
(iii) Branch Instructions: These instructions transfer control of execution to the specified address.
All the call, jump, interrupt and return instruction belong to this class.
(iv) Loop instructions: These instructions can be used to implement unconditional and conditional
loops. The LOOP, LOOPNZ , LOOPZ instructions belong to this category.
(v) Machine control instructions: These instructions control the machine status. NOP, HLT,
WAIT and LOCK instructions belong to this class.
(vi) Flag manipulation instructions: All the instructions which directly effect the flag register
come under this group of instructions. Instructions like CLD, STD, CLI, STI etc.., belong to this
category of instructions.
(vii) Shift and Rotate instructions: These instructions involve the bit wise shifting or rotation in
either direction with or without a count in CX.
(viii) String manipulation instructions: These instructions involve various string manipulation
operations like Load, move, scan, compare, store etc..,
8. Write an ALP to perform addition, Subtraction, multiplication, division on given operands,
perform BCD operation for addition & subtraction.

Data Segment
OPR-1 Equ 98H
OPR-2 Equ 49H
SUM DW 01 DUP (00)
DIFF DW 01 DUP (00)
PROD DW 01 DUP (00)
DIV DW 01 DUP (00)
Data Ends
Code Segment
Assume CS: Code, DS: Data
Start: MOV AX,Data
MOV DS,AX
MOV BL,OPR-2
XOR AL,AL
MOV AL,OPR-1
ADD AL,BL
DAA
MOV BYTE_PTR SUM,AL
JNC GO-1
INC [SUM+1]
GO-1: XOR AL,AL
MOV AL,OPR-1
SUB AL,BL
DAS
MOV BYTE_PTR DIFF,AL
JNB GO-2
INC [DIFF+1]
GO-2: XOR AL,AL
MOV AL,OPR-1
MUL BL
MOV WORD_PTR PROD,AX
XOR AX,AX
MOV AL,OPR-1
DIV BL
MOV WORD_PTR DIV,AX
MOV AH,4CH
INT 21H
Code Segment
End Start
9. It is necessary to define a block of data in 8086 assembly language program. The length of the
block is 90,000 bytes. Give the initialization of data segment for the above block of data. It is
necessary to add second element and 68,000th element of the above data. Give the sequence of
instructions to perform the above operation.

Sol: In 8086 the length of each segment is limited to 64KB (65536 bytes). Hence we cannot load
define a continous block of 90,000 bytes. For this purpose we need to define two segments. One
segment holding the first 62536 bytes of data while the other holding remaining 24464 bytes of
data.

Data Segment
Block-1 DB FFFFH DUP (0)
Data Ends
Extra Segment
Block-2 DB 24464H DUP (0)
Extra Ends
Code Segment
Assume CS:Code, DS:Data
Start: MOV AX,Data
MOV DS,AX
MOV AX,Extra
MOV ES,AX
LEA SI,Block-1
LEA DI,Block-2
MOV CX,FFFFH
INITI-1: MOV [SI],CX
INC SI
LOOP INITI-1
MOV CX,5F90H
INITI-2: MOV [DI],CX
INC DI
LOOP INITI-2
LEA SI,Block-1
LEA DI,Block-2
MOV AL,[SI+1]
ADD AL,[DI+2464]
Code Ends
End Start
10. Write an ALP to find no of +ve & -ve numbers from a given series of signed numbers
Data Segment

List DW 1234, 4567, 8976, 1238, 8975,

Count EQU 05h
Data Ends
Code Segment
Assume CS:Code, DS: Data
Start: MOV AX,Data
MOV DS,AX
XOR BX,BX
XOR DX,DX
MOV CL,Count
MOV SI,OFFSET List
AGAIN: MOV AX,[SI]
SHL AX,01H
JC NEG
INC BX
JMP NEXT
NEG: INC DX
NEXT: ADD SI,02H
DEC CL
JNZ AGAIN
MOV AH,4CH
INT 21H
Code Ends
End Start
11. Write an ALP to find no of Even & Odd numbers from a given series of signed numbers

Data Segment
List DW 1234, 4567, 8976, 1238, 8975,
Count EQU 05h
Data Ends
Code Segment
Assume CS:Code, DS: Data
Start: MOV AX,Data
MOV DS,AX
XOR BX,BX
XOR DX,DX
MOV CL,Count
MOV SI,OFFSET List
AGAIN: MOV AX,[SI]
ROR AX,01H
JC ODD
INC BX
JMP NEXT
ODD: INC DX
NEXT: ADD SI,02H
DEC CL
JNZ AGAIN
MOV AH,4CH
INT 21H
Code Ends
End Start

12. Write an ALP to find sum of series of numbers

Data Segment
Count Equ 05H
Num_List DB 01, 02, 03, 04, 05
Result DB (?)
Data Ends
Code Segment
Assume CS:Code, DS:Data
Start: MOV AX,Data
MOV DS,AX
MOV CL,Count
XOR AX,AX
MOV SI.OFFSET NUM_LIST
GO: MOV BX,[SI]
ADD AX,BX
INC SI
DEC CL
JNZ GO
MOV DI,OFFSET RESULT
MOV [DI],AX
MOV AH,4CH
INT 21H
Code Ends
End Start
13. Write an ALP to find largest number from the given list
Data Segment
LIST DB 52, 56, 89, 55, 23
Count DB 05H
Largest DB (?)
Data Ends
Code Segment
Assume CS: Code, DS: Data
Start: MOV AX,Data
MOV DS,AX
MOV CL,Count
MOV SI,OFFSET LIST
MOV AL,[SI]
AGAIN: CMP AL,[SI+1]
JNL NEXT
MOV AL,[SI+1]
NEXT: INC SI
DEC CL
JNZ AGAIN
MOV SI,OFFSET Largest
MOV [SI],AL
MOV AH,4CH
INT 21H
Code Ends
End Start

14. Write an ALP to arrange the given list of numbers in ascending order using bubble sorting
Data Segment
List DB 23, 45, 56, 89, 78
Count EQU 04H
Data Ends
Code Segment
Assume CS:Code, DS:Data
Start: MOV AX,Data
MOV DS,AX
MOV DL,Count-1
AGAIN: MOV CL,DL
MOV SI,OFFSET List
BACK: MOV AL,[SI]
CMP AL,[SI+1]
JL GO
XCHG [SI+1],AL
XCHG [SI],AL
GO: INC SI
LOOP BACK
DEC DL
JNZ AGAIN
MOV AH,4CH
INT 21H
Code Ends
End Start
15. Write an ALP to find weather the given data is even or odd parity, if even parity put DL=00H,
else put DL=01H, Assuming the given data is multi byte

Data Segment
NUM DD 33 44 88 66H
BYTE_COUNT EQU 04H
Data Ends
Code Segment
Assume CS:Code,DS:Data
Start: MOV AX,Data
MOV DS,AX
MOV DH,BYTE_COUNT
XOR AL,AL
MOV CL,00H
MOV SI,OFFSET NUM
NXT-BYTE: MOV AL,[SI]
JP EVEN-PARITY
INC CL
EVEN-PARITY: INC SI
MOV AL,00H
DEC DH
JNZ NXT-BYTE
MOV DL,00H
RCR CL,01H
JNC CLEAR
INC DL
CLEAR: MOV AH,4CH
INT 21H
Code Ends
End Start