Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Computer Architecture
Harimohan Khatri

Control Unit
• Control of the processor
• Hardwired control unit
• Control unit inputs
• Control unit logic
• Microinstruction format
• Microprogrammed control unit
• Micro instructions and its types
• Architecture of micro programmed control unit
• Micro instruction sequencing
• Micro inctruction execution
• Applications of hardwired and micro programmed control unit

BECE - PU 1
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Micro operation execution

• Micro-operations are the functional, or atomic, operations of the
processor.
• In executing a program, operation of a computer consists of a
sequence of instruction cycles, with one machine instruction per
cycle.
• Each instruction cycle is made up of a number of smaller units –
Fetch, Indirect, Execute and Interrupt cycles.
• Each of these cycles involves series of steps, each of which involves
the processor registers. These steps are referred as micro-operations.

Elements of program execution

BECE - PU 2
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Control of the processor

• Defining the functional requirements of the processor is the basis for
the design and implementation of the control unit.
• Three step process leads to a characterization of the control unit:
• Define the basic elements of the processor
• Describe the micro-operations of that the processor performs
• Determine the functions that the control unit must perform to cause the
micro-operations to be performed.
• The execution of program consists of operations involving processor
elements (ALU, registers, data paths, control unit). And these
operations consists of a sequence of micro-operations.

• Such micro-operations may fall into one of the following categories:

• Transfer data from one register to another
• Transfer data from a register ro an external interface(eg, system bus)
• Transfer data from an external interface to a register
• Perform an arithmetic or logical micro-operation, using registers for input and
output.
• All of the micro-operation needed to perform one instruction cycle,
including all of the micro-operations to execute every instruction in
the instruction set.
• So, the control unit performs two basic tasks:
• Sequencing: The controol unit causes the processor to step through a series
of micro-operations in the proper sequence, based on the program being
executed.
• Execution: The contol unit causes each micro-operation to be performed.

BECE - PU 3
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Control Unit
• For control unit to perform its
function, it must have inputs
that allow it to determine the
state of the system and outputs
that allow it to control the
behavior of the system. These
are the external specifications
of the control unit.
• Internally, the control unit
must have the logic required to
perform its sequencing and Figure: Block Diagram of the Control Unit
execution functions.

• The inputs of the control unit are:

• Clock: The control unit causes one micro-operation (or a set of simultaneous
micro-operations) to be performed for each clock pulse. This is sometimes
referred to as the processor cycle time, or the clock cycle time.
• Instruction register: The opcode and addressing mode of the current
instruction are used to determine which micro-operations to perform during
the execute cycle.
• Flags: These are needed by the control unit to determine the status of the
processor and the outcome of previous ALU operations. For example, for the
increment- and- skip- if- zero (ISZ) instruction, the control unit will increment
the PC if the zero flag is set.
• Control signals from control bus: The control bus portion of the system bus
provides signals to the control unit.

BECE - PU 4
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

• The outputs are as follows:

• Control signals within the processor: These are two types:
• Those that cause data to be moved from one register to another, and
• Those that activate specific ALU functions.
• Control signals to control bus: These are also of two types:
• Control signals to memory, and
• Control signals to the I/O modules.
• In general, three types of control signals are used:
• Those that activate an ALU function;
• Those that activate a data path; and
• Those that are signals on the external system bus or other external interface.
• All of these signals are ultimately applied directly as binary inputs to
individual logic gates.

Control unit – Illustration[1]

• Let us consider fetch cycle to see how the control unit maintains control.
• The control unit keeps track of where it is in the instruction cycle. At a given point, it
knows that the fetch cycle is to be performed next.
• The first step is to transfer the contents of the PC to the MAR. The control unit does
this by activating the control signal that opens the gates between the bits of the PC
and the bits of the MAR.
• The next step is to read a word from memory into the MBR and increment the PC.
The control unit does this by sending the following control signals simultaneously:
• A control signal that opens gates, allowing the contents of the MAR onto the address bus;
• A memory read control signal on the control bus;
• A control signal that opens the gates, allowing the contents of the data bus to be stored in the
MBR;
• Control signals to logic that add 1 to the contents of the PC and store the result back to the
PC.

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Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Control unit – Illustration[2]

• Following this, the control unit sends a control signal that opens gates
between the MBR and the IR.
• This completes the fetch cycle except for one thing: The control unit must
decide whether to perform an indirect cycle or an execute cycle next. To
decide this, it examines the IR to see if an indirect memory reference is made.
• The indirect and interrupt cycles work similarly.
• For the execute cycle, the control unit begins by examining the opcode and,
on the basis of that, decides which sequence of micro-operations to perform
for the execute cycle.

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Control signals example[1]

Here is a simple example of
simple processor with a single
accumulator (AC). The data paths
between elements are indicated.
The terminations of control
signals are labeled Ci and
indicated by a circle.
The control unit receives inputs
from the clock, the IR, and flags.
With each clock cycle, the
control unit reads all of its inputs
and emits a set of control signals.
Control signals go to three
separate destinations:
• Data paths
• ALU
• System bus

Figure: Data Paths and Control Signals

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Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Control signals example[2]

CR = Read control signal to system bus.

CW = Write control signal to system bus.

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Internal processor organization

• Using an internal processor bus, above CPU organization can be
rearranged as shown in figure. A single internal bus connects
the ALU and all processor registers.
• Gates and control signals are provided for movement of data
onto and off the bus from each register.
• Additional control signals control data transfer to and from the
system (external) bus and the operation of the ALU.
• Two registers, labeled Y and Z, are needed for the proper
operation of the ALU. When an operation involving two
operands is performed, one can be obtained from the internal
bus, but the other must be obtained from another source.
• Register Y provides temporary storage for the other input.
• The ALU has no internal storage, the output of the ALU cannot be
directly connected to the bus, because this output would feed back to
the input. Register Z provides temporary output storage.

Figure: CPU with Internal Bus

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BECE - PU 7
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Recommened reading
• The Intel 8085 control signals – W. Stalling, Computer Organization
and architecture 10th edition. Page no. 720-727

15

Control unit implementation

• Hardwired Implementation
• Microprogrammed Implementation

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Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Hardwired control unit

• In a hardwired implementation, the control unit is essentially a state
machine circuit. Its input logic signals are transformed into a set of output
logic signals, which are the control signals.
• The control signals are generated by specially designed hardware logical
circuits, in which we can not modify the signal generation method without
physical change of the circuit structure.
• The operation code of an instruction contains the basic data for control
signal generation.
• The instruction decoder constitutes a set of many decoders that decode
different fields of the instruction opcode. As a result, few output lines
going out from the instruction decoder obtains active signal values.

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Hardwired control unit - Decoder

• To simplify the control unit logic,
there should be a unique logic
input for each opcode. This
function can be performed by a
decoder, which takes an encoded
input and produces a single
output. In general, a decoder will
have n binary inputs and 2n
binary outputs. Each of the 2n
different input patterns will
activate a single unique output.

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Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Hardwired control unit

• These output lines are connected to the inputs of the matrix that
generates control signals for executive units of the computer.
• This matrix implements logical combinations of the decoded signals
from the instruction opcode with the outputs from the matrix that
generates signals representing consecutive control unit states and
with signals coming from the outside of the processor, e.g. interrupt
signals.
• The matrices are built in a similar way as a programmable logic arrays.

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Hardwired control unit

Figure: Control Unit with Decoded Inputs

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BECE - PU 10
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Hardwired control unit

• Control signals for an instruction execution have to be generated
during the entire time interval that corresponds to the instruction
execution cycle.
• Following the structure of this cycle, the suitable sequence of internal states
is organized in the control unit.
• A number of signals generated by the control signal generator matrix are sent
back to inputs of the next control state generator matrix.
• This matrix combines these signals with the timing signals, which are
generated by the timing unit based on the rectangular patterns usually
supplied by the quartz generator.

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Hardwired control unit

Instruction register
Opcode | Address field

Rectangular signal
from quarz Instruction
generator decoder

Control
Control
Next control signal for
Timing signal
state other
Unit generation
generator computer
matrix
unit
Flags and External
variables signals

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BECE - PU 11
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Hardwired control unit - Working

• When a new instruction arrives at the control unit, the control units is
in the initial state of new instruction fetching.
• Instruction decoding allows the control unit enters the first state
relating execution of the new instruction, which lasts as long as the
timing signals and other input signals as flags and state information of
the computer remain unaltered.
• A change of any of signals stimulates the change of the control unit state. This
causes a new respective input is generated for the control signal generator
matrix.

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Hardwired control unit - Working

• When an external signal appears, (e.g. an interrupt) the control unit takes
entry into a next control state that is the state concerned with the reaction
to this external signal (e.g. interrupt processing). The values of flags and
state variables of the computer are used to select suitable states for the
instruction execution cycle.
• The last states in the cycle are control states that commence fetching the
next instruction of the program:
• sending the program counter content to the main memory address buffer register
and
• reading the instruction word to the instruction register of computer.
• When the ongoing instruction is the stop instruction that ends program
execution, the control unit enters an operating system state, in which it
waits for a next user directive.

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BECE - PU 12
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Microprogrammed control unit

• The control signals associated with operations are stored in special
memory units inaccessible by the programmer as Control Words.
• Control signals are generated by a program are similar to machine
language programs.
• Micro-programmed control unit is slower in speed because of the
time it takes to fetch microinstructions from the control memory.

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Micro-progammed control - Basic terms

• Control Word : A control word is a word whose individual bits represent
various control signals.
• Micro-routine : A sequence of control words corresponding to the control
sequence of a machine instruction constitutes the micro-routine for that
instruction.
• Micro-instruction : Individual control words in this micro-routine are
referred to as microinstructions.
• Micro-program : A sequence of micro-instructions is called a micro-
program, which is stored in a ROM or RAM called a Control Memory (CM).
• Control Store : the micro-routines for all instructions in the instruction set
of a computer are stored in a special memory called the Control Store.

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BECE - PU 13
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Micro-progammed control
• For any micro-operation, each control line emanating from the
control unit is either on or off. This condition can be represented by a
binary digit for each control line.
• So we could construct a control word in which each bit represents
one control line. Then each micro-operation would be represented by
a different pattern of 1s and 0s in the control word.

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Horizontal micro-programmed control Unit

• Suppose we string together a sequence of control words to represent the
sequence of micro-operations performed by the control unit.
• Next, we must recognize that the sequence of micro-operations is not
fixed. Sometimes we have an indirect cycle; sometimes we do not. So let us
put our control words in a memory, with each word having a unique
address.
• Now add an address field to each control word, indicating the location of
the next control word to be executed if a certain condition is true (e.g., the
indirect bit in a memory-reference instruction is 1).
• Also, add a few bits to specify the condition.
• The result is known as a horizontal microinstruction.

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BECE - PU 14
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Horizontal micro-programmed control Unit

• There is
• one bit for each internal processor control line and
• one bit for each system bus control line.
• a condition field indicating the condition under which there should be a branch, and
• a field with the address of the micro- instruction to be executed next when a branch is taken.
• Such a microinstruction is interpreted as follows:
• To execute this microinstruction, turn on all the control lines indicated by a 1 bit;
• leave off all control lines indicated by a 0 bit.
• The resulting control signals will cause one or more micro-operations to be performed.
• If the condition indicated by the condition bits is false, execute the next micro-
instruction in sequence.
• If the condition indicated by the condition bits is true, the next microinstruction
to be executed is indicated in the address field.

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Horizontal micro-programmed control Unit

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Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Vertical Micro-programmed control Unit

• The control signals are represented in the encoded binary format. For N
control signals- log2(N) bits are required.
• It supports shorter control words.
• It supports easy implementation of new control signals therefore it is more
flexible.
• It allows low degree of parallelism i.e., degree of parallelism is either 0 or
1.
• Requires an additional hardware (decoders) to generate control signals, it
implies it is slower than horizontal microprogrammed.
• It is less flexible than horizontal but more flexible than that of hardwired
control unit.

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Vertical Micro-programmed control Unit

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Computer Architecture - Harimohan Khatri Monday, May 27, 2024

IOF: Inturrept or fetch routine

Figure: Control memory arrangement

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Microprogrammed control – architecture

• The set of microinstructions is stored in the
control memory.
• The control address register contains the
address of the next microinstruction to be read.
• When a microinstruction is read from the
control memory, it is transferred to a control
buffer register.
• Reading a microinstruction from the control
memory is the same as executing that
microinstruction.
• Sequencing unit loads the control address
register and issues a read command.

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BECE - PU 17
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Microprogrammed control – working

• The control unit functions as follows:
• To execute an instruction, the sequencing logic unit issues a READ command
to the control memory.
• The word whose address is specified in the control address register is read
into the control buffer register.
• The content of the control buffer register generates control signals and next-
address information for the sequencing logic unit.
• The sequencing logic unit loads a new address into the control address
register based on the next-address information from the control buffer
register and the ALU flags.
• All this happens during one clock pulse.

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Figure: Functioning of
Microprogrammed Control Unit

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Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Microprogrammed control – working

• At the conclusion of each micro-instruction, the sequencing logic unit
loads a new address into the control address register.
• Depending on the value of the ALU flags and the control buffer
register, one of three decisions is made:
• Get the next instruction: Add 1 to the control address register.
• Jump to a new routine based on a jump microinstruction: Load the address
field of the control buffer register into the control address register.
• Jump to a machine instruction routine: Load the control address register
based on the opcode in the IR.

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Microprogrammed control – working

• The upper decoder translates the opcode of the IR into a control
memory address.
• The lower decoder is used for vertical microinstructions.
• In a horizontal microinstruction every bit in the control field attaches to a
control line.
• Advantages: A hardwired control unit must contain complex logic for
sequencing through the many micro-operations of the instruction
cycle. But the decoders and sequencing logic unit of a
microprogrammed control unit are very simple pieces of logic.
• Disadvantages: it will be somewhat slower than a hardwired unit of
comparable technology.

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BECE - PU 19
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Micro-progammed control – tasks

• The two basic tasks performed by a microprogrammed control unit
are as follows:
• Microinstruction sequencing: Get the next microinstruction from the control
memory.
• Microinstruction execution: Generate the control signals needed to execute
the microinstruction.
• In designing a control unit, these tasks must be considered together,
because both affect the format of the microinstruction and the timing
of the control unit.

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Microprogram sequencing design considerations

• Two concerns are involved in the design of a microinstruction

sequencing technique:
• the size of the microinstruction and the address-generation time
• minimizing the size of the control memory reduces the cost of that component.
• Minimizing the address generation time is a desire to execute microinstructions as fast as
possible.

• In executing a microprogram, the address of the next microinstruction

to be executed is in one of these categories:
• Determined by instruction register
• Next sequential address
• Branch

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BECE - PU 20
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Sequencing techniques
• Based on the current microinstruction, condition flag, and the
contents of the instruction register, a control memory address
must be generated for the next microinstruction.
• We can group them into three general categories:
• Two address field
• Single address field
• Variable address field
• These categories are based on the format of the address
information in the microinstruction.

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Sequencing technique - two address field

• The simplest approach is to provide two address field in each
microinstruction.
• A multiplexer is provided that search as the destination for both the
address plus the instruction register.
• Based on an address selection input, the multiplexer transmit either
the opcode or one of the two address CAR( Control address
register).
• The CAR is subsequently decoded to provide the next micro
instruction address.
• The address selection signals are provided by a branch logic module
whose input consist of flags plus bits from the control portion of
micro-instruction.

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BECE - PU 21
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Sequencing technique - two address field

Two address in microinstruction

are Normal execution and
Branch address, in case of
branch multiplexer selects the
branch address otherwise
normal address is executed.

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Sequencing technique - single address field

• With single address field the option of next address are as
follows:
• address field,
• instruction field,
• next sequential address.
• The address selection signal determines which option is
selected.
• This approach reduces the no. of address filed to one. However
that the address filed often will not be used. Thus, there is some
inefficiency in micro instruction coding scheme.

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BECE - PU 22
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Sequencing technique - single address field

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Sequencing technique - single address field

• Similar to two-address format, the current address in the CAR is fetched and used
to retrieve a microinstruction from control memory.
• The fetched microinstruction has only one address field specifying the next
microinstruction in the normal sequence.
• Branching is handled by separate logic within the control unit:
• This logic analyzes the current instruction, status flags, and potentially the microinstruction
itself.
• Based on the analysis, the control unit decides whether to proceed sequentially or perform a
jump.
• If branching is needed, the control unit overrides the address field in the
microinstruction and uses a separate mechanism to determine the jump target
address. This mechanism might involve dedicated hardware or additional fields
within the microinstruction for specific branching scenarios.
• The final address, either from the microinstruction or determined by the
branching logic, is loaded into the CAR for the next cycle.

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Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Sequencing technique - variable address field

• It provides two entirely different micro instruction format one bit

designed which format being used.
• In one format the remaining bits are used to activate control signal.
• In other format some bits drives the branches logic and remaining
bits provides the address.
• With the 1st format, the next address is either the sequential address
or an address derive from the instruction register.
• With the 2nd format, either conditional or unconditional branch
being specified.

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Sequencing technique - variable address field

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Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Address generation
• Next address derivation can be divided into
• Explicit techniques, in which the address is explicitly available in the
microinstruction, and
• Implicit techniques, which require additional logic to generate the address.

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Address generation
• We essentially deal with the explicit techniques. With a two-field approach,
two alternative addresses are available with each microinstruction.
• Using either a single address field or a variable format, various branch
instructions can be implemented.
• Several implicit techniques are also commonly used. One of these,
mapping, is required with virtually all designs. The opcode portion of a
machine instruction must be mapped into a microinstruction address. This
occurs only once per instruction cycle.
• A common implicit technique is one that involves combining or adding two
portions of an address to form the complete address.
• Residual control approach involves the use of a microinstruction address
that has previously been saved in temporary storage within the control
unit.

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BECE - PU 25
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Microinstruction encoding
• In practice, microprogrammed control units are not designed using a
pure unencoded or horizontal microinstruction format.
• At least some degree of encoding is used to reduce control memory
width and to simplify the task of microprogramming.
• Microinstruction encoding is done in two approaches:
• Direct encoding
• Indirect encoding

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Microinstruction encoding - Direct

• The microinstruction is organized as a set of fields. Each field contains
a code, which, upon decoding, activates one or more control signals.
• When the microinstruction is executed, every field is decoded and
generates control signals.
• Thus, with N fields, N simultaneous actions are specified. Each action
results in the activation of one or more control signals.
• Considering the individual field. A field consisting of L bits can
contain one of 2L codes, each of which can be encoded to a different
control signal pattern. Because only one code can appear in a field at
a time, the codes are mutually exclusive, and, therefore, the actions
they cause are mutually exclusive.

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BECE - PU 26
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Microinstruction encoding - Direct

• The design of an encoded microinstruction format can now be stated in
simple terms:
• Organize the format into independent fields. That is, each field depicts a set of
actions (pattern of control signals) such that actions from different fields can occur
simultaneously.
• Define each field such that the alternative actions that can be specified by the field
are mutually exclusive. That is, only one of the actions specified for a given field
could occur at a time.
• Two approaches can be taken for organizing the encoded microinstruction
into fields: functional and resource.
• The functional encoding method identifies functions within the machine and
designates fields by function type. For example, if various sources can be used for
transferring data to the accumulator, one field can be designated for this purpose,
with each code specifying a different source.
• Resource encoding views the machine as consisting of a set of independent
resources and devotes one field to each (e.g., I/O, memory, ALU).

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Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Microinstruction encoding - Indirect

• With indirect encoding, one field is used to determine the
interpretation of another field.
• For example, consider an ALU that is capable of performing eight
different arithmetic operations and eight different shift operations.
• A 1-bit field could be used to indicate whether a shift or arithmetic operation
is to be used;
• a 3-bit field would indicate the operation.
• This technique generally implies two levels of decoding, increasing
propagation delays.

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Microinstruction encoding - Indirect

3 bits indicate the type of

operation, the next 3 encode
the operation, and the final 2
select an internal register.

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BECE - PU 28
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Microinstruction execution
• The micro-instruction is the basic event on the micro programmed
processor. Each cycle is made up of two parts: fetch & execute.
• The fetch portion is determined by the generation of micro
instruction address. The effect of execution of a micro-instruction is
to generate control signals.
• Some of these signals control point interval to the processor. The
remaining signals go to the external control bus or other external
interface.
• As an incidental function, the address of next microinstruction is
determined.

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Microinstruction execution
• The sequencing logic module contains the logic to perform functions.
• It generates address of next micro instruction, using as inputs: the
instruction register, ALU flags, the control address register(for
incrementing), and the control buffer register.
• Control buffer register provide an actual address, control bits or both.
• The module is driven by clock that determines the timing of micro
instruction cycle.
• The control logic module generates control signals as a function of some of
the bits in the micro instruction.
• The format and content of micro instruction determines complexity of
control logic module.

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Computer Architecture - Harimohan Khatri Monday, May 27, 2024

Applications of hardwired control unit

• High-Performance Systems: Hardwired control units are preferred in
systems requiring high performance and speed, such as gaming
consoles, high-frequency trading systems, and certain embedded
systems where execution speed is critical.
• Embedded Systems: In embedded systems where the instruction set
is fixed and simple, a hardwired control unit can provide efficient and
quick control.
• Real-time Systems: Systems needing deterministic and fast response
times often utilize hardwired control units due to their faster
operation compared to microprogrammed control units.

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Applications of microprogrammed control unit

• Complex Instruction Set Computers (CISC): Systems with complex

instruction sets, like many desktop and server CPUs, often use
microprogrammed control units to handle intricate operations.
• Adaptable and Upgradable Systems: Systems that might require
future updates or changes in the instruction set, such as some server
processors and programmable hardware, benefit from the flexibility
of microprogrammed control units.
• Prototyping and Development: For the development of new
architectures where instructions might frequently change,
microprogrammed control units offer an easier modification path.

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BECE - PU 30
Computer Architecture - Harimohan Khatri Monday, May 27, 2024

END OF CHAPTER - 04
References:
§ Computer Organization and Architecture – William Stallings
§ Compiled lecture notes from Pokhara University Constituent/Affiliated colleges.
§ Different internet sources for diagrams and figures.

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BECE - PU 31