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4-Cache Key Formula One Pager

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25 views4 pages

4-Cache Key Formula One Pager

asdsadaqw dsa das dwed da d ad ahe llo wskmlodkm

Uploaded by

mhasan
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Cache Key Formula and Concepts:

1. For direct mapped cache:

a) # of Byte Select bits (or also called # of Byte Offset bits) = log2M,
where M is the number of Bytes per cache line (or cache sets).
The Byte Select bits (or Byte Offset bits) are the least significant log2M address bits.

b) # of Index bits (or also called # of Set bits) = log2N,


where N is the total # of cache lines (or cache sets).
The Index bits (or Set bits) is the next least significant log2N address bits.

N = # of cache sets (or total # of cache lines) = cache capacity/cache line capacity

c) # of Tag bits = total Memory Address bits – # of Index bits - # of Byte Select bits

2. For N-Way Set Associative cache:

a) # of Byte Select bits (or also called # of Byte Offset bits) = log2M,
where M is the number of Bytes per cache line (or cache sets).
The Byte Select bits (or Byte Offset bits) are the least significant log2M address bits.

b) # of set (or # of index) = total cache capacity/capacity per set


# of set bits (or # of index bits) = log 2(# of set)

For example, for a 2-way set associative cache, the total cache capacity is 4 cache lines, and
each cache line has 2 Bytes, then
# of set = 4 lines/ (2 lines/set) = 2 sets
# of set bits = log 2 2 = 1

c) # of Tag bits = total Memory Address bits - # of set bits - # of Byte Select bits

3. How to figure out how many LRU bits are needed per Way for a N-way Set Associative cache?
# of LRU bits per Way = log2N
# of LRU bits for a N-way Set Associative cache = N x log2N
4. How to figure out how much storage is required to implement the tag array for a 256KB, 4-way set
associative cache using 64-byte lines and LRU replacement policy implemented using counters.
Addresses are 32 bits.

Steps to Solve Such Problem: Tag array refers to not just the tags (address tags) but also all other
bookkeeping bits such as LRU bits, Valid bit and Dirty bit.

256KB x 1 lines/64bytes x 1 set/4 lines = 218/(26 x 22) = 218/28 = 210 = 1K sets


Therefore 10 bits of the address are used for index

Since the cache uses 64-byte lines, so log264 = 6, therefore there are 6 bits for Byte Select

# of Tag bits = 32 – 10 – 6 = 16 bits per Way


16 bits/Way x 4 Ways/Set = 64 bits/Set

LRU bits requires 2 bits/line (for 4-way Set Associative cache, log24 = 2 bits per line)
LRU bits: 2 bits/line x 4 lines/Set = 8 bits/Set

Valid bit: need 1 Valid bit per line x 4 lines/Set = 4 bits/Set

Dirty bit: need 1 Dirty bit per line x 4 lines/Set = 4 bits/Set

Therefore:

Total Tag storage bits


= # of Tag bits + LRU bits + Valid bits + Dirty bits
= 64 bits/Set + 8 bits/Set + 4 bits/Set + 4 bits/Set
= 80 bits/Set
= 10 Bytes/Set

10 Bytes/Set x 1K Set = 10KB

Total storage required to implement the tag array for this cache is 10KB (Kilo Bytes).

5. For the cache in 4. above, to reduce thrashing, we could consider making the cache a 8-way set
associative cache (double the way per set) while keeping the overall size of the data portion of the
cache the same. How much more (or less) storage is now needed? Aside from the increased
storage, what other resources that would require a larger die are necessary?

256KB x 1 line/64 bytes x 1 set/8 lines = 218/(26 x 23) = 218/29 = 29 = 512 sets
Therefore 9 bits of address are used for index

64 bytes per line: log264 = 6, therefore there are 6 bits for Byte Select
# of Tag bits = 32 – 9 – 6 = 17 bits per Way
17 bits/Way x 8 Ways/Set = 136 bits/Set

LRU bits requires 3 bits/line (for 8-way Set Associative cache, log28 = 3 bits per line)
LRU bits: 3 bits/line x 8 lines/Set = 24 bits/Set

Valid bit: need 1 Valid bit per line x 8 lines/Set = 8 bits/Set

Dirty bit: need 1 Dirty bit per line x 8 lines/Set = 8 bits/Set

Total Tag storage bits


= # of Tag bits + LRU bits + Valid bits + Dirty bits
= 136 bits/Set + 24 bits/Set + 8 bits/Set + 8 bits/Set
= 176 bits/Set

176bits/Set x 512 Set = 90112 bits = 11264 Bytes


= 11264 Bytes/ (1024 Bytes/KB) = 11 KB

Therefore the total storage (or total space) required to implement the tag array for this cache is
now 11 KB, that is an increase of 1 KB from the design in 4 above which was 10KB.

Aside from the increased storage, we now require 8 comparators because it is now 8-way set
associative cache. The design from problem 4 above only require 4 comparators since that was a
4-way set associative cache.

6. As an alternative to doubling the associativity in 5. above, we consider adding a 16 entry, fully


associative victim cache using true LRU replacement policy implemented with counters. How
much more space is required by the victim cache (including both data and tag array) than the
original design in 4. What other resources are needed?

A fully associative cache of 16 lines would require:


32-6 = 26 tag bits/line,
4 LRU bits/line (log216 = 4)
1 valid bit/line
1 dirty bit/line
Total: 26 tag bits/line + 4 LRU bits/line + 1 valid bit/line + 1 dirty bit/line = 32 bits/line
32 bits/line x 16 lines = 64 Bytes for the tag array
AND 16 x 64 bytes for the data array
64 Bytes for the tag array + 16 x 64 Bytes for the data array = 1088 Bytes = 1.0625 KB
So 1.0625KB more space is required than the original design by adding the 16 entry, fully
associative victim cache.

We now require 16 comparators since we use the 16 entry, fully associative victim cache (just as
with the 16-way set associative cache).
7. If a cache is using MESI protocol, how many MESI bits are required per cache line?
# of MESI bits per cache line = log24 since MESI has 4 states: M for Modified, E for Exclusive,
S for Shared, I for Invalid.

8. Average Memory Access Time (AMAT) = (Hit Rate x Hit Time) + (Miss Rate x Miss Time)
(See Lecture slides “4-Caches-with Notes.pptx” page 33).

If there are 2 level of caches: L1 and L2, then AMAT is:

Average Memory Access Time (AMAT)


= (HitRateL1 x HitTimeL1) + MissRateL1 x (MissTimeL1)
= (HitRateL1 x HitTimeL1) + MissRateL1 x [HitRateL2 x HitTimeL2 + MissRateL2 x MissTimeL2]
(See lecture slide “4-Caches-with Notes.pptx” page 49).

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