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Hardware programming using C++

Article in Microprocessing and Microprogramming · December 1994

DOI: 10.1016/0165-6074(94)90047-7 · Source: dx.doi.org

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 Microprocessing
and
Microprogramming
ELSEVIER Microprocessing and Microprogramming 40 (1994) 817-820

Hardware Programming Using C++

E. P. Mariatos a, P. Merakos a, M. K. Birbas b, A. N. Birbas c

a VLSI Design Lab. University of Patras, 26110 GREECE

tel. +30 61 997 324 email: "[email protected]"

b SYNERGY SYSTEMS ltd., Patras, GREECE

c Applied Electronics Lab. University of Patras, GREECE

The use of a programming language for describing hardware is proposed in this paper. The presented
approach, based on minor extensions of C++, gives an attractive way to program computers with reconfigurable
hardware elements (i.e. FPGAs). It can also be used as a common implementation-level language for hardware-
software codesign frameworks.
The proposed approach differs from other codesign methodologies due to the use of a single, object oriented,
notation for all design levels; from the most abstract OMT notations, where the system's functionality and
requirements are first captured, to the detailed implementation-level C++ code.

1. I N T R O D U C T I O N language, the use of the most widespread

programming tool (C++) is adopted. Only a few
Automated CAD tools and the introduction extensions, that need not be new keywords, have to
of a formal language (VHDL [10]) for hardware be added. The use of C++ was decided for two key
description, have offered the hardware designer the reasons; first, a large number of programmers
ability to control the complexity by designing at already know the language and wouldn't move
higher abstraction level. On the other hand, CASE easily to an entirely new notation, and second, due
tools and Object Oriented Techniques have given a to the Object Oriented capabilities of C++. Indeed,
significant boost to Software development. there are many proposals to use objects for
However, in order to continue this progress, we hardware modelling and especially for the
cannot longer separate the machines from the conceptual phase of system design [4][5] [6].
programs they run. Several Hardware/Software The first section of the paper deals with the
codesign techniques [1][2][3][12] have already been introduction of the target architectures that can be
developed and used in the design of embedded supported by the proposed language. A system
systems. They usually start from an abstract, architecture's model is introduced that seems to
conceptual description, introduce specifications for cover a wide range of possible system structures.
cost and performance and then partition the system This model is largely based on reconfigurable
into software and hardware parts. From that point hardware elements (FPGAs [7]) that combine the
on, separate tools and languages are used, which performance of specially designed hardware
usually differ from method to method, connected (ASICs) with the flexibility of programmable
only through a simple cosimulation framework. The hardware (iProcessors, DSPs etc.).
result is usually, VHDL code for the hardware and
C code for the software. 2.TARGET A R C H I T E C T U R E S
In this paper we present a new idea in the
field of hardware/software codesign. It is the use of Systems with Hardware and Software parts
one common language for the implementation level can be designed using two alternative
of description. Instead of developing a new methodologies. One is to start from the system's

0165-6074,/94/$07.00 © 1994 - Elsevier Science B.V. All fights reserved.

SSI)I 0165-6074(94)00060-3
818 E.P. Mariatos et al. / Microprocessing and Microprogramming 40 (1994) 817--820

specifications and proceed with refinement steps As it can be seen, a special hardware part
until the system's structure is derived [4][8]. The labelled "programmable interconnections" is used. It
other option, is to decide on a target system opens channels for communication between the
architecture at an early phase, and then try to map reconfigurable hardware components and the other
the required tasks on that architecture [1][2]. chips of the system. This could be a specially
Although the second approach seems restrictive, it designed ASIC (e.g. crossbar switch) or a FPIC
allows for more automation thus shortening the (field programmable interconnections) chip.
design cycle. Furthermore, since the target The proposed model for the target
architecture is flexible enough, it is felt that it acts architecture can be extended or adapted in order to
more as a guideline than as a limitation to the cover many different system configurations. For
designer's creativity. example, ASICs performing specific tasks could be
In this paper we propose such a target model used instead of/ or in addition to FPGAs, the
for the system's structure. Compatibility with this memory and I/O control part could be minimised for
model is a "requirement" for the proposed an embedded control application e.t.c.
extensions of the C++ language. However, the
language could also cover other architectures, or 3. EXTENDED C++ L A N G U A G E
variations derived from the one presented here.
The proposed architecture is based on the This section presents the proposed C++
standard Microprocessor Bus Memory/IO extensions. An illustrative overview of the
structure, since this scheme has been used for more programming procedure that has to be used with
than three decades and has proven efficient, this language is shown in figure 2.
expandable and has created a basis of existing Starting from a Top-Level description in
experience among programmers. A separate module some graphical notation (like O.M.T [9]), the
for the reconfigurable hardware components is programmer can then move to writing the C++
added. Each FPGA can be viewed by the soft-ware code. A gross decision about the partitioning in
as either a "Fast" function or as a component of a software and hardware has to be made at this step.
larger hardware system. In this way, direct The C++ code can be used for functional
communication with the microprocessor can be simulation, where hardware components will be
assured and also, independence of the emulated in software. The next phase is to compile
reconfigurable parts can be allowed, if required. the software into executable code. The hardware
Figure 1 shows the proposed architecture. components can be translated to a synthesisable
format (e.g. Register Transfer level VHDL) before
being compiled on the FPGAs. Alternatively, ASICs
can be generated from this final synthesisable
MEMORYANDI/0 CONTROL
description of the hardware.
The tools that have to be developed for this

.•.Programable
design procedure are a pre-processor, that partitions
C++ into software and hardware based on simple
principles such as "as-much-hardware-as-can-fit",
MicroProcesso and the Translator to VHDL. Prototypes for both
~ mterconnections tools have been developed. The pre-processor, at
this phase, also generates a hardware emulation
routine in the executable C++ code. The translator is
currently a part of a larger VHDL translation system
--1
ExpansionBus
Figure l.Target Architecture Model
that has been built. Integration of these tools in a
unified framework is planned in the near future.
 E.P. Mariatos et al. / Microprocessing and Microprogramming 40 (1994) 817-820 819

as instances of these classes. Hierarchy is supported

1J
DesignF"~ ExtendedC++ by simply including sub-components in the
Original declaration of higher-level hardware classes. The
component class has all the required member
ExecutableCode functions for construction and connection.
O.M.T. I[ ) ~ I Prlrocessing~._f
for Emulation Functions that represent processes which run
in the component, are also member functions.
Macros are used to declare a function as a process
[ ~ ( Hardware 1 and to define it's sensitivity list. This sensitivity list,
contains all the signals whose change can trigger
the execution of the process. During emulations, a
special part of the C++ code undertakes the
Translation "parallel" execution of all processes and the signal
update procedure. The timing-scheme used is very
similar to that of VHDL'87 simulators, with the
SynthesisableV~L repeated "Execute Processes - Update Signals -
Advance Time" loop.
Figure 2: The Proposed Design Procedure The presented extension of the C++ language
is currently limited for hardware description at a
The extension to the language was built register transfer level and higher abstraction is not
following some objectives. A short list of these yet supported. Signal types have to be easily
objectives were: mapped on wires and buses, and a strict clock-based
timing scheme is imposed. However, integration of
• Standard C++ compatibility existing high-level-synthesis techniques [11][12] is
a straightforward procedure and may be part of a
• View Hardware and Software in a manner more advanced "pre-processor" tool.
compatible with the OMT notations
4. CONCLUSIONS
• Easy translation of hardware to synthesisable
VHDL A simple extension of the C++ programming
language to support description of hardware has
• Support for executable code generation been presented. The proposed language, acts as a
link between higher level design notations and
• As few new concepts and keywords as possible implementation specific details. Aided by tools for
partitioning and translating, it can be used to
To achieve those goals, a class library to program reconfigurable computer architectures
support hardware description has been developed. without loosing the strength and portability of
The main classes are "Component" and "Signal". A standard C++.
special "Interface" component class is also declared Further improvement can be accomplished
that handles communication between software and by developing more clever pre-processors and
hardware. Figure 3 (on the next page) presents a hardware compilers, towards an integrated
diagram of the hardware class library. Hardware/Software CoProgramming Framework.
All components in a hardware description are
coded as classes derived from "Hard Component".
Instances of components in the circuit are described
 820 E.P. Mariatos et al. / Microproces~ing and Microprogramming 40 (1994) 817-820

!
SIGNAL

COMPONENT Name, ID
Connect through PORT
Contain
Waveform
Name, ID List of
Sched. Events
Signals, I/O
Construct
Assign Connect
Destruct
Read (val/wav) Disconnect
Initialize
Event(Change..)

I l I I
INTERFACE •HARD" Comp. BIT

Port S t a t e m e n t Port Statement Type Type III Type

Interf.Variable Internal Signals (Structure) structur/iJ ] ture
Components
Read V a r i a b l e J
BUS , Other I
Write Variable
Type
(Structure)

Figure 3: Class Diagram for the Hardware Description Library

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Mentor Graphics 1993.
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