EE247

Lecture 24
• Interleaved ADCs

• Oversampled ADCs
– Why oversampling?
– Pulse-count modulation
– Sigma-delta modulation
• 1-Bit quantization
• Quantization error (noise) spectrum
• SQNR analysis
• Limit cycle oscillations
EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 1

Summary Last Lecture

Pipelined ADCs (continued)
– Effect gain stage, sub-DAC non-idealities on
overall ADC performance
• Digital calibration (continued)
• Correction for inter-stage gain nonlinearity

– Implementation
• Practical circuits
• Combining the digital bits
• Stage implementation
– Circuits
– Noise budgeting
EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 2
 Time Interleaved Converters
• Example:
– 4 ADCs operating in parallel at 4fs fs
sampling frequency fs VIN
– Each ADC converts on one of T/H ADC
the 4 possible clock phases
fs+Ts/4

Output Combiner
– Overall sampling frequency= 4fs

Digital Output
– Note T/H has to operate at 4fs! ADC

• Extremely fast: fs+2Ts/4

Typically, limited by speed of T/H ADC

• Accuracy limited by mismatch fs+3Ts/4

among individual ADCs (timing, ADC
offset, gain, …)

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 3

Oversampled ADCs

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 4

 Analog-to-Digital Converters
• Two categories:
– Nyquist rate ADCs Æ fsigmax ~ 0.5xfsampling
• Maximum achievable signal bandwidth higher compared
to oversampled type
• Resolution limited to max. 12-14bits

– Oversampled ADCs Æ fsigmax << 0.5xfsampling

• Maximum possible signal bandwidth lower compared to
nyquist
• Maximum achievable resolution high (18 to 20bits!)

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 5

The Case for Oversampling

Nyquist sampling:
Signal fs

“narrow” “Nyquist” DSP

transition fs >2B + δ ADC
B Freq AA-Filter Sampler

Oversampling: fs >> fN??

Signal

“wide” Oversampled
DSP
transition fs = M fN ADC

B Freq AA-Filter Sampler

• Nyquist rate fN = 2B
• Oversampling rate M = fs/fN >> 1

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 6

 Nyquist v.s. Oversampled Converters
Antialiasing
|X(f)| Input Signal

fB frequency

Nyquist Sampling

fB fs 2fs frequency
fS ~2fB
Anti-aliasing Filter
Oversampling

fB fs frequency
fS >> 2fB

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 7

Oversampling Benefits
• No stringent requirements imposed on analog
building blocks
• Takes advantage of the availability of low
cost, low power digital filtering
• Relaxed transition band requirements for
analog anti-aliasing filters
• Reduced baseband quantization noise power
• Allows trading speed for resolution

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 8

 ADC Converters
Baseband Noise
• For a quantizer with step size Δ and sampling rate fs :
– Quantization noise power distributed uniformly across Nyquist
bandwidth ( fs/2)
Ne(f)

NB

-fs /2 -fB fB f s /2

– Power spectral density:

e2 ⎛ Δ2 ⎞ 1
N e( f ) = =⎜ ⎟
fs ⎝ 1 2 ⎠ fs

– Noise is distributed over the Nyquist band –fs /2 to fs /2

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 9

Oversampled Converters
Baseband Noise
fB fB
⎛ Δ2 ⎞ 1
SB = ∫ N e( f )d f = ∫ ⎜ ⎟ df
−f B −f B ⎝ 1 2 ⎠ fs Ne(f)
2⎛
Δ 2 fB ⎞
= ⎜⎜ ⎟ NB
12 ⎝ f s ⎟⎠

wh e re for f B = f s / 2
Δ2
SB0 = -fs /2 -fB fB f s /2
12
⎛2f ⎞ S
SB = SB0 ⎜ B ⎟ = B0
⎜ f ⎟ M
⎝ s ⎠
f
whe re M = s = ov e rsampling ratio
2 fB

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 10

 Oversampled Converters
Baseband Noise
⎛2f ⎞ S
SB = SB0 ⎜ B ⎟ = B0
⎜ f ⎟ M
⎝ s ⎠
f
whe re M = s = ov e rsampling ratio
2 fB
2X increase in M
Æ 3dB reduction in SB
Æ ½ bit increase in resolution/octave oversampling

To increase the improvement in resolution:

ƒ Embed quantizer in a feedback loop
ÆNoise shaping (sigma delta modulation)

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 11

Pulse-Count Modulation

Nyquist
Vin(kT)
ADC
0 1 2
t/T

Oversampled
Vin(kT)
ADC, M = 8
0 1 2 t/T

Mean of pulse-count signal approximates analog input!

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 12

 Pulse-Count Spectrum
Magnitude

• Signal: low frequencies, f < B << fs

• Quantization error: high frequency, B … fs / 2
• Separate with low-pass filter!

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 13

Oversampled ADC
Predictive Coding

+ 1-bit Digital
vIN ADC Filter
_ DOUT N-bit

Predictor

• Quantize the difference signal rather than the signal itself

• Smaller input to ADC Æ Buy dynamic range
• Only works if combined with oversampling
• 1-Bit digital output
• Digital filter computes “average” ÆN-bit output

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 14

 Oversampled ADC
f =Mf f = f +δ
s1 N s2 N
Signal
E.g. Decimator
“wide” Pulse-Count “narrow” DSP
transition f =Mf Modulator
s N transition
Analog Sampler Modulator Digital
AA-Filter AA-Filter
B Freq
1-Bit Digital N-Bit
Digital

Decimator:
• Digital (low-pass) filter
• Removes quantization error for f > B
• Provides anti-alias filtering for DSP
• Narrow transition band, high-order
• 1-Bit input, N-Bit output (essentially computes “average”)

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 15

Modulator (AFE)

• Objectives:
– Convert analog input to 1-Bit pulse density stream
– Move quantization error to high frequencies f >>B
– Operates at high frequency fs >> fN
• M = 8 … 256 (typical)….1024
• Since modulator operated at high frequencies Æ need to
keep circuitry “simple”

Æ ΣΔ = ΔΣ Modulator

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 16

 Sigma- Delta Modulators

Analog 1-Bit ΣΔ modulators convert a continuous time

analog input vIN into a 1-Bit sequence DOUT
fs
+
VIN H(z)
_ DOUT

DAC

Loop filter 1b Quantizer (comparator)

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 17

Sigma-Delta Modulators
• The loop filter H can be either switched-capacitor or continuous time
• Switched-capacitor filters are “easier” to implement + frequency
characteristics scale with clock rate
• Continuous time filters provide anti-aliasing protection

fs
+
VIN H(z)
_
DOUT

DAC

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 18

 Oversampling A/D Conversion
fs fs /M

Input Signal Bandwidth Oversampling Decimation n-bit

1-bit
Modulator
B=fs /2M (AFE) @ fs Filter @ fs /M

fs = sampling rate
M= oversampling ratio

• Analog front-end Æ oversampled noise-shaping modulator

• Converts original signal to a 1-bit digital output at the high rate of
(2BXM)
• Digital back-end Æ digital filter (decimation)
• Removes out-of-band quantization noise
• Provides anti-aliasing to allow re-sampling @ lower sampling rate

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 19

1st Order ΣΔ Modulator

1st order modulator, simplest loop filter Æ an integrator
z-1
H(z) =
1 – z-1
+
VIN
_ ∫ DOUT

DAC

Note: Non-linear system with memory Æ difficult to

analyze
EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 20
 1st Order ΣΔ Modulator
Switched-capacitor implementation

φ1 φ2 φ2
-
1,0
+
VIN DOUT

+Δ/2

-Δ/2

– Full-scale input range Æ Δ

– Note that Δ here is different from Nyquist rate ADC Δ (1LSB)

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 21

1st Order ΔΣ Modulator

+
VIN
_
∫
-Δ/2≤VIN≤+Δ/2 DOUT

-Δ/2 or +Δ/2
DAC
• Properties of the 1st order modulator:
– Maximum analog input range is equal to the DAC reference
– The average value of DOUT must equal the average value of VIN
– +1’s (or –1’s) density in DOUT is an inherently monotonic function of VIN
Æ To 1st order, linearity is not dependent on component matching
– Alternative multi-bit DAC (and ADCs) solutions reduce the quantization
error but loose this inherent monotonicity & relaxed matching
requirements

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 22

 1st Order ΣΔ Modulator
Tally of 1-Bit
quantization error quantizer
Analog input 1 2 3
-Δ/2≤Vin≤+Δ/2 X Q Y

z-1
-1
1-z 1-Bit digital
Sine Wave Integrator Comparator
output stream,
-1, +1

Instantaneous Implicit 1-Bit DAC

quantization error +Δ/2, -Δ/2
(Δ = 2)

• M chosen to be 8 (low) to ease observability

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 23

1st Order Modulator Signals

1st Order Sigma-Delta X analog input
1.5 X
Q
Q tally of q-error
Y Y digital/DAC output
1
Amplitude

0.5
Mean of Y approximates X
0 That is exactly what the
digital filter does
-0.5

-1
T = 1/fs = 1/ (M fN)
-1.5
0 10 20 30 40 50 60
Time [ t/T ]

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 24

 ΣΔ Modulator Characteristics
• Inherently linear for 1-Bit DAC
• Quantization noise and thermal noise (KT/C) distributed
over –fs /2 to +fs /2
ÆTotal noise within signal bandwidth reduced by 1/M
Æ Required capacitor sizes x1/M compared to nyquist rate ADCs

• Very high SQNR achievable (> 20 Bits!)

• To first order, quantization error independent of
component matching
• Limited to moderate & low speed

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 25

1st Order ΣΔ Modulator

Output Spectrum
• Quantization noise
30 definitely not white!
Input
Amplitude [ dBWN ]

20
• Skewed towards higher
10 frequencies
0
• Notice the distinct tones
-10

-20

-30 • dBWN (dB White Noise)

-40 scale sets the 0dB line
at the noise per bin of a
-50
0 0.1 0.2 0.3 0.4 0.5 random -1, +1
Frequency [ f /fs] sequence

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 26

 Quantization Noise Analysis
Quantization
Error e(kT)
Integrator

z −1
x(kT) Σ H( z ) =
1 − z −1
Σ y(kT)
Quantizer
Model

• Sigma-Delta modulators are nonlinear systems with memory Æ difficult to

analyze directly

• Representing the quantizer as an additive noise source linearizes the

system

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 27

Signal Transfer Function

x(kT)
z −1 Σ Integrator y(kT)
H ( z) = - H(z)
1 − z −1
ω0
H ( jω ) =
jω

Signal transfer function

Æ low pass function:
Magnitude

1
H Sig ( jω ) =
1+ s
ω0
Y ( z) H ( z) f0 Frequency
H Sig ( z ) = = = z −1 ⇒ Delay
X ( z) 1 + H ( z)

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 28

 Noise Transfer Function
Qualitative Analysis
2
vn
vi ω0 vo 2
Σ veq
- jω
2
veq = vn2 × ⎛⎜ f ⎞⎟
⎝ f0 ⎠
2
v n2 × ⎛⎜ f ⎞
⎟
⎝ f0 ⎠
vi ω0 vo
Σ
- jω

f0 Frequency
2
2
veq = vn2 × ⎛⎜ f ⎞⎟
⎝ f0 ⎠
ω0 vo • Input referred-noiseÆ zero @
Σ DC (s-plane)
vi - jω

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 29

1st Order ΣΔ Modulator

STF and NTF
Quantization
Integrator Error e(kT)

z −1
x(kT) Σ H( z ) = Σ y(kT)
1 − z −1
Quantizer
Model

Signal transfer function:

Y ( z) H ( z)
STF = = = z −1 ⇒ Delay
X ( z) 1 + H ( z)

Noise transfer function:

Y ( z) 1
NTF = = = 1 − z −1 ⇒ Differentiator
E ( z) 1 + H ( z)

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 30

 Noise Transfer Function
Y ( z) 1
NTF = = = 1 − z −1 set z = e jωT
E( z) 1 + H ( z)
⎛ e jωT / 2 − e− jωT / 2 ⎞
NTF ( jω ) = (1 − e− jωT )=2e− jωT / 2 ⎜ ⎟
⎜
⎝
2 ⎟
⎠
= 2e− jωT / 2 j sin (ωT / 2 )
= 2e− jωT / 2 × e− jπ / 2 ⎡sin (ωT / 2 )⎤
⎣ ⎦

= ⎡ 2sin (ωT / 2) ⎤ e− j (ωT −π ) / 2

⎣ ⎦
where T = 1/ f s
Thus:
NTF ( f ) =2 sin (ωT / 2 ) =2 sin (π f / f s )

2
Output noise power spectrum: N y ( f ) = NTF ( f ) Ne ( f )

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 31

First Order ΣΔ Modulator

Noise Transfer Characteristics
Noise Shaping Function

2
Low-pass N y ( f ) = NTF ( f ) ⋅ N e ( f )
Digital 2
Filter = 4 sin (π f / f s ) ⋅ N e ( f )

First-Order Noise Shaping

frequency

fB fN fs /2

Key Point:
Most of quantization noise pushed out of frequency band of interest

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 32

 Quantizer Error
• For quantizers with many bits

Δ2
e 2 (kT ) =
12

• Let’s use the same expression for the 1-bit case

• Use simulation to verify validity

• Experience: Often sufficiently accurate to be useful,

with enough exceptions to be careful

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 33

First Order ΣΔ Modulator

Simulated Noise Transfer Characteristic
Simulated output spectrum
Computed NTF
20 Signal • Confirms
assumption of
Amplitude [ dBWN ]

10
quantization
0 noise being white
at insertion point
-10
• Linearized model
-20 seems to be
N y ( f ) = 4 sin (π f / f s )
2 accurate
-30

-40

0 0.1 0.2 0.3 0.4 0.5

Frequency [f /fs]

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 34

 First Order ΣΔ Modulator
In-Band Quantization Noise

NTF ( z ) = 1 − z − 1
2 2
NTF ( f ) = 4 sin (π f / f s ) for M >> 1
B
2
SY = ∫ SQ ( f ) NTF ( z ) df
z = e 2 π jfT
−B

fs
2M
1 Δ2 2
≅ ∫ f s 12
( 2 sin π fT ) df
− fs
2M

π 2 1 Δ2
→ SQ ≈ Total in-band quantization noise
3 M 3 12

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 35

1st Order ΣΔ
Dynamic Range
⎡ full-scale signal power ⎤ ⎡S ⎤
DR = 10log ⎢ ⎥ = 10log ⎢ X ⎥
⎣ inband noise power ⎦ ⎢⎣ SQ ⎥⎦
2
1⎛Δ⎞
SX = ⎜ ⎟ sinusoidal input, STF = 1
2⎝ 2 ⎠
M DR
π 2 1 Δ2
SQ = 16 33 dB
3 M 3 12 32 42 dB
SX 9 1024 87 dB
= M3
SQ 2π 2
⎡ 9 ⎤ ⎡ 9 ⎤
DR = 10log ⎢ 2 M 3 ⎥ = 10log ⎢ 2 ⎥ + 30log M
⎣ 2π ⎦ ⎣ 2π ⎦

DR = −3.4dB + 30log M
2X increase in MÎ9dB (1.5-Bit) increase in dynamic range
EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 36
Oversampling and Noise Shaping
• ΣΔ modulators have interesting characteristics
– Unity gain for input signal VIN
– Significant attenuation of in-band quantization noise injected at
quantizer input
– Performance significantly better than 1-bit noise quantizer
performance possible for frequencies << fs
• Increase in oversampling (M = fs /fN >> 1) improves SQNR
considerably
– 1st order ΣΔ: DR increases 9dB for each doubling of M
– To first order, SQNR independent of circuit complexity and accuracy
• Analysis assumes that the quantizer noise is “white”
– Not entirely true in practice, especially for low-order modulators
– Practical modulators suffer from other noise sources also
(e.g. thermal noise)

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 37

1st Order ΣΔ Modulator

Response to DC Input
• Matlab & Simulink model used
• Input Æ DC at 1/11 full-scale level

1 2 3
X Q Y

z-1
-1
1-z
DC Input=1/11 FS Integrator Comparator

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 38

 1st Order ΣΔ
Response to DC Input
• DC input A = 1/11
DC
20
Amplitude [ dBWN ]

Component • Output spectrum shows

DC component plus
0 distinct tones!!

• Tones frequency shaped

-20 the same as quantization
noise
-40 Æ More prominent at
higher frequencies
0 0.1 0.2 0.3 0.4 0.5
Frequency [ f /fs ] Æ Seems like periodic
quantization “noise”

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 39

Limit Cycle Oscillation

DC input 1/11 Æ
Periodic sequence:
First order sigma-delta, DC input
1 +1
0.4 2 +1
3 -1
0.2
4 +1
Output

0 5 -1
6 +1
-0.2
7 -1
-0.4 8 +1
9 -1
0 10 20 30 40 50 10 +1
Time [t/T] 11 -1
Æ Average =1/11

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 40

 1st Order ΣΔ
Limit Cycle Oscillation
In-band spurious tone
with f ~ DC input level

Amplitude First-Order Noise Shaping

fB fN Frequency fs /2
• Problem: quantization noise becomes periodic in response to low level DC inputs &
could fall within passband of interest!
• Solution:
¾ Use dithering (inject noise-like signal at the input ): randomizes quantization noise
- If circuit thermal noise is large enoughÆ acts as dither
¾ Second order loop

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 41

1st Order ΣΔ Modulator

Linearized Model Analysis

(
Y ( z ) = z −1 X ( z ) + 1 − z −1 E ( z ))
LPF HPF

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 42

 2nd Order ΣΔ Modulator

• Two integrators in series

• Single quantizer (typically 1-bit)
• Feedback from output to both integrators
• Tones less prominent compared to 1st order

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 43

2nd Order ΣΔ Modulator

Linearized Model Analysis

Recursive drivation: Yn = X n −1 + ( E n − 2 E n −1 + E n − 2 )

( )
2
Using the delay operator z −1 : Y ( z ) = z −1 X ( z ) + 1 − z −1 E (z)
LPF HPF

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 44

 2nd Order ΣΔ Modulator
In-Band Quantization Noise

( )
2
NTF ( z ) = 1 − z −1
2
NTF ( f ) =
4
= 2 sin (π f / f s )
4
for M >> 1
B
2
SQ = ∫ SQ ( f ) NTF ( z ) z = e 2 π jfT df
−B
fs
2M
1 Δ2
≅ ∫ ( 2 sin π fT )4 df
− fs f s 12
2M

π 4 1 Δ2
≈
5 M 5 12

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 45

Quantization Noise
2nd Order ΣΔ Modulator vs 1st Order Modulator

Ideal 2nd -Order Noise Shaping

Noise Shaping Function

Low-pass
Digital
Filter

1st Order Noise Shaping

π 2 1 Δ2
SQ ≈
3 M 3 12

π 4 1 Δ2 fB Frequency fs /2
SQ ≈
5 M 5 12

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 46

 2nd Order ΣΔ Modulator
Dynamic Range
⎡ full-scale signal power ⎤ ⎡ SX ⎤
DR = 10log ⎢ ⎥ = 10log ⎢ S ⎥
⎣ inband noise power ⎦ ⎣⎢ Q ⎦⎥
2
1⎛Δ⎞
SX = ⎜ ⎟ sinusoidal input, STF = 1
2⎝ 2 ⎠
π 4 1 Δ2
SQ =
5 M 5 12
SX 15
= M5
SQ 2π 4
⎡ 15 ⎤ ⎡ 15 ⎤
DR = 10log ⎢ 4 M 5 ⎥ = 10log ⎢ 4 ⎥ + 50log M
⎣ 2π ⎦ ⎣ 2π ⎦

DR = −11.1dB + 50log M
2X increase in MÎ15dB (2.5-bit) increase in DR
EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 47

2nd Order vs 1st Order ΣΔ Modulator

Dynamic Range

M 2nd Order 1st Order Resolution

D.R. D.R. (2nd order - 1st order)
16 49 dB (7.8bit) 33dB (5.2bit) 2.6 bit

32 64 dB (10.3bit) 42dB (6.7bit) 3.6 bit

256 109 dB (17.9bit) 68.8dB (11.1bit) 6.8 bit

1024 139 dB (22.8bit) 87dB (14.2bit) 8.6 bit

– Note: For higher oversampling ratios resolution of 2nd order modulator

significantly higher compared to 1st order

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 48

 2nd Order ΣΔ Modulator
Example
• Digital audio application
9 Signal bandwidth 20kHz
9 Desired resolution 16-bit

16 − bit → 98 dB Dynamic Range

DR 2 nd order ΣΔ = -11.1dB + 50 log M
M min = 153
M Æ 256=28 two reasons:
1. Allow some margin so that thermal noise dominate &
provides dithering
2. Choice of M power of 2 Æ ease of digital filter
implementation

Æ Sampling rate (2x20kHz + 5kHz)M = 12MHz (quite reasonable!)

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 49

Limit Cycle Tones in 1st Order & 2nd Order ΣΔ Modulator

• Higher
oversampling ratio
Æ lower tones
6dB 1st Order ΣΔ Modulator

• 2nd order tones

much lower
compared to 1st

• 2X increase in M 12dB 2nd Order ΣΔ Modulator

decreases the
tones by 6dB for
1st order loop and
12dB for 2nd order Inband Quantization noise
loop

Ref: B. P. Brandt, et al., "Second-order sigma-delta modulation for digital-audio signal

acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618 - 627, April 1991.
R. Gray, “Spectral analysis of quantization noise in a single-loop sigma–delta modulator
with dc input,” IEEE Trans. Commun., vol. 37, pp. 588–599, June 1989.

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 50

 ΣΔ Implementation
Practical Design Considerations
• Internal node scaling & clipping

• Effect of finite opamp gain & linearity

• KT/C noise

• Opamp noise

• Effect of comparator nonidealities

• Power dissipation considerations

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 51

Switched-Capacitor Implementation 2nd Order ΣΔ

Nodes Scaled for Maximum Dynamic Range

• Modification (gain of ½ in front of integrators) reduce & optimize required

signal range at the integrator outputs ~ 1.7x input full-scale (Δ)
• Note: Non-idealities associated with 2nd integrator and quantizer when
referred to the ΣΔ input is attenuated by 1st integrator high gain
Æ The only building block requiring low-noise and high accuracy is the
1st integrator
Ref: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,”
IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1298-1308, Dec. 1988.

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 52

 2nd Order ΣΔ Modulator
Example: Switched-Capacitor Implementation

VIN Dout

• Fully differential front-end

• Two bottom-plate integrators
• 1-bit DAC is made of switches and Vrefs

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 53

Switched-Capacitor Implementation 2nd Order ΣΔ

Phase 1

VIN Dout

During phase 1:
• 1st integrator samples Vin on 1st stage C1
• 2nd integrator samples output of 1st integrator
• Comparator senses polarity of 2nd intg. output Æ result
saved in output latch
• S3 opens prior to S1 Æ minimize effect of charge injection

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 54

 Switched-Capacitor Implementation 2nd Order ΣΔ
Phase 2

VIN Dout

• Input sampled during φ1 transferred to C2 Æ

integration
• Note: S2 connects integrator inputs to + or – Vref,
polarity depends on whether Dout is 0 or 1

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 55

2nd Order ΣΔ Modulator

Switched-Capacitor Implementation

• The ½ loss in front of each integrator

implemented by choice of:

C2=2C1 Æ f0intg=fs /(4π)

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 56

 Design Phase Simulations
• Design of oversampled ADCs requires simulation of extremely long data
traces
• SPICE type simulators:
– Normally used to test for gross circuit errors only
– Too slow for detailed performance verification
• Typically, behavioral modeling is used in MATLAB-like environments
• Circuit non-idealities either computed or found by using SPICE at
subcircuit level
• Non-idealities introduced in the behavioral model one-by-one first to
fully understand the effect of each individually
• Next step is to add as many of the non-idealities simultaneously as
possible to verify whether there are interaction among non-idealities

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 57

2nd Order ΣΔ
Effect of 1st Integrator Maximum Signal Handling Capability on SNR

M=256
– Behavioral model
– Non-idealities
tested one by one

1st integrator maximum signal handling:

1.4, 1.5,1.6, and 1.7X Δ

• Effect of 1st Integrator maximum signal handling capability on converter SNR

Æ No SNR loss for max. sig. handling >1.7Δ
Ref: B.E. Boser et. al, “The Design of Sigma-Delta Modulation A/D Converters,” JSSC, Dec. 1988.

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 58

 2nd Order ΣΔ
Effect of 2nd Integrator Maximum Signal Handling Capability on SNR

2nd integrator maximum signal handling:

0.75,1,1.25, 1.5, and 1.7X Δ

• Effect of 2nd Integrator maximum signal handling capability on SNR

Æ Νο SNR loss for max. sig. handling >1.7 Δ
Ref: B.E. Boser et. al, “The Design of Sigma-Delta Modulation A/D Converters,” JSSC, Dec. 1988.

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 59

2nd Order ΣΔ
Effect of Integrator Finite DC Gain

Integrator
CI
φ1 φ2 H ( z )ideal =
Cs
×
z −1
CI 1 − z −1
- ⎛ ⎞
Cs
a ⎜ a ⎟ −1
⎜ z
+
Vo Cs ⎟
Vi ⎜1+ a + ⎟
Cs
H ( z ) Finit DC Gain = × ⎝ CI ⎠
CI ⎛ ⎞
⎜ 1 + a ⎟ −1
aÆ opamp gain at DC 1− ⎜
Cs ⎟
z
⎜1+ a + ⎟
⎝ CI ⎠
→ H ( DC ) = a

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 60

 2nd Order ΣΔ
Effect of Integrator Finite DC Gain
l o g H (s) eQ + DOUT
Ideal Integ. (a=infinite)
_
a
H (ω )

ω0
ω0 ∫
P1 =
a
Integrator magnitude response

Dout = 1
• Note: Quantization transfer eQ 1 + H (ω )
function wrt output has
integrator in the feedback → @ D C for ide al inte g: D o ut = 0
eQ
path:
→ @ D C for real integ: D ou t≈1
eQ a

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 61

2nd Order ΣΔ
Effect of Integrator Finite DC Gain
Max signal level

f0 /a

• Low integrator DC gain Æ Increase in total in-band quantization noise

• Can be shown: If a > M (oversampling ratio) Æ Insignificant degradation in
SNR
• Normally DC gain designed to be >> M in order to suppress nonlinearities

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 62

 2nd Order ΣΔ
Effect of Integrator Finite DC Gain

M/a

• Example: a =2M Æ 0.4dB degradation in SNR

a =M Æ 1.4dB degradation in SNR
Ref: B.E. Boser et. al, “The Design of Sigma-Delta Modulation A/D Converters,” JSSC, Dec. 1988.

EECS 247 Lecture 24 Oversampled ADCs © 2008 H.K. Page 63