International Journal of Computer Applications (0975 – 8887)

Volume 11– No.1, December 2010

Implementation of Low Power Scalable Encryption

Algorithm
K.J. Jegadish Kumar S. Salivahanan K. Chenna Kesava Reddy
Assistant Professor Principal Principal
SSN College of Engineering SSN College of Engineering Jyothismathi College of
Kalavakkam-603110 Kalavakkam-603110 Engineering and Technology
Chennai, India Chennai, India Shamirpet-500078, India

ABSTRACT platforms with minimum code change. Most algorithms

perform differently on different platforms but SEA is an
Scalable Encryption algorithm (SEA) is a symmetric block
exception as it allows obtaining a small encryption routine
cipher, especially designed for resources constrain systems. targeted to any given processor, the security of the cipher
SEA proposes low cost encryption routines (i.e. small code being adapted in function of its key size. Since we operate on
size, memory and power), targeted for processors with a a limited resource processor, we only do some basic
limited instruction set. SEA is parametric with text, key and operations (i.e. XOR, AND, OR, mod2b addition).
processor size, and allows efficient combination of
encryption/decryption and key derivation. SEA was initially 1.2 Literature Survey
designed for software implementations in controllers, smart Though there are many cryptographic algorithms, most of
cards, or processors and small embedded applications. In this them require high or moderate processing power, like
Advanced Encryption Standards (AES), Data Encryption
paper, we investigate the performance of SEA in a Field
Standard (DES), Tiny Encryption Algorithm (TEA),
programmable gate array (FPGA) device. For this purpose, Extended TEA (XTEA). But these encryption algorithms
an iterative loop design of the block cipher is implemented cannot be implemented in a resource constrained system due
on FPGA. Beyond its low cost performances, the proposed to various complexities involved like i.e. Non Scalability,
architecture is fully flexible with any parameters and takes Processor Intensive, and Security Level.
advantage of generic VHDL coding. Our efficient modular
AES (Rijndael) [5, 6] comprises three block ciphers, all the
adders implementation achieves lower area, power
block cipher vary depending on the number of bits. AES is a
consumption and considerably higher throughputs on the fixed block cipher of 128 bits with a key size of 128,192,256.
target platform VIRTEX-4, xc4vl25 and SPARTAN-3, AES requires four 256 entry, 32 bit tables, so totally 4096 of
xc3s1400. memory which equals 1kilo byte for each table. AES is more
Keywords: Block ciphers, constrained applications, FPGA processor intensive and is non scalable, so it cannot be
implementation. implemented on constrained systems. Though there are
efficient implementations of AES [7] , there are still non-
1 INTRODUCTION scalable for need of any processing platform.
Resource constrained encryption does not have a long history
in symmetric cryptography. Notable examples of such DES [3] is based on symmetric key algorithms of bit size 56.
ciphers are the Tiny Encryption Algorithm TEA or Yuval's DES is the archetypal block cipher – an algorithm that takes
proposal. However, both of them are relatively old and do a fixed length string of plain text bits and transforms through
not provide provable security against attacks such as linear the series of complicated operations into another cipher bit
and differential cryptanalysis. Present block ciphers, like the string of the same key. DES by itself is not a secure means of
Advanced Encryption Standard Rijndael rather focus on encryption but must instead be used in a mode of operation
finding a good trade-off between cost, security and as suggested by FIPS-81(Federal Information Processing
performance. Hence, there arises a need for a new Standard). DES is more processor intensive, non scalable
cryptosystem that provides suitable solution for resource and is breakable by Linear Cryptanalysis.
constrained systems. Embedded applications such as building
infrastructures present a significant opportunity and TEA [4] is notable for its simplicity and implementable on
challenge for such new cryptosystems. One such new various platforms (scalability) and operates on 64 bit blocks
cryptosystem is Scalable Encryption Algorithm (SEA). and uses 128 bit key. When crypt analyzed with equivalent
key, each key gives three other keys. So in terms of security
TEA is insecure [7]. XTEA was an advanced version of
1.1 SEA: An Overview TEA, mainly aimed at improving all the security glitches.
The purpose for SEA is to implement in limited processing XTEA has complex key scheduling and rearrangement of
resources (e.g. a small processor); the proposed architecture Shift XOR and addition operations. XTEA is vulnerable to
is parametric with respect to plaintext, cipher text, key and related key differential attack. Like SEA, HIGHT [8] is also
the processor size. Since the architecture is parametric in another Block Cipher for resource constrained systems, but
nature, there is flexibility and allows implementing in all its non scalable and consumes more number of gates and the

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 International Journal of Computer Applications (0975 – 8887)
Volume 11– No.1, December 2010

throughput and operating frequency are much less when in C-like notation. For efficiency purposes, it is
compared to SEA (48, 8). So, implementing SEA for applied bitwise to any set of three words of data
constrained systems is a better option. using the following recursive definition:

This paper is organized as follows. The introduction and

literature survey are provided in section 1. Section 2
describes parameters, definitions and basic operations for
implementation of SEA. Section 3 illustrates hardware
implementation strategies. In section 4 implementation
results are presented. Finally, conclusions are made in
section 5.

2. IMPLEMENTATION OF SEA where

Most present symmetric encryption algorithms result from a and respectively represent the bitwise AND
tradeoff between implementation cost and resulting and OR.
performances. In addition, they generally aim to be
implemented efficiently on a large variety of platforms. SEA 3. Word rotation R: The word rotation is defined on
takes an opposite approach and considers a context where we nb-word vectors:
have very limited processing resources and throughput
requirements. It was initially designed as a low-cost
encryption and authentication routine targeted for processors
with a limited instruction set. Additionally and contrary to
most recent block ciphers (e.g. the DES and AES Rijndael),
the algorithm takes the plaintext, key and the bus sizes as 4. Bit rotation r: The bit rotation is defined on nb-
parameters and therefore can be straightforwardly adapted to word vectors:
various implementation contexts and/or security
requirements. Compared to older solutions for low cost
encryption like TEA (Tiny Encryption Algorithm) or Yuval‟s
proposal, SEA also benefits from a stronger security analysis,
derived from recent advances in block cipher ,
design/cryptanalysis [2]. In practice, SEA was proven to be
an efficient solution for embedded software applications
using microcontrollers, but its hardware performances have
not yet been investigated. This paper therefore proposes to Where and represent the cyclic right
investigate the interest of this algorithm for area and power and left shifts inside a word.
in constrained applications. The investigation starts with an
exploration of the features of a low cost FPGA encryption/ 5. Addition mod 2b : The mod 2b addition is defined
decryption core for SEA [1]. on nb-word vectors:

2.2 Algorithmic Description

2.2.1 Basic Operations In this section, we give a complete description of the
algorithm, starting with the important parameters, and then
Due to its simplicity constraints, SEAn,b is based on a limited
emphasizing its basic operation. Afterwards follows the
number of elementary operations (selected for their
round and key round description of SEA is presented [1].
availability in any processing device) denoted as follows: (1)
bitwise XOR , (2) substitution box S, (3) word (left) rotation
R and inverse word rotation R-1, (4) bit rotation r, (5) 2.2.2 Encrypt/Decrypt and Key round
addition mod 2b .
The encrypt round FE, decrypt round FD and key round FK are
1. Bitwise XOR : The bitwise XOR is defined on defined as:
n/2 -bit vectors:
Encryption Round FE :

2. Substitution box S: SEAn,b uses the following 3-bit Decryption Round FD :

substitution table:
ST: = {0; 5; 6; 7; 4; 3; 1; 2},

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 International Journal of Computer Applications (0975 – 8887)
Volume 11– No.1, December 2010

C = Rnr&Lnr ;
switch KLnr−1, KRnr−1;}
Figure 2.2: Pseudo Code description

Since nr is odd, referring the figure 2.2 for key scheduling

and encryption the value of nr must rounded up or down.
Rounding up or ceil is denoted as ⌈⌉ and rounding down or
floor is denoted as ⌊⌋.

2.2.4 Suggested Number of rounds

The minimum required number of rounds to provide security
against known attacks would be nr = [3(n/4) + 2((n/2b )+
b/2)]. This roughly corresponds to the number of rounds to
resist linear/differential attacks plus twice the number of
rounds to obtain complete diffusion (to prevent both
structural attacks and outer rounds improvements of
statistical attacks). The value of nr must be always odd, if not
1 must be added to make it odd.
Figure. 2.1. Encrypt/decrypt round and key round,

Key Scheduling Round FK : 3. HARDWARE IMPLEMENTATION

3.1 Implementation Description
The first investigation step to the hardware implementation
of SEA proposes to take a look at a straightforward
implementation of the algorithm on an FPGA platform,
2.2.3 The Complete Cipher achieving one round per clock cycle and denoted as the loop
implementation. Resource-consuming blocks are the S-boxes
The cipher iterates an odd number nr of rounds. The pseudo
and the mod 2b adder; the Word Rotate and Bit Rotate
code given in Figure 2.2 illustrates the necessary steps to
blocks are implemented by swapping wires. According to the
encrypt a plaintext P under a key K and produce a cipher text
specifications, the key schedule contains two multiplexors
C. P,C and K have a parametric bit size n. The operations
allowing switching the right and left part of the round key at
within the cipher are performed considering parametric b-bit
half the execution of the algorithm, using the appropriate
words. In this pseudo code, the „&‟ relates to the
command signal Swap. The multiplexor controlled by Switch
concatenation operator, KR nr/2 is taken before the switch
provides the round function with the right part of the round
and C(i) is a nb-word vector of which all the words have
key for the first half of the execution and transmits its left
value 0 excepted the LSB that equals i. Decryption is exactly
part instead after the switch. The Generic Loop Architecture
the same, using the decrypt round FD.
is simple and only changes in the location of the R and R-1
Block. The number of rounds nr is an optional input that can
C=SEAn,b(P,K)
be automatically derived from n and b. In this paper , we
{
% initialization: mainly focused to propose a light weight Modular adders in
consider of low power optimization at the synthesizable
L0&R0 = P;
VHDL design level.
KL0&KR0 = K;
% key scheduling:
for i in 1 to ⌊nr/2 ⌋ 3.2 Implementation of efficient Modular
[KLi,KRi] = FK(KLi−1,KRi−1,C(i)); adders
The modulo m addition of two numbers x and y belonging to
switch KL⌊ nr/2 ⌋, KR⌊ nr/2 ⌋;
{0, . . .,m − 1} is defined by:
for i in ⌈nr/2 ⌉ to nr − 1
(x + y) mod m = x + y if x +y < m, and -----(3.1)
[KLi,KRi] = FK(KLi−1,KRi−1,C(r − i));
= x + y − m if x + y ≥ m,
% encryption:
and can be straightforwardly implemented by an adder, a
for i in 1 to ⌈nr/2 ⌉ comparator, and a subtractor. The comparison is however
[Li,Ri] = FE(Li−1,Ri−1,KRi−1); expensive, both in terms of area and delay. The algorithms
studied in this section allow to get rid of it and lead to more
for i in ⌈nr/2 ⌉ + 1 to nr
efficient hardware operators. In this paper, k = [log2 m]+1
[Li,Ri] = FE(Li−1,Ri−1,KLi−1); denotes the number of bits which are required to encode both
% final: inputs and output of a modulo m arithmetic operator. There

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 International Journal of Computer Applications (0975 – 8887)
Volume 11– No.1, December 2010

are basically three methodologies to carry out a modulo m are also shown in Figure 4.4. Our implementation of SEA
addition [10]: exhibited a very small area utilization that comes at the cost
1. Table based operator method of increased throughput and reduced power consumption.
2. Hybrid based operator method Consequently, it can be considered as the interesting
3. Adder-Based operator method. alternative for constrained devices.

Adder-Based Operators. Implementing Equation (3.1)

and described by Algorithm 1 leads to the circuit of Figure
1c. Reference [10] provides for instance a proof a correctness
of this method. This architecture requires only two carry-
propagate adders and a Multiplexer and is therefore well
suited for FPGAs.

Algorithm 3.1 Modulo m addition.

1: Choose j such that 2j-1 < m < 2j

2: s0 ← x+y
3: s1 ← (s0 mod 2j) + 2j − m
4: if the carry-out bit of s0 or s1 is one then
5: (x + y) mod m ← s1 mod 2j
6: else Figure 4.1
7: (x + y) mod m ← s0 mod 2j
8: end if

The architecture of implemented algorithm 3.1 is portrayed

in figure 3.1. Our proposed modulo addition algorithm leads
to smallest circuits, in turn reduced overall circuit complexity
of SEA.

Figure 4.2

Figure 3.1

4 IMPLEMENTATION RESULTS
Implementation results were extracted with the ISE 9.2i tool
from Xilinx on an device XC4VLX25, VIRTEX-4 platform
with speed grade-12 and XC3S1400, SPARTAN-3 platform
with speed grade -4. XPower Analyzer tool was used to
analyze the power consumption of the implementation. The
implementation was done for variants bit data (n) and a
processor word size (b). We achieved reduction in number
of slice (Figure 4.1), high throughputs (Figure 4.2) and
increase in work frequency (Figure 4.3) in implementation
Figure 4.3
compared to implementation of [1]. Throughput /Area ratio

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 International Journal of Computer Applications (0975 – 8887)
Volume 11– No.1, December 2010

[2] Francois-Xavier Standaert, Gilles Piret, Neil

Gershenfeld, Jean-Jacques Quisquater “SEA a Scalable
Encryption Algorithm for Small Embedded
Applications” in Proc.CARDIS, 2006,pp 222-236.

[3] Data Encryption Standard, FIPS PUB 46-3, Oct. 1999.

[4] D.J. Wheeler, R. Needham, TEA, a Tiny Encryption

Algorithm, in the proceedings of FSE 1994, Lecture
Notes in Computer Science, vol 1008, pp 363-366,
Leuven, Belgium, December 1994, Springer-Verlag.

[5] J. Daemen and V. Rijmen, The Design of Rijndael.

New York: Springer-Verlag, 2001.

Figure 4.4 [6] Advanced Encryption Standard, FIPS PUB 197, Nov.
2001.
5 CONCLUSION
SEA was initially proposed for low cost software [7] G. Yuval, “Reinventing the travois: Encryption/MAC
implementations. While these design criteria turned out to in 30 ROM bytes,” in Proc. Fast Softw. Encryption
allow low cost hardware implementations as well, it is likely
(FSE), 1997, pp. 205–209.
that targeting a cipher specifically for low cost hardware
would lead to even better solutions.
[8] N. Pramstaller and J. Wolkerstorfer, “A universal and
Through the hardware investigation of the SEA, we show efficient AES co-processor for field programmable
that this modular symmetric algorithm, targeted for low- logic arrays,” in Proc. FPL, 2004, pp. 565–574.
resources software solutions, can interestingly respond to
constrained hardware needs. We first demonstrated that the
[9] Francisco Rodriguez-Henriquez,N.A. Saqib,A. Diaz-
scalability of this algorithm can be kept in the hardware
description language(VHDL). The simple iterative loop Perez,Cetin Kaya K09, “Cryptographic Algorithms on
design achieves interesting performance in area and power Reconfigurable Hardware”, Springer Series on Signals
reduction, improvise throughputs in FPGA. In addition we and Communication Technology,2006.
analysed the power consumed by the SEA module for
different variants in data block and word size. [10] Beuchat,J.-L.; Lab. De l'Infonnatique du Parallelisme,
“ Some Modular adders and multipliers for Field
It is also important to emphasize a number of advantages in
programmable Gate arrays”, in Proc. Parallel and
SEA that cannot be found in other recent block ciphers,
namely its simplicity, scalability(re-implementing SEA for a Distributed processing symposium 2003.
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combination of encryption and decryption. [11] J.-L. Beuchat. “Modular Multiplication for FPGA
Implementationof the IDEA Block Cipher”, Technical
6 ACKNOWLEDGEMENT Report 2002-32,Laboratoire de l‟Informatique du
We are grateful to the experts who have contributed towards Parall´elisme, Ecole NormaleSup´erieure de Lyon, 46
development of our work. We acknowledge Shankar Kuhan, All´ee d‟Italie, 69364 LyonCedex 07, Sept. 2002.
Thirumurugan and Praveen V for all their help during the
design phase. [12] J.-L. Beuchat and A. Tisserand. Small Multiplier-
basedMultiplication and Division Operators for Virtex-
II Devices.In M. Glesner, P. Zipf, and M. Renovell,
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