CHAPTER 5

ARITHMETIC
CIRCUITS

Objectives

 Half Adder and Full Adder

 Parallel Adder and Subtractor

 2’s complement number

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5.1 Binary Addition

Binary addition is performed in the same way as decimal addition except that
the values of individual digits can only be 0 or 1. The addition of a one-bit
number has 4 possible combinations as shown below.

When adding a larger numbers that has multiple bits, it is still necessary to
add each pair of bits with a carry-in Cin. For example, A=1101 (13) and
B=0110 (6).

The 1s column is producing the outputs Sum S and Carry Out Cout.
1
The carry out C0 is carried to 2s column as Cin. In the 2s column, we have
producing the outputs S dan C The Co is carried to the 4s
2 out.

column as Cin. In the 4s column, . In the last

column 8s, .

5.2 Half Adder and Full Adder Circuit

The 1s column adds 2 bits and generates 2 outputs S and Co. This is
known as a half adder operation.

The half adder truth table and circuit are shown below.
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The 2s, 4s and 8s columns add 3 bits and generates S and Cout,
which known as a full adder operation.

The full adder truth table and circuit are shown below.
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5.3 Parallel Adder Circuit

To construct a 4 bit parallel adder, a single half adder and three full adder
circuits are used. The top half adder adds the 1s column ( ) and
generates S1 and Co. The 2s, 4s and 8s columns use a full adder. Note that
the carry out Co is connected to the Cin of the next adder.

7483 is a commercial 4-bit full adder. It has four full adders connected as
shown below. To perform a 4 bit addition, the Cin is connected to GND (0).
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An 8-bit parallel adder is constructed using two 7483 ICs. The Cout of the first
IC is connected to the Cin of the preceding IC.

5.4 Signed Numbers

A binary number can be represented as either a positive or a negative value.
The common representation of signed numbers is either in the form of
sign-magnitude or in the form of 2’s complement.

In a sign-magnitude system, a number consists of two parts, the magnitude

and the sign. A 0 signifies a positive number and a 1 signifies a negative
number. An n bit sign-magnitude number could represent integers ranging
n-1 n-1
from –(2 -1) to +(2 -1). A 4 bit sign-magnitude ranges from -7 to +7. Note
that, there two possible representations of zero: -0 and +0. Thus +6 (0110)
and -6 (1110) differ only in the sign bit.

The sign-magnitude representation is not commonly used in practice for

representing integer numbers. It requires arithmetic circuit that are most
costly and slower computation time. The addition and subtraction of
sign-magnitude numbers requires the comparison of signs and magnitude.
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5.5 Two’s Complement Number

The complement number system was invented to make addition and

subtraction faster and easier, by omitting the need for compare sign and
magnitude comparison. Instead it requires complementation which can be
performed quite efficiently on binary numbers.

In 2’s complement number system, a positive number is represented in the

same fashion as in a sign-magnitude number. For example, . A
negative number is represented in its 2’s complement form. For example,
.

An n bit 2’s complement number could represent integers ranging from

to . A four bit 2’s complement number ranges from -8 to +7.
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A negative number in 2’s complement is obtained from a positive number by

complementing each bit including the sign bit and then adding 1 to it. The
carry that occurs out of the MSB is discarded. As an example, the 2s
complement for -6 is illustrated below:

Example 1: Find the 2’s complement number for +30 and -30.

a. The magnitude for +30 is 11110. Attach sign bit = 0

2s complement for + 30 = 011110

b. 2s complement for -30 = 100010

011110
100001
+1
100010
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Example 2: Show how an 8-bit computer would represent a 2’s complement

number for +30 and -30.

a. 2s complement for + 30 using 8 bit = 00011110

b. b. 2s complement for -30 = 11100010

00011110
11100001
+1
11100010

Example 3: Determine the decimal value for the following 2’s complement
number: a. 00100010 b. 10100010 c. 11111111

a. From the sign bit, 00100010 is a positive number. The decimal value is
+34.

b. From the sign bit, 10100010 is a negative number. Complement each bit
and add 1. The decimal value is -94.

c. From the sign bit, 11111111 is a negative number. Complement each bit
and add 1. The decimal value is -1.

The number of bits available in the computer’s arithmetic unit, limits the
range of numbers that can be represented in the machine. Numbers that fall
outside this range cannot be handled by the system. Machines that uses 2’s
complement number system can represent integers in the range

where n is the number of bits available for representing N. If an operation

produces a result that falls outside the available range, than an overflow
occurs.
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Example 1: Determine the range of integers that can be represented in the 2’s
complement number system having n bits:
a. n= 8 bit b. n=16 bit c. n= 32 bit

8-1 8-1
a. - 2 to + 2 -1 : -128 (10000000) to +127 (01111111)
b. - 32,768 to + 32,767
c. – 2,147,483,648 to 2,147,483,647

5.6 Two’s Complement Arithmetic

We will now learn how to add and subtract using 2’s complement system.
Four cases will be considered: A+B, A-B, -A+B and –A-B.

Case 1: A+B Two positive numbers.

Since both A and B are positive, the result will also be positive. So, there is no
need to use the 2’s complement.

Example 1: 2+ 4 = +6

Example 2: 9+4 = +13

There are cases when an operation produces a result that exceeds the range of
the number system, producing a condition known as overflow. When we add
two numbers with the same sign, which produce a sum that is larger than the
largest representable number, we can obtain an incorrect result. As a rule,
addition overflow occurs whenever the sign of the sum is different from the
signs of both addends.
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Example 1: 6+3=-7

The result 1001 is interpreted as -7. The sign bit shows that it is a negative
number. The correct answer is +9, which is outside the 4-bit 2’s complement
range [-8,+7]. Hence an overflow condition has occurred. The sum of the two
given numbers requires more than the allotted 4 bits to represent it.

Example 2: 12+7 = -13

The result 10011 is interpreted as -13. The correct answer is +19, which is
outside the 5-bit 2’s complement range [-16,+15]. The sum of the two given
numbers requires more than the allotted 5 bits to represent it.

Example 3: Compute 6+3 using 5 bits.

The range for a 5-bit 2’s complement is [-16,+15]. Since the sign bit is 0, it
correctly represents the desired answer which is interpreted as +9.

Example 4: Compute 12+7 using 6 bits.

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The range for a 6-bit 2’s complement is [+32,-31]. Since the sign bit is 0, it
correctly represents the desired answer which is interpreted as +19.

Example 5: Compute 19+27 using 2’s complement system.

The sum is +46 which requires at least 7 bits, where the range for a 7-bit 2’s
complement is [-64,+63].

Case 2: -A-B Two negative numbers.

Both –A and –B will be represented by the 2’s complement and the

computation will be performed as (-A) + (-B).

Example 1: -3-2 = -5

Adding two negative numbers will generate a negative sum as indicated by the
1 sign bit. We ignore the carry beyond the sign bit. Therefore, the result is
1011 = -5.

Example 2: -12-5
The sum is -17 which requires 6 bits. The range for a 6-bit 2’s complement is
[-32,+31].

The result is 101111 = -17.

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Suppose we use 5 bits to compute -12-5, the answer is 01111 = +15. Note that
the sign bit (0) is incorrect, indicating an overflow. The desired result (-17)
exceeds the number range for a 5-bit 2’s complement [-16,+15].

Case 3: A-B

The positive number A is unchanged, however B is represented in 2’s

complement form.

Example 1: 3-2 = 1

Add the two numbers. Ignore the carry beyond the sign bit. The result is 0001
= +1.

Example 2: 12-5

The answer is 00111 = +7.

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Example 3: 5-12

The answer is 11001 = -7.

Case 4: -A+B

Add the two numbers. Ignore the carry beyond the sign bit. The result is 1111
= -1.

5.7 Subtractor Circuit

The 4-bit parallel adder can be modified slightly to form a subtractor circuit.
Subtraction S= A-B in the 2’s complement number system is performed as
follows:

The 2’s complement for B is obtained by complementing each bit and then
adding 1 to the LSB.
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A 4-bit subtractor circuit is shown below. The 2’s complement is formed by

the inverters on the B input and adding Cin = 1 to the LSB. The MSB (A4, B4
and S4) is used for the sign bit and the C4 output is not used.

The diagram shown below is a 4-bit subtractor circuit using a 7483 adder and
NOT gates.

This circuit can only accept values between -7 (1001) and +7 (0111), and the
result is also limited to values between -7 to +7. Some arithmetic operation
can result in an overflow condition if the output result is beyond the range of
valid numbers.

Example 1: 7-1=6
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Example 2: 7-0=7

An 8-bit subtractor circuit is constructed by connecting two 4-bit subtractor

circuit. The output of C4 is connected to the Cin of the preceding subtractor.
This circuit can compute values between -127 to +127.

This circuit can accept values between -127 (10000001) and +127
(01111111), and the result is also limited to values between -127 to +127.

Example 1: 127-0=127
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Example 2: 7-1=6

5.8 Adder-Subtractor Circuit

The 4-bit adder and subtractor circuits are almost identical. These circuits
can be combined to form an adder-subtractor circuit. The circuit has an
additional input called the control input. If the control input is 0, the circuit
performs addition, , where Cin=0. If the control input is 1, the
circuit performs subtraction , where Cin=1.
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From the truth table, we can write the expression as:

The 4 bit adder-subtractor circuit is shown below. When the control input is
1, the input Cin=1 and the XOR gate will act as inverter to perform
subtraction. When the control input is 0, the input Cin=0 and the XOR gate
has no effect on B.
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5.9 Exercises

1. Convert the following two’s complement numbers to a decimal number:

a) 10100111
b) 10000111
c) 10110010
d) 11011001
e) 10101010

2. Convert the following two’s complement numbers to a hexadecimal

number:
a) 11010101
b) 10010110
c) 11000011
d) 11110010
e) 11110100

3. Convert the following decimal number to two’s complement number:

a) -1410
b) -2710
c) -11110
d) -6010
e) -5310

4. Subtract the following numbers using two’s complement number system:

a) 710 - 310
b) 4010 - 1110
c) 610 - 1310
d) 8710 - 10010
e) 2010 - 1510

5. Subtract the following numbers using 8 bits two’s complement number

system:
a) 510 – 1010
b) 2510 – 1410
c) 1210 – 2010
d) 3110 – 1810
e) 8510 – 6510

6. Draw the 4 bit adder-subtractor circuit to show how the following

arithmetics work:
a) 510 – 210
b) 310 + 410
c) 410 – 610
d) 110 + 310
e) 710 – 510