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System-Programming Paging

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33 views

System-Programming Paging

Uploaded by

tom.liu.961213
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Virtualizing Memory:

Paging
Problem:
Fragmentation
Definition: Free memory that can’t be usefully allocated
Why?
• Free memory (hole) is too small and scattered
• Rules for allocating memory prohibit using this free space

Types of fragmentation
• External: Visible to allocator (e.g., OS)
• Internal: Visible to requester (e.g., if must allocate at some granularity)

Segment A Allocated to requester


External useful
Segment B
free Internal
Segment E

Segment C No contiguous space!

Segment D
Paging
Goal: Eliminate requirement that address space is contiguous
• Eliminate external fragmentation
• Grow segments as needed

Idea: Divide address spaces and physical memory into fixed-sized pages
• Size: 2n, Example: 4KB
• Physical page: page frame

Physical View
Process 1 Process 3
Process 2
Logical View
Translation of
Page Addresses
• How to translate logical address to physical address?
• High-order bits of address designate page number
• Low-order bits of address designate offset within page

20 bits 12 bits 32 bits

page number page offset Logical address

translate

frame number page offset Physical address

No addition needed; just append bits correctly…


How does format of address space determine number of pages and size of pages?
Quiz: Address Format
Given known page size, how many bits are needed in address to specify offset in page?

Page Size Low Bits (offset)

16 bytes 4
1 KB 10
1 MB 20
512 bytes 9
4 KB 12
Quiz: Address Format
Given number of bits in virtual address and bits for offset,
how many bits for virtual page number?

Page Size Low Bits Virt Addr Bits High Bits


(offset) (vpn)

16 bytes 4 10 6
1 KB 10 20 10
1 MB 20 32 12
512 bytes 9 16 5 7

4 KB 12 32 20

Correct?
Quiz: Address Format
Given number of bits for vpn, how many virtual pages can there be in an address space?

Page Size Low Bits Virt Addr Bits High Bits Virt Pages
(offset) (vpn)

16 bytes 4 10 6 64
1 KB 10 20 10 1K
1 MB 20 32 12 4K
512 bytes 9 16 5 32
4 KB 12 32 20 1 MB
VirtUAL => Physical PAGE
Mapping
VPN offset
Number of bits in 0 1 0 1 0 1
virtual address
format does not
need to equal Addr Mapper
number of bits in
physical address
format
1 0 1 1 0 1 0 1

PPN offset
How should OS translate VPN to PPN?

For segmentation, OS used a formula (e.g., phys addr = virt_offset + base_reg)

For paging, OS needs more general mapping mechanism

What data structure is good? Big array: pagetable


The Mapping

P1 P2 P3
Virt Mem

Phys Mem
Quiz:
Fill in Page Table
P1 P2 P3
Virt Mem

Phys Mem
0 1 2 3 4 5 6 7 8 9 10 11

P1 P2 P3
3 0 8
1 4 5
Page Tables: 7 2 9
10 6 11
Where Are Pagetables
Stored?
How big is a typical page table?
- assume 32-bit address space
- assume 4 KB pages
- assume 4 byte entries

Final answer: 2 ^ (32 - log(4KB)) * 4 = 4 MB


• Page table size = Num entries * size of each entry
• Num entries = num virtual pages = 2^(bits for vpn)
• Bits for vpn = 32– number of bits for page offset
= 32 – lg(4KB) = 32 – 12 = 20
• Num entries = 2^20 = 1 MB
• Page table size = Num entries * 4 bytes = 4 MB

Implication: Store each page table in memory


• Hardware finds page table base with register (e.g., CR3 on x86)

What happens on a context-switch?


• Change contents of page table base register to newly scheduled process
• Save old page table base register in PCB of descheduled process
Other PT info
What other info is in pagetable entries besides translation?
• valid bit
• protection bits
• present bit (needed later)
• reference bit (needed later)
• dirty bit (needed later)

Pagetable entries are just bits stored in memory


• Agreement between hw and OS about interpretation
Memory Accesses
with Pages
0x0010: movl 0x1100, %edi Old: How many mem refs with segmentation?
0x0013: addl $0x3, %edi
5 (3 instrs, 2 movl)
0x0019: movl %edi, 0x1100
Physical Memory Accesses with Paging?
Assume PT is at phys addr 0x5000 1) Fetch instruction at logical addr 0x0010;
Assume PTE’s are 4 bytes vpn?
Assume 4KB pages • Access page table to get ppn for vpn 0
How many bits for offset? 12 • Mem ref 1: 0x5000
• Learn vpn 0 is at ppn 2
Simplified view
• Fetch instruction at 0x2010 (Mem ref 2)
of page table
Exec, load from logical addr 0x1100; vpn?
2
• Access page table to get ppn for vpn 1
0
• Mem ref 3: 0x5004
80
• Learn vpn 1 is at ppn 0
99
• Movl from 0x0100 into reg (Mem ref 4)
Pagetable is slow!!! Doubles memory references
Advantages of
Paging
No external fragmentation
• Any page can be placed in any frame in physical memory

Fast to allocate and free


• Alloc: No searching for suitable free space
• Free: Doesn’t have to coallesce with adjacent free space
• Just use bitmap to show free/allocated page frames

Simple to swap-out portions of memory to disk (later lecture)


• Page size matches disk block size
• Can run process when some pages are on disk
• Add “present” bit to PTE
Disadvantages of
Paging
Internal fragmentation: Page size may not match size needed by process
• Wasted memory grows with larger pages
• Tension?
Additional memory reference to page table --> Very inefficient
• Page table must be stored in memory
• MMU stores only base address of page table
• Solution: Add TLBs (future lecture)
Code
Storage for page tables may be substantial
• Simple page table: Requires PTE for all pages in address space Heap
• Entry needed even if page not allocated
• Problematic with dynamic stack and heap within address space
• Page tables must be allocated contiguously in memory
• Solution: Combine paging and segmentation (future lecture)
Stack

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