Microcomputer:

- Generally stands for personal computer, or a computer that depends on a

microprocessor.
- Designed to be used by individuals, whether in the form of PCs, workstations or
notebook computers.
- Contains a CPU on a microchip (the microprocessor), a memory system (typically
ROM and RAM), a bus system and I/O ports, typically housed in a motherboard.

Microprocessor:
- Digital electronic component with transistors fabricated on a single semiconductor
integrated circuit (IC).
- One or more microprocessors typically serve as a central processing unit (CPU) in a
computer system or handheld device.
- Also controls the logic of almost all digital devices, from clock radios to fuel-
injection systems for automobiles.

Three basic characteristics differentiate microprocessors:

- Instruction set: The set of instructions that the microprocessor can execute.
- Bandwidth: The number of bits processed in a single instruction.
-Clock speed: Given in megahertz (MHz), the clock speed determines how many
instructions per second the processor can execute.
- Example, higher the value of clock speed, the more powerful the CPU. A 32 bit
microprocessor that runs at 50MHz is more powerful than a 16-bit microprocessor that
runs at 25MHz.
In addition to bandwidth and clock speed, microprocessors are classified as being either RISC
(reduced instruction set computer) or CISC (complex instruction set computer).

Supercomputer:
- Fastest speed computer.
- Typically used for scientific and engineering applications that must handle very large
databases or do a great amount of computation.
- Most supercomputers are really multiple computers that perform parallel processing.
- In general, there are two parallel processing approaches: symmetric multiprocessing
(SMP) and massively parallel processing (MPP).
-
Microcontroller:
- A highly integrated chip that contains all the components comprising a controller.
- Typically includes a CPU, RAM, some form of ROM, I/O ports, and timers.
- Unlike a general-purpose computer, which also includes all of these components, a
microcontroller is designed for a very specific task - to control a particular system.
- A microcontroller differs from a microprocessor, which is a general-purpose chip that
is used to create a multi-function computer or device and requires multiple chips to
handle various tasks.
 - A microcontroller is meant to be more self-contained and independent, and functions
as a tiny, dedicated computer.
- They are typically designed using CMOS (complementary metal oxide
semiconductor) technology, an efficient fabrication technique that uses less power
and is more immune to power spikes than other techniques.
- Microcontrollers are sometimes called embedded microcontrollers, which just means
that they are part of an embedded system that is, one part of a larger device or system.

Controller:
- A device that controls the transfer of data from a computer to a peripheral device and
vice versa.
- For example, disk drives, display screens, keyboards and printers all require
controllers.
- In personal computers, the controllers are often single chips.
- When we purchase a computer, it comes with all the necessary controllers for
standard components, such as the display screen, keyboard, and disk drives.
- If we attach additional devices, however, we may need to insert new controllers that
come on expansion boards.
- Controllers must be designed to communicate with the computer's expansion bus.
- There are three standard bus architectures for PCs - the AT bus, PCI (Peripheral
Component Interconnect ) and SCSI.
- When we purchase a controller, therefore, we must ensure that it conforms to the bus
architecture that computer uses.

Evolution of Microprocessors

We can categorize the microprocessor according to the generations or according to the size of the
microprocessor:

First Generation (4 - bit Microprocessors)

The first generation microprocessors were introduced in the year 1971-1972 by Intel
Corporation. It was named Intel 4004 since it was a 4-bit processor.

It was a processor on a single chip. It could perform simple arithmetic and logical operations
such as addition, subtraction, Boolean OR and Boolean AND.

It had a control unit capable of performing control functions like fetching an instruction from
storage memory, decoding it, and then generating control pulses to execute it.

Second Generation (8 - bit Microprocessor)

The second generation microprocessors were introduced in 1973 again by Intel. It was a first 8 -
bit microprocessor which could perform arithmetic and logic operations on 8-bit words. It was
Intel 8008, and another improved version was Intel 8088.

Third Generation (16 - bit Microprocessor)

The third generation microprocessors, introduced in 1978 were represented by Intel's 8086,
Zilog Z800 and 80286, which were 16 - bit processors with a performance like minicomputers.

Fourth Generation (32 - bit Microprocessors)

Several different companies introduced the 32-bit microprocessors, but the most popular one is
the Intel 80386.

Fifth Generation (64 - bit Microprocessors)

From 1995 to now we are in the fifth generation. After 80856, Intel came out with a new
processor namely Pentium processor followed by Pentium Pro CPU, which allows multiple
CPUs in a single system to achieve multiprocessing.

Other improved 64-bit processors are Celeron, Dual, Quad, Octa Core processors .
8085 Microprocessor

- It is 8 bit microprocessor.
- It is manufactured with N-MOS technology.
- It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB)
memory locations through A0-A15.
- The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 – AD7.
- Data bus is a group of 8 lines D0 – D7.
- It supports external interrupt request.
- It has 16 bit program counter (PC)
- It has 16 bit stack pointer (SP)
- It has six 8-bit general purpose register arranged in pairs: BC, DE, HL.
- It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock.
- It is enclosed with 40 pins DIP (Dual in line package).

Memory
- Program, data and stack memories occupy the same memory space. The total
addressable memory size is 64 KB.
- Program memory - program can be located anywhere in memory. Jump, branch and
call instructions use 16-bit addresses, i.e. they can be used to jump/branch anywhere
within 64 KB. All jump/branch instructions use absolute addressing.
- Data memory - the processor always uses 16-bit addresses so that data can be placed
anywhere.
- Stack memory is limited only by the size of memory. Stack grows downward.
- First 64 bytes in a zero memory page should be reserved for vectors used by RST
instructions.

Interrupts
- The processor has 5 interrupts. They are presented below in the order of their priority
(from lowest to highest):
- INTR is maskable 8080A compatible interrupt. When the interrupt occurs the
processor fetches from the bus one instruction, usually one of these instructions:
- One of the 8 RST instructions (RST0 - RST7). The processor saves current program
counter into stack and branches to memory location N * 8 (where N is a 3-bit number
from 0 to 7 supplied with the RST instruction).
- CALL instruction (3 byte instruction). The processor calls the subroutine, address of
which is specified in the second and third bytes of the instruction.
- RST5.5 is a maskable interrupt. When this interrupt is received the processor saves
the contents of the PC register into stack and branches to 2CH (hexadecimal) address.
- RST6.5 is a maskable interrupt. When this interrupt is received the processor saves
the contents of the PC register into stack and branches to 34H (hexadecimal) address.
- RST7.5 is a maskable interrupt. When this interrupt is received the processor saves
the contents of the PC register into stack and branches to 3CH (hexadecimal) address.
 - TRAP is a non-maskable interrupt. When this interrupt is received the processor
saves the contents of the PC register into stack and branches to 24H (hexadecimal)
address.
- All maskable interrupts can be enabled or disabled using EI and DI instructions. RST
5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM
instruction.

Reset Signals
- RESET IN: When this signal goes low, the program counter (PC) is set to Zero, μp is
reset and resets the interrupt enable and HLDA flip-flops.
- The data and address buses and the control lines are 3-stated during RESET and
because of asynchronous nature of RESET, the processor internal registers and flags
may be altered by RESET with unpredictable results.
- RESET IN is a Schmitt-triggered input, allowing connection to an R-C network for
power-on RESET delay.
- Upon power-up, RESET IN must remain low for at least 10 ms after minimum Vcc
has been reached.
- For proper reset operation after the power – up duration, RESET IN should be kept
low a minimum of three clock periods.
- The CPU is held in the reset condition as long as RESET IN is applied. Typical
Power-on RESET RC values R1 = 75KΩ, C1 = 1μF.
- RESET OUT: This signal indicates that μp is being reset. This signal can be used to
reset other devices. The signal is synchronized to the processor clock and lasts an
integral number of clock periods.

Serial communication Signal

- SID - Serial Input Data Line : The data on this line is loaded into accumulator bit 7
whenever a RIM instruction is executed.
- SOD – Serial Output Data Line : The SIM instruction loads the value of bit 7 of the
accumulator into SOD latch if bit 6 (SOE) of the accumulator is 1.

DMA Signals
- HOLD: Indicates that another master is requesting the use of the address and data
buses. The CPU, upon receiving the hold request, will relinquish the use of the bus as
soon as the completion of the current bus transfer.
- Internal processing can continue. The processor can regain the bus only after the
HOLD is removed.
- When the HOLD is acknowledged, the Address, Data RD, WR and IO/M lines are 3-
stated.
- HLDA: Hold Acknowledge : Indicates that the CPU has received the HOLD request
and that it will relinquish the bus in the next clock cycle.
- HLDA goes low after the Hold request is removed. The CPU takes the bus one half-
clock cycle after HLDA goes low.
- READY: This signal Synchronizes the fast CPU and the slow memory, peripherals.
 - If READY is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receive data.
- If READY is low, the CPU will wait an integral number of clock cycle for READY
to go high before completing the read or write cycle.
- READY must conform to specified setup and hold times.

Registers
- Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and
load/store operations.
- Flag Register has five 1-bit flags.
o Sign - set if the most significant bit of the result is set.
o Zero - set if the result is zero.
o Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result.
o Parity - set if the parity (the number of set bits in the result) is even.
o Carry - set if there was a carry during addition, or borrow during
subtraction/comparison/rotation.
Internal architecture of 8085:

ALU
- In addition to the arithmetic & logic circuits, the ALU includes the accumulator,
which is part of every arithmetic & logic operation.
- Also, the ALU includes a temporary register used for holding data temporarily during
the execution of the operation. This temporary register is not accessible by the
programmer.

Registers
General Purpose Registers
- B, C, D, E, H & L (8 bit registers)
- Can be used singly
- Or can be used as 16 bit register pairs BC, DE& HL
- HL used as a data pointer (holds memory address)

Accumulator
- Stores 8 bit data
- Store the result of an operation
 - Store 8 bit data during I/O transfer Address

Flag Register
- 8 bit register – shows the status of the microprocessor before/after an operation. S
(sign flag), Z (zero flag), AC (auxiliary carry flag), P (parity flag) & CY (carry flag)
Sign Flag
- Used for indicating the sign of the data in the accumulator
- The sign flag is set if negative (1 – negative)
- The sign flag is reset if positive (0 –positive)

Zero Flag
- Is set if result obtained after an operation is 0
- Is set following an increment or decrement operation of that register

Carry Flag
- Is set if there is a carry or borrow from arithmetic operation

Auxiliary Carry Flag

- Is set if there is a carry out of bit 3

Parity Flag
- Is set if parity is even
- Is cleared if parity is odd

Program Counter
- This is a register that is used to control the sequencing of the execution of
instructions.
- This register always holds the address of the next instruction.
- Since it holds an address, it must be 16 bits wide.

Stack Pointer
- The stack pointer is also a 16-bit register that is used to point into memory.
 - The memory this register points to is a special area called the stack. The stack is an
area of memory used to hold data that will be retrieved soon.
- The stack is usually accessed in a Last in First out (LIFO) fashion.

Non Programmable Registers

Instruction Register & Decoder
- Instruction is stored in IR after fetched by processor
- Decoder decodes instruction in IR

Internal Clock Generator

- 3.125 MHz internally
- 6.25 MHz externally

Address and Data Busses

- The address bus has 8 signal lines A8 – A15 which are unidirectional.
- The other 8 address bits are multiplexed (time shared) with the 8 data bits.
- So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0 – D7 at the
same time.
- During the xecution of the instruction, these lines carry the address bits during the
early part, then during the late parts of the execution, they carry the 8 data bits.
- In order to separate the address from the data, we can use a latch to save the value
before the function of the bits changes.

Demultiplexing AD7-AD0
- From the above description, it becomes obvious that the AD7– AD0 lines are serving
a dual purpose and that they need to be demultiplexed to get all the information.
- The high order bits of the address remain on the bus for three clock periods.
However, the low order bits remain for only one clock period and they would be lost
if they are not saved externally. Also, notice that the low order bits of the address
disappear when they are needed most.
- To make sure we have the entire address for the full three clock cycles, we will use an
external latch to save the value of AD7– AD0 when it is carrying the address bits. We
use the ALE signal to enable this latch.

Demultiplexing AD7-AD0 13
 - Given that ALE operates as a pulse during T1, we will be able to latch the address.
Then when ALE goes low, the address is saved and the AD7– AD0 lines can be used
for their purpose as the bi-directional data lines.

Demultiplexing AD7 – AD0

- The high order address is placed on the address bus and hold for 3 clock periods.
- The low order address is lost after the first clk period, this address needs to be hold
however we need to use latch
- The address AD7 – AD0 is connected as inputs to the latch 74LS373.
- The ALE signal is connected to the enable (G) pin of the latch and the OC – Output
control – of the latch is grounded

Addressing Modes
The microprocessor has different ways of specifying the data for the instruction. These
are called addressing modes.
The 8085 has four addressing modes:
– Implied (Register) addressing, example CMA
– Immediate addressing, example MVI B, 45
– Direct addressing, example LDA 4000
– Indirect addressing, example LDAX B

Register Addressing
- This type of addressing mode specifies register or register pair that contains data.ie
(only the register need be specified as the address of the operands).
- Example MOV B, A (the content of A is copied into the register B)
Direct Addressing Mode
- Data is directly copied from the given address to the register.
- Example LDA 3000H (The content at the location 3000H is copied to the register A).
Register Indirect Addressing
- In this mode, the address of operand is specified by a register pair
- Example MOV A, M (Move data from memory location specified by H-L pair to
accumulator)
Immediate Addressing Mode
- In this mode, the operand is specified within the instruction itself.
- Example MVI A, 05 H (Move 05 H in accumulator.)
Implied Addressing Mode
- This mode doesn't require any operand. The data is specified by opcode itself.
- Example RAL, CMP

- The interfacing of the I/O devices in 8085 can be done in two ways :
- 1. Memory-Mapped I/O Interfacing :
In this kind of interfacing, we assign a memory address that can be used in the same
manner as we use a normal memory location.
- 2. I/O Mapped I/O Interfacing :
A kind of interfacing in which we assign an 8-bit address value to the input/output
 devices which can be accessed using IN and OUT instruction is called I/O Mapped
I/O Interfacing.
-
- Basis for - Memory
- I/O mapped I/O
Comparison mapped I/O

- Basic - I/O devices are - I/O devices are treated

treated as as I/O devices.
memory.

- Allotted address - 16-bit (A0 – - 8-bit (A0 – A7)

size A15)

- Data transfer - Same for - Different for memory

instructions memory and I/O and I/O devices.
devices.

- Cycles involved - Memory read - I/O read and I/O write

and memory
write

- Interfacing of I/O - Large (around - Comparatively small

ports 64K) (around 256)

- Control signal - No separate - Special control signals

control signal is are used for I/O
needed for I/O devices.
devices.

- Efficiency - Less - Comparatively more

- Decoder hardware - More decoder - Less decoder

hardware hardware required.
required.

- IO/M’ - During memory - During I/O read and

read or memory I/O write operation,
write IO/M’ is kept high.
operations,
IO/M’ is kept
low.

- Data movement - Between - Between accumulator

registers and and ports.
ports.
 - Basis for - Memory
- I/O mapped I/O
Comparison mapped I/O

- Logical approach - Simple - Complex

- Usability - In small systems - In systems that need

where memory large memory space.
requirement is
less.

- Speed of - Slow - Comparatively fast

operation

- Example of - LDA ****H - IN ****H

instruction STA ****H OUT ****H
MOV A, M
-

Peripheral I/O 8255

- The parallel input-output port chip 8255 is also called as programmable peripheral
input-output port.
- The Intel’s 8255 is designed for use with Intel’s 8-bit, 16-bit and higher capability
microprocessors.
- It has 24 input/output lines which may be individually programmed in two groups of
twelve lines each, or three groups of eight lines.
- The two groups of I/O pins are named as Group A and Group B. Each of these two
groups contains a subgroup of eight I/O lines called as 8-bit port and another
subgroup of four lines or a 4-bit port. Thus Group A contains an 8-bit port A along
with a 4-bit port C upper.
- The port A lines are identified by symbols PA0-PA7 while the port C lines are
identified as PC4-PC7. Similarly, Group B contains an 8-bit port B, containing lines
PB0-PB7 and a 4-bit port C with lower bits PC0- PC3. The port C upper and port C
lower can be used in combination as an 8-bit port C.
- Both the port C are assigned the same address. Thus one may have either three 8-bit
I/O ports or two 8-bit and two 4-bit ports from 8255. All of these ports can function
independently either as input or as output ports. This can be achieved by
programming the bits of an internal register of 8255 called as control word register
(CWR).
- The 8-bit data bus buffer is controlled by the read/write control logic. The read/write
control logic manages all of the internal and external transfers of both data and
control words.
- RD , WR , A1, A0 and RESET are the inputs provided by the microprocessor to the
READ/ WRITE control logic of 8255. The 8-bit, 3-state bidirectional buffer is used to
interface the 8255 internal data bus with the external system data bus.
- This buffer receives or transmits data upon the execution of input or output
instructions by the microprocessor. The control words or status information is also
transferred through the buffer.
- PA7-PA0: These are eight port A lines that acts as either latched output or buffered
input lines depending upon the control word loaded into the control word register.
- PC7-PC4 : Upper nibble of port C lines. They may act as either output latches or
input buffers lines.
- PC3-PC0 : These are the lower port C lines, other details are the same as PC7-PC4
lines.
- PB0-PB7 : These are the eight port B lines which are used as latched output lines or
buffered input lines in the same way as port A.
- RD : This is the input line driven by the microprocessor and should be low to indicate
read operation to 8255.
- WR : This is an input line driven by the microprocessor. A low on this line indicates
write operation.
- CS : This is a chip select line. If this line goes low, it enables the 8255 to respond to
RD and WR signals, otherwise RD and WR signal are neglected.
- A1-A0 : These are the address input lines and are driven by the microprocessor.
- These lines A1-A0 with RD , WR and CS from the following operations for 8255.
These address lines are used for addressing any one of the four registers, i.e. three
ports and a control word register as given in table below.
Direct Memory Access (DMA) :
- DMA Controller is a hardware device that allows I/O devices to directly access
memory with less participation of the processor. DMA controller needs the same
old circuits of an interface to communicate with the CPU and Input/Output devices.
If any device which is connected to input-output port wants to transfer data to memory, first of
all it will send input-output port address and control signal, input-output read to input-output
port, then it will send memory address and memory write signal to memory where data has to
be transferred. In normal input-output technique the processor becomes busy in checking
whether any input-output operation is completed or not for next input-output operation,
therefore this technique is slow.
This problem of slow data transfer between input-output port and memory or between two
memory is avoided by implementing Direct Memory Access (DMA) technique. This is faster
as the microprocessor/computer is bypassed and the control of address bus and data bus is
given to the DMA controller.
Data transfer to and from the peripherals may be done in any of the three possible ways
1. Programmed I/O.
2. Interrupt- initiated I/O.
3. Direct memory access( DMA).

Programmed I/O: It is due to the result of the I/O instructions that are written in the computer
program. Each data item transfer is initiated by an instruction in the program. Usually the
transfer is from a CPU register and memory. In this case it requires constant monitoring by the
CPU of the peripheral devices.

Interrupt- initiated I/O: Since in the above case we saw the CPU is kept busy unnecessarily.
This situation can very well be avoided by using an interrupt driven method for data transfer.
By using interrupt facility and special commands to inform the interface to issue an interrupt
request signal whenever data is available from any device. In the meantime the CPU can
proceed for any other program execution. The interface meanwhile keeps monitoring the
device. Whenever it is determined that the device is ready for data transfer it initiates an
interrupt request signal to the computer. Upon detection of an external interrupt signal the CPU
stops momentarily the task that it was already performing, branches to the service program to
process the I/O transfer, and then return to the task it was originally performing.

Direct Memory Access: The data transfer between a fast storage media such as magnetic disk
and memory unit is limited by the speed of the CPU. Thus we can allow the peripherals
directly communicate with each other using the memory buses, removing the intervention of
the CPU. This type of data transfer technique is known as DMA or direct memory access.
During DMA the CPU is idle and it has no control over the memory buses. The DMA
controller takes over the buses to manage the transfer directly between the I/O devices and the
memory unit.

Types of DMA transfer using DMA controller:

Burst Transfer :
DMA returns the bus after complete data transfer. A register is used as a byte count,being
decremented for each byte transfer, and upon the byte count reaching zero, the DMAC will
release the bus. When the DMAC operates in burst mode, the CPU is halted for the duration of
the data
transfer.

Cyclic Stealing :
An alternative method in which DMA controller transfers one word at a time after which it
must return the control of the buses to the CPU. The CPU delays its operation only for one
memory cycle to allow the direct memory I/O transfer to “steal” one memory cycle.

Interleaved mode:
In this technique , the DMA controller takes over the system bus when the
microprocessor is not using it.An alternate half cycle i.e. half cycle DMA + half cycle
processor.

Interrupt controller:
When microprocessor receives any interrupt signal from peripheral(s) which are requesting its
services, it stops its current execution and program control is transferred to a sub-routine by
generating CALL signal and after executing sub-routine by generating RET signal again
program control is transferred to main program from where it had stopped.
When microprocessor receives interrupt signals, it sends an acknowledgement (INTA) to the
peripheral which is requesting for its service.
Interrupts can be classified into various categories based on different parameters:
Hardware and Software Interrupts –
When microprocessors receive interrupt signals through pins (hardware) of microprocessor,
they are known as Hardware Interrupts. There are 5 Hardware Interrupts in 8085
microprocessor. They are – INTR, RST 7.5, RST 6.5, RST 5.5, TRAP.
Software Interrupts are those which are inserted in between the program which means these are
mnemonics of microprocessor. There are 8 software interrupts in 8085 microprocessor. They
are – RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.

Vectored and Non-Vectored Interrupts –

Vectored Interrupts are those which have fixed vector address (starting address of sub-routine)
and after executing these, program control is transferred to that address.

Maskable and Non-Maskable Interrupts –

Maskable Interrupts are those which can be disabled or ignored by the microprocessor. These
interrupts are either edge-triggered or level-triggered, so they can be disabled. INTR, RST 7.5,
RST 6.5, RST 5.5 are maskable interrupts in 8085 microprocessor.
Non-Maskable Interrupts are those which cannot be disabled or ignored by
microprocessor. TRAP is a non-maskable interrupt. It consists of both level as well as edge
triggering and is used in critical power failure conditions.
us Arbitration refers to the process by which the current bus master accesses and then leaves
the control of the bus and passes it to another bus requesting processor unit. The controller that
has access to a bus at an instance is known as a Bus master.
A conflict may arise if the number of DMA controllers or other controllers or processors try to
access the common bus at the same time, but access can be given to only one of those. Only
one processor or controller can be Bus master at the same point in time. To resolve these
conflicts, the Bus Arbitration procedure is implemented to coordinate the activities of all
devices requesting memory transfers. The selection of the bus master must take into account
the needs of various devices by establishing a priority system for gaining access to the bus.
The Bus Arbiter decides who would become the current bus master.
There are two approaches to bus arbitration:
1. Centralized bus arbitration –
A single bus arbiter performs the required arbitration.

2. Distributed bus arbitration –

All devices participating in the selection of the next bus master.

Example programs:
//Write assembly language program (ALP) to calculate sum of two 8-bit numbers.
LXI H, 2501H : "Get address of first number in H-L pair. Now H-L points to 2501H"
MOV A, M : "Get first operand in accumulator"
INX H : "Increment content of H-L pair. Now, H-L points 2502H"
ADD M : "Add first and second operand"
INX H : "H-L points 4002H"
MOV M, A : "Store result at 2503H"
HLT : "Stop"

//Write assembly language program (ALP) to calculate difference of two 8-bit numbers.
LXI H, 2501H : "Get address of first number in H-L pair. Now H-L points to 2501H"
MOV A, M : "Get first operand in accumulator"
INX H : "Increment content of H-L pair. Now, H-L points 2502H"
SUB M : "Subtract first to second operand"
INX H : "H-L points 4002H"
MOV M, A : "Store result at 2503H"
HLT : "Stop"

//Write assembly language program (ALP) to calculate sum of two 16-bit numbers.
LHLD 2501H : "Get 1st 16-bit number in H-L pair"
XCHG : "Save 1st 16-bit number in DE"
LHLD 2503H : "Get 2nd 16-bit number in H-L pair"
MOV A, E : "Get lower byte of the 1st number"
ADD L : "Add lower byte of the 2nd number"
MOV L, A : "Store result in L-register"
MOV A, D : "Get higher byte of the 1st number"
ADC H : "Add higher byte of the 2nd number with CARRY"
MOV H, A : "Store result in H-register"
SHLD 4004H : "Store 16-bit result in memory locations 2505H and 2506H"
HLT : "Stop"

//Write assembly language program (ALP) to calculate difference of two 16-bit numbers.
LHLD 2500H : "Get first 16-bit number in HL"
XCHG : "Save first 16-bit number in DE"
LHLD 2502H : "Get second 16-bit number in HL"
MOV A, E : "Get lower byte of the first number"
SUB L : "Subtract lower byte of the second number"
MOV L, A : "Store the result in L register"
MOV A, D : "Get higher byte of the first number"
SBB H : "Subtract higher byte of second number with borrow"
MOV H, A : "Store l6-bit result in memory locations 2504H and 2505H"
SHLD 2504H : "Store l6-bit result in memory locations 2504H and 2505H"
HLT : "Terminate program execution"

//Write assembly language program to swap contents of two 8-bit numbers

LDA 2500 : Load accumulator with the content of location 2500
MOV B, A :Copy content of accumulator to register B
LDA 2501 :Load accumulator with the content of location 2501
STA 2500 :Store content of accumulator to location 2500
MOV A, B :Copy content of register B to accumulator
STA 2501 :Store content of accumulator to location 2501
HLT :Terminates the program