DE Lab Examination Sample Questions

1. Design and set up a 3 bit asynchronous up-down counter using JK flip flop.
2. Design and set up a self starting mode 6 counter.
3. Design and set up an asynchronous 4 bit binary down counter.
4. Design and set up a circuit to divide the given pulse train of frequency by 6. Use minimum
number of flip flops. (Hint: Johnson Counter)
5. Design and set up a self starting counter for a sequence 0, 1, 3, 6, 0 etc (Hint: synchronous counter)
6. Design and set up a self starting mode 4 counter.
7. Set up and verify the performance of SISO using JK and D flip flops.
8. Design and set up 4 bit ring and Johnson counter.
9. Design and set up a self starting counter for a sequence 0, 1,2, 3, 6, 0 etc (Hint: synchronous counter)
10. Set up an asynchronous decade up counter.
11. Design a 3 bit parallel up-down counter.
12. Design and set up a circuit to divide the frequency of the given pulse train by 3 (Hint: Ring
Counter).
13. Design and set up a 3 bit asynchronous up-down counter using D flip flop
14. Obtain 1 KHz square wave from a 4 KHz square wave. (Hint: divide by 4 counter)
15. Set up a circuit to divide an input frequency by 6. Output should have 50% duty cycle. (Hint:
Johnson Counter)
16. Design and set up a 7 segment static display system to display numbers 0 to 9.
17. Design an asynchronous mode 6 counter using T flip flop.
18. Design and implement a synchronous BCD counter using JK flip flops.
19. Design and set up a self starting counter for a sequence 0,2,4,5,0,2,4,5 etc (Hint: synchronous counter)
20. Design and set up a self starting counter for a sequence 0, 3,5,6,0 etc (Hint: synchronous counter)
21. Design and set up ring and Johnson counter using mode control.
22. Design and set up a 7 segment static display system to display the output of a 4 bit Johnson
Counter
23. Design and set up a self starting counter for a sequence 0,1,2,4,5, 6,0 etc (Hint: synchronous counter)
24. Design and set up a full adder using EXOR and NAND gates.
25. Set up decade up/down counter.
26. Design a circuit to convert the given 2 KHz pulse into 500 Hz pulse signal.
27. Design and set up a self starting counter for a sequence 0,1,2,4,6,0 etc (Hint: synchronous counter)
28. A warehouse is used to store industrial chemicals. Toxic fumes produced by the chemicals are
removed from the ware house and dispersed in the atmosphere through three exhaust fans. The
three exhaust fans should be continuously working to remove the dangerous toxic fumes. If any
one or more fans fail an alarm should be activated to signal the failure of one or more exhaust
fans. Implement a suitable circuit to perform the function.
29. Obtain spikes without using function generator
30. A Washing Machine has three sensors to check for washing machine lid open, washing tub filled
to minimum level and weight of cloths and water in the tub. If the lid of the Washing machine is
open or the water is below the minimum level or the washing machine has been overloaded, then
the main switch must switch off the washing machine. Design a proper circuit to implement the
operation.
31. Set up a digital circuit to light four LEDs in a row. The lighting pattern is first and second,
second and third, third and fourth, fourth and first with an interval of one second. This must
repeat continuously.
32. Design and set up ring and Johnson counter using mode control.
33. Deign and set up the following circuits:
a. Circuit which works as voltage follower
b. Time delay circuit
34. Design a 2-bit serial adder.
35. Design a 3 bit parallel up-down counter. Hint: synchronous counter
36. Design and set up a circuit to divide the frequency of the given pulse train by 3. Hint. Ring
counter using 3 FF
37. Implement a simple traffic light system (only one junction is opened at a time) for a four way
junction.

38. Obtain 1 KHz square wave from a 4 KHz square wave. Hint: divide by 4 counter using 2 JK flip flop

39. Set up a circuit to divide an input frequency by 6.output should have 50% duty cycle. Ans.johnson
counter
40. Design and set up a full subtrator using E-XOR and NAND gates.
41. Design and set up a 7 segment static display system to display numbers 0 to 9.
42. Design an asynchronous mode 6 counter using T flip flop.
43. Design and implement a synchronous BCD counter using JK flip flops. Hint: mode 10 counter.

Viva Questions

1. Conversion
 decimal to hexadecimal
 Octal to hexadecimal
 Binary to octal
 Binary to hexadecimal
2. What is Gray code

3. What is a Controlled inverter.

4. State De Morgans theorem.

5. Supply voltage range of CMOS Ics.

6. What is meant by min-term and max-term.

7. What is meant by Karnaugh map/K-map.

8. What is meant by logic gate.

Ans: A gate is an electronic circuit with one input and one or more inputs. The output
always depends on the input combinations.

9. State the basic gates.

Ans: AND,OR,NOT

10. Types of logic systems.

Ans. Positive logic system – Here more positive value is assumed as logic ‘1’ and the other
as logic ‘0’. & negative logic system – Here more positive value is assumed as logic ‘0’ and
the other as logic ‘1’

11. Truth table of AND,OR ,NOT,NAND,NOR,X-OR,X-NOR

12. What is meant by universal gates. List the same.
13. The memory unit constructed using only gates.
a. ROM b.RAM c.Core d. Disc
Ans.a

14. Which logic gate is similar to the function of two series switches.
Ans. AND
15. 15. The working of a staircase switch is a typical example of the logical operation.
Ans. XOR

16. Which gate is known as the coincidence detector.

Ans.AND gate

17. What is meant by logic family.

18. Different logic families are,
a. RTL-Resistor Transistor
b. DCTL-direct coupled transistor logic
c. RCTL-Resistor Capacitor transistor logic
d. DTL-Diode Transistor Logic
e. TTL- Transistor Transistor Logic
f. IIL-Integrated Injection Logic
g. HTL-High Threshold Logic
h. ECL-Emitter Coupled Logic
i. MOS-Metal oxide semi-conductor

j. CMOS-Complementary Metal oxide semi-conductor

19. What is meant by ‘ fan –in’.

Ans. The maximum number of inputs that can be applied to the logic gate.

20. What is meant by ‘fan-out’.

Ans. the number of standard loads that the output of the gate can drive without disturbing
its normal operation.

21. Power dissipation

Ans. The power consumed per gate.

22. Propagation delay

Ans. The average transition delay time for the signal to propagate from input to output
when the signals change in value.
23. Noise margin
Ans. It is the limit of a noise voltage which may be present without impairing the proper
operation of the circuit.

24. Figure of merit

Ans. The product of propagation delay time and power dissipation.( minimum value is
desired)

25. Logic swing

Ans. The difference between the two output voltages

26. Noise immunity

Ans. The ability to withstand variations in the input levels.

27. Saturation logic

Ans. A form of logic gates in which one output state is the saturation voltage level of the
transistor. Eg. RTL,TTL,DTL

28. Current mode logic/unsaturated logic

Ans. A form at logic with transistors operated outside the saturation region. Eg: ECL

Fastest logic family ECL

Slowest logic family CMOS

Logic family which consumes less power CMOS

Logic family which consumes more power ECL

Logic family which is having highest fan out CMOS

Bi-polar logic families RTL/DTL/ECL/IIL

Unipolar logic families MOS/CMOS

TTL family IC’s are available in 74/54 series

CMOS IC’s are 4000 series & ECL family with 10000 series

Logic family with highest noise margin IIL

Logic family with minimum figure of merit IIL

29. Comparison of different logic families

DTL TTL ECL CMOS

Fan-out 8 10 25 50
Propagation 30 n sec 10 n sec 4 n sec 70 n sec
delay

Power 8mw 10mw 40mw 0.01 mw

dissipation

Noise margin 700 mv 400 mv 200 mv 300 mv

30. Differentiate b/w combinational and sequential circuits.

31. What is meant by decoder.
Ans. Logic ckt that converts an n-bit binary input code into m(2n) output lines such that
each output line will be activated for only one of the possible combinations of inputs.(its a
combinational ckt)

32. What is meant by encoder,multiplexer and de-multiplexer.

33. What is meant by flip flops.
Ans. Its a bistable multivibrator that can store one bit of information.

34. What is meant by latch.

Ans. refers to non-clocked flip-flops

35. What is meant by synchronous and asynchronous inputs.

36. Preset and clear are asynchronous inputs
37. S and R are synchronous inputs.
38. Disadvantages of SR flip-flop.
39. What is meant by race around condition. How can it be eliminated.
40. How does a FF acts like a frequency divider.
Ans.If x KHz clock signal is applied to a T- FF when T=1,then the out put signal frequency
is given by x/2 KHz.Thus it acts as a frequency divider.
41. What is meant by registers.
Ans.It s a group of FF used to store binary information.

42. What is meant by shift register.

Ans.A register that is able to shift the information either from left to the right or from right
to the left.

43. Different operations in shift registers. Ans. SIPO,SISO,PIPO,PISO

44. What is meant by universal shift register.
Ans.A register that can perform all four operations.

45. Applications of shift registers.

Ans. Multiplication/division
 Sequence generator
Ring counter and johnson ring counter

46. How can a shift register be used to multiply a binary number by 2. Ans. Left shift operation
47. What is meant by divide by n and divide by 2n counter.
48. What is meant by synchronous/parallel counter.
49. What is meant by asynchronous /ripple/serial counter.
50. Synchronous counter is faster than asynchronous counter.Why.
51. What is meant by modulus of a counter. Ans.total counting states of a counter
52. What is meant by adder and subtractor circuits.
53. What is meant by 8421 BCD code,excess three code,gray code.
54. What is meant by lock out in counters.
55. What are the ideal characteristics of an op-amp.
a. Voltage gain-infinite
b. Output resistance-zero
c. Input resistance-infinite
d. Bandwidth-infinite
e. CMMR-infinite
f. Slew rate-infinite
56. Define the op-amp parameters.
Ans. Input bias current-average of the currents entering into the inverting and non-inverting
terminals of an op-amp.
Input offset current-algebraic difference between the currents into the inverting and
noninverting terminals.
CMMR-(common mode rejection ratio)it is the ratio of differential gain to the common
mode gain.
Slew rate-rate of rise of output voltage.

57. Define unity gain frequency of the op-amp.

Ans.it is thr frequency at which open loop gain decreases to unity.(unity frequency gain for
741 IC is 1 MHz)

58. What is meant by zero crossing detector.

59. Name a circuit that can be use for checking the condition of an op-amp. Ans. Zero crossing
detector
60. What is the output of an inverting amp when a sine wave is applied.What is the gain of an
inverting amp.

61. What is the equation of gain in a non inverting amp.

62. What is meant by voltage follower.
63. Explain the working of summing amp.
64. What is the output of an integrator when the input to the integrator is a sinewave.
65. What is the output of an integrator when the input to the integrator is a square wave with 50
percentage duty cycle.

66. What happens to the frequency of the differentiator when gain increases.
Ans.The gain of the differentiator increases with increases with frequency which makes the
circuit unstable.this is the drawback of this circuit.

67. What are the merits of an op-amp integrator compared to a passive RC integrator.
Ans.provides gain and linear output.

68. List some features of the voltage follower.

Ans.high input impedance,low output impedance,unity voltage gain

69. What is meant by half power frequencies.

Ans.frequency at which gain reduces to 0.707 of its maximum value.

70. What is hysterisis.

Ans. Difference between UTP and LTP voltages.

71. Explain the working of astable multivibrator.

72. Explain the working of monostable /one shot multivibrator.
73. Derive the expression for the time period of astable and monostable multivibrator.
74. Explain the functional block diagram of 555 timer.
75. What is meant by positive edge triggering,negative edge triggering and level edge triggering.
76. Excitation table of SR,JK,T and D flip flops.

77. State the ideal characteristics of Op-amp.

i) Open loop gain, Aol = ∞
ii) Input impedance, Ri = ∞
iii) Output Impedance, Ro = 0
iv) Zero Offset, Vo = 0
v) Bandwidth, BW = ∞
78. Why differential amplifier is used as an input stage of IC op-amp?
 The differential amplifier eliminates the need for an emitter bye-pass capacitor. So,
differential amplifier is used as an input stage in op-amp ICs
79. What does operational amplifier refers to?
Operational amplifier refers to an amplifier that performs a mathematical operation. A
typical op-amp is a DC amplifier with a very high voltage gain, very high input
impedance and very low output impedance.
80. What causes slew rate?
The rate at which internal or external capacitance of Op-amp changes causes slew rate.
Also slew rate is caused by current limiting and saturation of internal stages of op-amp
where a high frequency, large – amplitude signal is applied.

81. What is input bias current?

The average of the currents entering the negative input (IB-) and positive input
(IB+) of an op-amp is called input bias
current(IB) The equation is
IB = IB+ - IB- / 2
82. Why do we use Rcomp resistor?
In a bipolar op-amp circuit, even when the input is zero, the output will not be zero.
This is due to effect of input bias current. This effect can be compensated by using
compensation resistor Rcomp, where
83. What is thermal drift?
In an op-amp the bias current, offset current and off set voltage changes with change in
temperature. Offset current drift is measured in nA/ 0C and offset voltage drift is
measured in mV/ 0C. These indicate the change in offset current or voltage for each
degree Celsius change in temperature. Forced air cooling may be used to stabilize the
ambient temperature
84. Why is IC741 op-amp not used for high frequency applications?
Op-amp IC741 has very low slew rate (0.5V/μS) and therefore cannot be used for high
frequency applications.
85. What is unity gain circuit?
Voltage follower is called unity gain circuit. The circuit does not amplify and provides
constant gain of unity.

86. Which gates are called Universal gates?

NAND and NOR gates are called universal gates because any basic gates can be
implemented using these gates.
87. What is combinational logic?
 It consists of logic gates whose output at any time is determined directly from the
present combinations of the inputs without regards to previous inputs.
88. What is sequential logic?

It uses memory elements in addition to logic gates. Their outputs are function of inputs
and state of the memory elements.
89. What is Flip flop?

A Flip flop is a sequential circuit which can maintain the binary state indefinitely as long
as power is delivered to the circuit, until directed by an input signal to switch states.

90. What are the characteristics of a clocked R-S flip flop?

RS Flip flop has 2 inputs. The cross coupled connection from the output of one gate to
the input of other gate constitutes a feedback path.
91. Bubbled OR gate is equal to NAND gate

92. Bubbled AND gate is equal to NOR gate

93. What is the difference between Latch and Flip flop?

Latches are level sensitive, flip flops are edge sensitive. Flip flops changes its output only
at times determined by clock signal. Latches changes output any time independent of
clock signal.
94. How can you convert SR flip flop to JK flip flop?

By giving the feed back we can convert, i.e Q=>S and Q=>R. Hence the S and R
inputs will act as J and K respectively.
95. What is half adder?
A combinational circuit that performs addition of 2 bits. It consists of 2 inputs and 2
outputs.
96. What is full adder?

B combinational circuit that performs addition of 3 bits. It consists of 3 inputs and 2

outputs.
97. What are half and full subtractor?

Combinational circuit that performs the subtraction of 2 bits is half subtractor and the
circuit that performs the subtraction of 3 bits is called full subtractor.
98. What is a multiplexer?
It is a digital circuit which transmits large number of information units through small
number of channels.
99. What is demultiplexer?
It is a logical circuit which receives data in asingle line and transmits it in possible 2
lines. n
100. Multiplexer is also called data selector.
101. Demultiplexer is also called data distributor.
102. What is the difference between demultiplexer and decoder? Demultiplexer does not
have enable line.
103. What is the basic difference between comparator and Schmitt trigger?
A comparator compares the input signal with reference voltage and gives the output
whereas Schmitt trigger operates between two reference points LTP and UTP.
104. State barkhausen criterion.
a) Magnitude, = 1 vA
b) Phase, = 0 vA
105. 4. What is the merit of regenerative comparator?

In regenerative comparator, the feedback enhances the comparator input. The phase
difference is not visualized due to positive feedback.
106. What is an oscillator?
An oscillator is basically a positive feedback circuit where a fraction of output voltage
Vo is fed back to the input end of the basic amplifier, which is in phase with the signal
to the basic amplifier. What are Counters and what are its types?
A sequential circuit that goes through a prescribed sequence of states upon the
application of input pulses is called counter. a) Asynchronous counters
b) Synchronous counters.

107. What are Ripple counters?

Counters in which first flip flop output transition serves as trigger for the other
consecutive flip flops.
108. What are synchronous counters?

Counters in which clock pulses of all the flip flops are triggered at the same instant.
109. State the advantage of synchronous counter over asynchronous counters?

Synchronous counter reduces the delay time as all the clock pulses are given
simultaneously. 5. When two counters are cascaded, the overall MOD number is equal to
the product of their individual MOD numbers.

110. How many flip-flops are required to construct a decade counter?

Four (4).
111. What is MOD counter?

The modulus of a counter is the number of different logic states it goes through before
it comes back to the initial stage to repeat the count sequence.
112. How many different states does a 3-bit asynchronous counter have?
Eight (8).
113. State some applications of counters.
 a) Traffic signals
b) Medical instruments
114. List the basic blocks of IC 555 timer? A relaxation oscillator.
R-S flip-flop
Two comparators
Discharge transistors.

115. Give the applications of 555-timer Astable multivibrator.

a) Square wave generator
b) Voltage Controlled Oscillator (VCO)
c) FSK Generator
d) Schmitt trigger.
116. What is the advantage of 555 IC over op amp?
555 IC generates accurate time delay compared to op amp.
117. List the applications of monostable mode of 555 timer. .
a) Missing Pulse detector
b) Linear ramp generator
c) Frequency divider
118. List all the types of DAC.
a) Weighted resistor
b) R-2R ladder
c) Inverted R-2R ladder.

119. What is the advantage of R-2R ladder over weighted resistor?

In weighted resistor, for higher order conversion the values of resistors become very
high which is overcome in R-2R ladder which has only R and 2R values of resistors.
120. List the various types of ADC.
i) Direct type
d) Flash type
e) Counter
f) Successive Approximation Register
g) Tracking

ii) Integrating type

a) Charge balancing
b) Integrating 4. Define resolution.
` Smallest change in voltage which may be produced at output of the converter.
121. 5. List the specifications of DAC and ADC.
a) Resolution
b) Linearity
c) Accuracy
d) Monotonicity
e) Settling time
f) Stability.
122. How many comparisons will be performed in an 8 bit successive approximation type
ADC? 8 Comparisons
123. The basic step of 9 bit DAC is 10.3mV. If 000000000 represents 0V. What output is
produced if the input is 101101111?

7.38mV.
124. State the applications of DAC and ADC .

a) Digital signal processing

b) Communication circuits
125. For R-2R ladder 4 bit type DAC find the output voltage if digital input is 1111. Assume
VR = 10V, R = Rf = 10K.
Vo = 9.375V
126. Which is the fastest type of ADC? Why?
Successive approximation is the fastest type of ADC. It completes n-bit conversion in n
clock periods.