Department of Electronics & Communication

Engineering

DIGITAL ELECTRONICS LAB

II B.Tech-IT,IOT,AI&DS I-Semester (2023-24)

LABORATORY MANUAL

SCHOOL OF ENGINEERING & TECHNOLOGY

GURU NANAK INSTITUTIONS TECHNICAL CAMPUS
(AUTONOMOUS)
Ibrahimpatnam, RR Dist-501506
www.gniindia.org
 Department of Electronics & Communication
Engineering
DIGITAL ELECTRONICS LAB

II B.Tech- IT,IOT,AI&DS I-Semester (2023-24)

LABORATORY MANUAL

SCHOOL OF ENGINEERING & TECHNOLOGY

GURU NANAK INSTITUTIONS TECHNICAL CAMPUS
(Affiliated to JNUTH, Approved by AICTE)
Ibrahimpatnam, RR Dist-501506
www.gniindia.org
 Department of Electronics & Communication
Engineering
DIGITAL ELECTRONICS LAB
II B.Tech- IT,IOT,AI&DS I-Semester (2023-24)
LABORATORY MANUAL

SCHOOL OF ENGINEERING & TECHNOLOGY

GURU NANAK INSTITUTIONS TECHNICAL CAMPUS
(Affiliated to JNUTH, Approved by AICTE)
Ibrahimpatnam, RR Dist-501506
www.gniindia.org

Authorized by
Document No:
Prepared by:
GNITC/ECE/DE
Regulation:
HOD-ECE
 GURU NANAK INSTITUITONS TECHNICAL CAMPUS
SCHOOL OF ENGINEERING & TECHNOLOGY

Department of Electronics & Communication Engineering

DIGITAL ELECTRONICS LAB

II B.Tech- IT,IOT,AI&DS I-Semester (2023-24)
LABORATORY MANUAL

CONTENT PAGE

S.No Description Page No

1 Syllabus

2 PEO’s & PO’s

3 List of Experiments

4 Experiment Planner
 GURU NANAK INSTITUITONS TECHNICAL CAMPUS
(AUTONOMOUS)

DIGITAL ELECTRONICS LAB

IIYear –B.TECH -IT,IOT,AI&DS I SEM -

LIST OF EXPERIMENTS

1. Realization of Boolean Expression using Gates

2. Design and realization of logic gates using Universal gates
3. Generation of clock using NAND / NOR gates.
4. Design a 4 – bit Adder / Subtractor.
5. Design and realization of a 4 – bit Gray to Binary and Binary to Gray Converter.
6. Design and realization of a 4-bit pseudo random sequence generator using logic gates.
7. Design and realization of an 8 bit parallel load and serial out shift register using flip-flops.
8. Design and realization of a Asynchronous counter using flip-flops.
9. Design and realization of Synchronous counters using flip-flops.
10. Design and realization of 8x1 MUX using 2x1 MUX.
11. Design and realization of 4 bit comparator.
12. Design and Realization of a sequence detector-a finite state machine.

PROGRAMME EDUCATIONAL OBJECTIVES (PEO’s):

 PEO1: Produce Industry ready graduates having the ability to apply knowledge across the disciplines and in
emerging areas of Electronics and Communication Engineering for higher studies, employability
and handle the realistic problems.

PEO2: Graduates shall have good communication skills, possess ethical conduct, sense of responsibility to
serve the society and protect the environment.

PEO3: Graduates shall have soft skills, managerial skills, leadership qualities and understand the need for
lifelong learning for a successful professional career.

PROGRAM OUTCOMES (POs) :

Engineering Graduates will be able to:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an
engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex engineering problems
reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and design system
components or processes that meet the specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research methods including
design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid
conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and IT
tools including prediction and modeling to complex engineering activities with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health,
safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering solutions in societal and
environmental contexts, and demonstrate the knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams,
and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the engineering community
and with society at large, such as, being able to comprehend and write effective reports and design documentation,
make effective presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one’s own work, as a member and leader in a team, to manage projects
and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent and
life-long learning in the broadest context of technological change.
PSOs:

PSO1: Solve, Design and analyze circuits in the field of Communication Engineering

PSO2: Design and implement Circuits in the field of Digital Signal Processing, Embedded Systems and Antenna
using various modern software tools

MAPPING of PEO’s and PO’s:

Program Program Outcomes

Education
al
Objectives
PO PO PO PO PO PO PO PO PO PO PO PO PSO PSO
1 2 3 4 5 6 7 8 9 10 11 12 1 2
PEO1 3 3 3 3 3 2 1 1 1 2 2 2 3 3
PEO2 1 1 1 1 1 3 3 3 2 3 1 1 1 1
PEO3 1 1 1 1 2 1 1 2 3 3 3 3 2 2
EXPERIMENT NO.1 DATE:

REALIZATION OF BOOLEAN EXPRESSION USING GATES

AIM:

To Implement of the given Boolean function using logic gates in both SOP and POS forms
Two input SOP - A.B + A’.B’
Two input POS: - (A+B) (B+C) (A+C’)

APPARATUS REQUIRED:

1. Digital Trainer Kit/Bread board.

2. Single Strand Wires.
3. ICs-7408,7432,7404.
4. Power Supply
5. Connecting Wires.

THEORY:

a) SOP: Sum of Product is the abbreviated form of SOP. Sum of product form is a form of expression in
Boolean algebra in which different product terms of inputs are being summed together. This product is not
arithmetical multiply but it is Boolean logical AND and the Sum is Boolean logical OR.
b) POS: The product of Sum form is a form in which products of different sum terms of inputs are taken. These
are not arithmetic product and sum but they are logical Boolean AND and OR respectively.

PROCEDURE:

a) FOR SOP: A.B + A’.B’

1. Place the Digital lab kit at one place.

2. Take the one AND gate ICs i.e. IC no.7408, one NOT gate IC i.e. IC no. 7404 and one OR
gate IC i.e. IC no. 7432.
3. Place these 3 ICs in the breadboard one by one.
4. Now, connect the AND gate with the inputs of A and B and other AND gate in the same IC is
given by the complement input of the A and B i.e. A’ and B’ by using NOT gate with the help
of connecting wires
5. Give the output voltage Vcc and GROUND to all the ICs separately. When whole
configuration is read, gently on the switch and note there output of different values of A and B
i.e. either 0 or 1.
LOGIC CIRCUIT FOR POS:

Y= (A+B) (B+C) (A+C’)

TRUTH TABLE:

A B C A+B B+C A+C’ Y=(A+B)(B+C)(A+C’)

0 0 0 0 0 1 0
0 0 1 0 1 0 0
0 1 0 1 1 1 1
0 1 1 1 1 0 0
1 0 0 1 0 1 0
1 0 1 1 1 1 1
1 1 0 1 1 1 1
1 1 1 1 1 1 1

b) FOR POS: (A+B) (B+C) (A+C’)

1. Place the Digital lab kit at one place.
2. Take the 1 OR, 1 AND, 1 NOT gates IC
3. Place these 3 ICs in the breadboard one by one.
4. Now, connect the OR gate of Input A or B, B or C and last one is A or C’ (i.e. complement
of C using NOT gate). Inputs are connected with the help of connecting wires.
5. When whole circuit is complete, on the switch and note down the output with different
values of A, B and C.

PRECAUTIONS:
1. Connecting wires should be rubbed with sand papers so that there is no rust.

2. Make sure that the apparatus is switched off while placing ICs and connecting of wires.

3. The connections should be tights.

4. ICs are placed in a proper way in the breadboard. There is no short of current in the in same inputs.
LOGIC CIRCUIT FOR SOP:

Y= A.B + A’.B’

TRUTH TABLE:

A B A’ B’ A.B A’.B’ Y=AB’+AB’

0 0 1 1 0 1 1
0 1 1 0 0 0 0
1 0 0 1 0 0 0
1 1 0 0 1 0 1

RESULT:
Hence, given Boolean Expression is implemented by the Logic Gates.

VIVA:
1. What is Min term and Max Term?
2. State the difference between SOP and POS.
3. What is meant by canonical representation?
4. What is K-map? Why it is used?
5. What are universal gates?
EXPERIMENT NO.2 DATE:

DESIGN & REALIZATION OF LOGIC GATES USING UNIVERSAL GATES

AIM:

a) To construct NOT, AND, OR, Exclusive OR (EX-OR), Exclusive NOR (EX-NOR) logic gates using only NAND
gates.
b) To construct NOT, AND, OR, Exclusive OR (EX-OR), Exclusive NOR (EX-NOR) logic gates using only NOR gates.

APPARATUS REQUIRED:

1. Digital Trainer Kit/Bread board.

2. Single Strand Wires.
3. ICs-7408,7432,7404.
4. Power Supply
5. Connecting Wires.

THEORY:

we can realise all of the other Boolean functions and gates by using just one single type of universal logic gate,
the NAND (NOT AND) or the NOR (NOT OR) gate, thereby reducing the number of different types of logic gates required,
and also the cost.
The NAND and NOR gates are the complements of the previous AND and OR functions respectively and are individually
a complete set of logic as they can be used to implement any other Boolean function or gate. But as we can construct other
logic switching functions using just these gates on their own, they are both called a minimal set of gates. Thus the NAND and
the NOR gates are commonly referred to as Universal Logic Gates.

i. NAND GATE as NOT GATE:

A NOT produces complement of the input. It can have only one input, tie the inputs of a NAND
gate together. Now it will work as a NOT gate. Its output is

Q = (A.A)’ = (A)’
LOGIC DIAGRAM FOR IMPLEMENTATION OF LOGIC GATE USING NAND GATE:

TRUTH TABLE:

A)NAND GATE B) NOT GATE C) AND GATE D) OR GATE

A B Q A A’ A B Q A B Q
0 0 1 0 1 0 0 0 0 0 0
0 1 0
0 1 1 1 0 0 1 1
1 0 0
1 0 1 1 0 1
1 1 1
1 1 0 1 1 1
E) EX-OR GATE F)BUFFER G) NOR GATE H) EX-NOR GATE
A B Q A Q A B Q A B Q
0 0 0 0 0 0 0 1 0 0 1
0 1 1 1 1 0 1 0 0 1 0
1 0 1 1 0 0 1 0 0
1 1 0 1 1 0 1 1 1
LOGIC DIAGRAM FOR IMPLEMENTATION OF LOGIC GATE USING NOR GATE:

TRUTH TABLE:

A)NAND GATE B) NOT GATE C) AND GATE D) OR GATE

A B Q A A’ A B Q A B Q
0 0 1 0 1 0 0 0 0 0 0
0 1 0
0 1 1 1 0 0 1 1
1 0 0
1 0 1 1 0 1
1 1 1
1 1 0 1 1 1
E) EX-OR GATE F)BUFFER G) NOR GATE H) EX-NOR GATE
A B Q A Q A B Q A B Q
0 0 0 0 0 0 0 1 0 0 1
0 1 1 1 1 0 1 0 0 1 0
1 0 1 1 0 0 1 0 0
1 1 0 1 1 0 1 1 1

ii. NAND GATE as AND GATE:

A NAND produces complement of AND gate. So, if the output of a NAND gate is inverted, overall
output will be that of an AND gate.
Q = ((A.B)’)’= (A.B)
 iii. NAND GATE as OR GATE:
From Demorgan’s theorems: (A.B)’ = A’ + B’. Similarly, (A’.B’)’ = A’’ + B’’ = A + B So, give the inverted inputs to
a NAND gate, obtain OR operation at output.
iv. NAND GATE as EX-OR GATE:
The output of a two input EX-OR gate is given by: Y = A’B + AB’. EX-OR gate can be implemented using four
NAND gates as follows.
Q= ((A (AB)’)’ (B (AB)’)’)’
= (A(AB)’)’’ + (B(AB)’)’’
= (A(AB)’) + (B(AB)’)
= (A(A’ + B)’) + (B(A’ + B’))
= (AA’ + AB’) + (BA’ + BB’)
= ( 0 + AB’ + BA’ + 0 )
= AB’ + BA’
Q = AB’ + A’B
v. NAND GATE as EX-OR GATE:
EX-NOR gate is actually EX-OR gate followed by NOT gate. So give the output of EX-OR gate to a
NOT gate, overall output is that of an EX-NOR gate.
Q = AB+ A’B’
vi. NAND GATE as NOR GATE:
A NOR gate is an OR gate followed by NOT gate. So connect the output of OR gate to a NOT gate,
overall output is that of a NOR gate.
Q = (A + B)’
vii. NOR GATE as NOT GATE:
A NOT produces complement of the input. It can have only one input, tie the inputs of a NOR gate
together. Now it will work as a NOT gate. Its output is
Q = (A+A)’ = (A)’
viii. NOR GATE as AND GATE:
From Demorgan’s theorems: (A+B)’ = A’. B’. Similarly, (A’+B’)’ = A’’. B’’ = A .B So, give the inverted inputs to a
NOR gate, obtain AND operation at output.

ix. NOR GATE as OR GATE:

A NOR produces complement of OR gate. So, if the output of a NOR gate is inverted, overall output will
be that of an OR gate.
Q = ((A+B)’)’= (A+B)
x. NOR GATE as EX-OR GATE:
EX-OR gate is actually EX-NOR gate followed by NOT gate. So give the output of EX-NOR gate to a NOT gate,
overall output is that of an EX-OR gate.
xi. NOR GATE as EX-NOR GATE:
The output of a two input EX-NOR gate is given by: Y = AB + A’B’. EX-NOR gate can be implemented using four
NOR gates as follows.
 Q = ((A + (A+B)’)’ (B +( A+B)’)’)’
= (A+(A+B)’)’’.(B+(A+B)’)’’
= (A+(A+B)’).(B+(A+B)’)
= (A+A’B’).(B+A’B’)
= (A + A’).(A + B’).(B+A’)(B+B’)
= 1.(A+B’).(B+A’).1
= (A+B’).(B+A’)
= A.(B + A’) +B’.(B+A’)
= AB + AA’ +B’B+B’A’
= AB + 0 + 0 + B’A’
= AB + B’A’
Q = AB + A’B’
xii. NOR GATE as NAND GATE:
A NAND gate is an AND gate followed by NOT gate. So connect the output of AND gate to a NOT gate, overall
output is that of a NAND gate.
Q = (AB)’
PROCEDURES:

1. Connect the trainer kit to ac power supply.

2. Connect the NOR/ NAND gates for any of the logic functions to be realized.
3. Connect the inputs of first stage to logic sources and output of the last gate to logic
indicator.
4. Apply various input combinations and observe output for each one.
5. Verify the truth table for each input/ output combination.
6. Repeat the process for all logic functions.
7. Switch off the ac power supply.

RESULT:
Hence all the logic gates are realized by universal gates.

VIVA:
1. Why NAND and NOR gates are called universal gates?
2. State Demorgan’s theorem,
3. What is Boolean algebra?
4. What is truth table?
5. Why NAND NAND realization is prefer over AND OR realization?
EXPERIMENT NO.3 DATE:

GENERATION OF CLOCK USING NAND/NOR GATES

AIM:
To design a generation of clock using NAND/NOR gates.

APPARATUS REQUIRED:
1. Digital Trainer Kit

2. CRO & CRO Probes.

3. IC 7400/IC4093.
4. Connecting wires.

5. Capacitor-0.0001uF.

6. Resistor-3.5kΩ.

7. Power Supply.

THEORY:

A clock generator is a circuit that produces a timing signal (known as a clock signal and behaves as such) for use in
synchronizing a circuit's operation. The signal can range from a simple symmetrical square wave to more complex
arrangements. The basic parts that all clock generators share are a resonant circuit and an amplifier. Since all logic
operations in a synchronous machine occur in synchronism with a clock, the system clock becomes the basic timing unit.
The system clock must provide a periodic wave forms that can be used as a synchronous signal. The square waveform is a
typical clock waveform used in a digital system.
The clock defines a basic timing interval during which logic operation must be performed. This basic timing interval
is defined as a clock cycle time and is equal to one period of the clock waveform. Thus all logic elements, flip-flops, gates,
and so on must complete their transition in less than one clock cycle time. In this experiment to generating the clock we are
using the NAND and NOR gates using these gates we generating the 450KHZ clock signal.
CIRCUIT DIAGRAM USING NAND GATE CIRCUIT DIAGRAM USING NOR GATE

THEORETICAL CALCULATIONS:-
F=450 KHz
F= 1/2πRC
Assume C=0.0001uF
R=1/2π*450K*0.0001FR=3.
5KΏ
PROCEDURE:
1. Connect the NAND/NOR gate inputs as for circuit diagram.
2. Connect the Capacitor to input of NAND/NOR gate and with respect to the Ground.
3. Connect the Resistor feedback or parallel to the NAND/NOR gate.
4. Take the output at NAND/NOR gate output and at the ground.
5. Observe the waveform at the CRO and calculate the frequency of clock pulse.

THEORETICAL CALCULATIONS:-
F=450 KHz
F= 1/2πRC
Assume C=0.0001uF
R=1/2π*450K*0.0001FR=3.
5KΏ
EXPECTED OUTPUT:

RESULT: Hence the design of a 450 KHZ clock pulse using NAND/NOR gates has been verified practically.

VIVA:
1. What is frequency?
2. What is the formula to find frequency?
3. What is meant by timing signal?
4. What is meant by one period?
EXPERIMENT NO.4 DATE:
DESIGN A 4-BIT ADDER/SUBTRACTOR
AIM:
To study and implement 4 bit adder/subtractor

APPARATUS REQUIRED:
1) Trainer kit
2) IC 7483
3) Patch chords
4) Power supply

THEORY:
Adders are important not only in computers but in many types of digital system in which numerical data are
processed. An understanding of the basic adder operation is fundamental to the study of digital system. In this experiment
using the 4 bit add/sub constructing the 16 bit add/sub. The IC number for 4 bit add/sub is 74LS83A. These full adders
perform the addition of two 4-bit binary numbers. The sum (∑) outputs are provided for each bit and the resultant carry (C4) is
obtained from the fourth bit. These adders feature full internal look ahead across all four bits. This provides the system
designer with partial look ahead performance at the economy and reduced package count of a ripple-carry implementation.
The adder logic, including the carry, is implemented in its true form meaning that the end- around carry can be accomplished
without the need for logic or level inversion. The cascading of the 4 bit adder we can form the 16 bit adder. The carry should
be forwarded to another IC.

PIN DIAGRAM OF IC7483:

CIRCUIT DIAGRAM:

PROCEDURE:

a) ADDITION

1) Connect the A0-A3 to the logic switches provided on the trainer kit.

2) Connect the B0-B3 to the logic switches provided on the trainer kit.

3) Connect the outputs to the LED indicators.

4) Connect the mode switch to the logic switches.

5) Now put the mode switch in logic ‘0’ it is indicated that addition operation performing.

6) Now give the input data using the A0-A3 and B0-B3logic switches

b) SUBTRACTION

1) Connect the A0-A3 to the logic switches provided on the trainer kit.

2) Connect the B0-B3 to the logic switches provided on the trainer kit.
 3) Connect the outputs to the LED indicators.

4) Connect the mode switch to the logic switches.

5) Now put the mode switch in logic ‘1’ it is indicated that Subtraction operation performing.

6) Now give the input data using the A0-A3 and B0-B3logicswitches.

7) To perform the subtraction operation we 1’s complement the data of the ‘B’ input.

8) Now add the data input A and 1’s Complemented data B

OUTPUT:

A) ADDITION
Input data A0-A3 = 1 0 1 0

Input data B0 - B3 = 0 1 0 1

Output =1 1 1 1

B) SUBTRACTION
Input data A0-A3 = 1 0 1 0
Input data B0-B3 = 0 1 0 1
1’s complement of i/p B = 1 0 1 0
Output = 0 1 0 0
Carry = 1

RESULT:

Hence the 4 bit addition and subtraction is verified.

VIVA:
1) What are the basic types of adder?
2) What is the other name of controlled inverter?
3) Which logic gate is known as half adder?
4) What is meant by combinational circuit?
5) List the applications of combinational circuit.
EXPERIMENT NO.5 DATE:
DESIGN & REALIZATION OF 4 BIT GRAY TO BINARY AND BINARY TO GRAY
CODE CONVERTION

AIM:
To study and implementation of 4 bit gray to binary and binary to gray code conversion.

APPARATUS REQUIRED:
1)Trainer kit
2)Patch chords
3)Power supply

THEORY:-
The availability of a large variety of codes for the same discrete elements of information results in the use of different
codes by different digital system. It is sometimes necessary to use the output of one system as the input to another. A
conversion circuit must be inserted between the two systems if each uses different codes for the same information. Thus, a
code converter is a circuit that makes the two systems compatible even though each uses a different binary code. The binary
number system is a system that uses only the digits 0 & 1 as codes. To represent a group of 2n distinct element in a binary
code requires a minimum of n bits. This is because it is possible to arrange n bits in 2n distinct ways.
Although the minimum number of bits required to code 2n distinct quantities is
n, there is no maximum number of bits that may be used for binary code. For example, a group of four distinct quantities can
be represented by a two bit code, with each quantity assigned one of the following bit combinations: 00, 01, 10, and 11. A
group of eight elements requires a three bit code, with each element assigned to one and only one of the following 000, 001,
010, 011, 100, 101, 110, and 111. Gray code (reflected code) is shown in Table 1. Number in the gray code changes by only
one bit as it proceeds from one number to the next. For example in going from decimal 7 to 8, the gray code number changes
from 0100 to 1100; these number differ only in MSB. So it is with the entire gray code; every number differs by only one bit
from the preceding number. Here we are using the XOR gates the IC 74ls86 is quardpack XOR gate Ices.

PIN DIAGRAM (74LS86):-

LOGIC DIAGRAM:-

BINARY TO GRAY CODE CONVETER

PROCEDURE (BINARY TO GRAY):-

1) The inputs are B0, B1, B2 and B3 connected to the logic switches.

2) The outputs are G0, G1, G2 and G3 connected to the led indication.

3) Now switch on the trainer kit.

4) By applying the binary inputs through the logic switches observe the outputs G0, G1, G2 and G3 led indication.

TRUTH TABLE:(BINARY TO GRAY)

Inputs Outputs
Decimal
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
 14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
K-MAP:
For G3: For G2

G2=b3

5) Note down the outputs in a truth table.

PROCEDURE (GRAY TO BINARY CODE):

1) The inputs are G0, G1, G2 and G3 connected to the logic switches.

2) The outputs are B0, B1, B2 and B3 connected to the led indication.

3) Now switch on the trainer kit.

4) By applying the gray inputs through the logic switches observe the outputs B0, B1, B2 and B3 led indication.

5) Note down the outputs in a truth table.

For G1 For G0
LOGIC DIAGRAM OF GRAY TO BINARY CODE:

TRUTH TABLE:(GRAY TO BINARY)

Inputs Outputs
Decimal
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 1 0 0 1 0
3 0 0 1 0 0 0 1 1
4 0 1 1 0 0 1 0 0
5 0 1 1 1 0 1 0 1
6 0 1 0 1 0 1 1 0
7 0 1 0 0 0 1 1 1
8 1 1 0 0 1 0 0 0
9 1 1 0 1 1 0 0 1
10 1 1 1 1 1 0 1 0
11 1 1 1 0 1 0 1 1
12 1 0 1 0 1 1 0 0
13 1 0 1 1 1 1 0 1
14 1 0 0 1 1 1 1 0
15 1 0 0 0 1 1 1 1
For B0: For B1
For B2 For B3

RESULT:-
Hence the Binary to Gray and Gray to Binary code conversion is designed and verified.

VIVA:
1) What is the use of code converters?

2) Why is gray code is used?

3) Why gray code is called reflected code?

4) What are the advantages of gray code?

5) What are the applications of gray code?

EXPERIMENT NO.8 DATE:
Design and realization of a 4-bit pseudo random sequence generator
using logic gates.

AIM: To verify the 4 Bit Pseudo Random Sequence Generator Using Logic gates.

EQUIPMENT REQUIRED:
1.4-bit Ring Counter trainer kit.
2.Patch Cards.
3.Power Supply.

THEORY:
In the Shift register if we apply a serial data signal to the input of a serial-in to serial-out shift
register, the same sequence of data will exit from the last flip-flop in the register chain after a preset
number of clock cycles thereby acting as a sort of time delay circuit to the original signal. But what if
we were to connect the output of this shift register back to its input so that the output from the last flip-
flop, QD becomes the input of the first flip-flop, DA. We would then have a closed loop circuit that "re-
circulates" the DATA around a continuous loop for every state of its sequence, and this is the principal
operation of a Ring Counter. Then by looping the output back to the input, we can convert a standard
shift register into a ring counter. Consider the circuit below.
The synchronous Ring Counter example above is preset so that exactly one data bit
in the register is set to logic "1" with all the other bits reset to "0". To achieve this, a "CLEAR" signal
is firstly applied to all the flip-flops together in order to "RESET" their outputs to a logic "0" level and
then a "PRESET" pulse is applied to the input of the first flip-flop (FFA) before the clock pulses are
applied. This then places a single logic "1" value into the circuit of the ring counter.
So on each successive clock pulse, the counter circulates the same data bit between
the four flip-flops over and over again around the "ring" every fourth clock cycle. But in order to cycle
the data correctly around the counter we must first "load" the counter with a suitable data pattern as all
logic "0's" or all logic "1's" outputted at each clock cycle would make the ring counter invalid. This
type of data movement is called "rotation", and like the previous shift register, the effect of the
movement of the data bit from left to right through a ring counter can be presented graphically as
follows along with its timing diagram.
4- bit Ring Counter:
 PROCEDURE:

1. Connect Input pins A,B & CLR to the input switches, CLK to the pulsar switch.
2. Connect the outputs QA, QB, QC and QD to the output switches.
3. First make the clear input high, then make both input A & B high.
4. Now give the clock pulse, for every pulse the output shifts from one flip flop to another.
5. Verify the 4-bit ring counter truth table.

TRUTH TABLE:

INPUTS OUTPUTS

A B CLK CLR QA QB QC QD
L L 0 L L L L L

X X L L L L L

H H H H L L L

H H H H H L L

H H H H H H L

H H H H H H H

H L H SHIFT LEFT WITH LOW

L H H SHIFT LEFT WITH LOW

H H L L L L L

NOTE: When you are giving the clear input high all the outputs may not become zero and
hence count continues in the same manner.

Result: Hence the truth table of 4 Bit Pseudo Random Sequence Generator Using Logic gates has been
verified.
EXPERIMENT NO.7 DATE:
DESIGN & REALIZATION OF 8 BIT PARALLEL LOAD AND SERIAL OUT SHIFT
REGISTER

AIM:
To study and implementation of 8 bit parallel load and serial out using two 4 bit shift Register.

APPARATUS REQUIRED:
1)Trainer kit
2)Patch chords
3)Power supply

THEORY:
A register is simply a group of flip flops that can be used to store a binary number. A shift register is a
group of flip flops connected such that the binary number can be entered (shifted) into the register and possibly
shifted out. There are two ways to shift the data (bits in the binary number) from one place to another. The first
method involves shifting the data 1 bit at a time in a serial fashion, beginning with either MSB or LSB. This
technique is referred to as serial shifting. The second method involves shifting all the data bits simultaneously and
is referred to as parallel shifting. There are two ways to shift data into a register (serial or parallel) and similarly
two ways to shift data out of the register. This leads to the construction of four basic types of registers.

This bidirectional shift register is designed to incorporate virtually all of the features a system designer
may want in a shift register; they feature parallel inputs, parallel outputs, right- shift and left-shift serial inputs,
operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation,
namely:

a. Parallel (broadside) load

b. Shift right (in the direction QA toward QD)
c. Shift left (in the direction QD toward QA)
d. Inhibit clock (do nothing)

Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode
control inputs, S0 and S1, HIGH. The data is loaded into the associated flip-flops and appear at the outputs after
the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished
synchronously with the rising edge of the clock pulse when S0 is HIGH and S1 is LOW. Serial data for this mode
PIN DIAGRAM OF IC74LS194:

CIRCUIT DIAGRAM:
TRUTH TABLE:-

SERIA
PARALLEL OUTPUTS L
INPU TS OUTPU
Mode S S Clea Clock T
0 1 r
Q Q Q Q QH
A B C D E F G H Q Q QE Q
A B C D F G H
Hold 1 1 H 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
1 0 H 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
1 0 H 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Shift 1 0 H 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0
right 1 0 H 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
1 0 H 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
1 0 H 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
1 0 H 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

LOGIC DIAGRAM FOR 4-BIT PISO SHIFT REGISTER USING FLIPFLOP

Serial data for this mode is entered at the shift-right data input. When S0 is LOW and S1 is HIGH, data shifts left
synchronously and new data is entered at the shift-left serial input.

PROCEDURE:-

1) Connect the above circuit on the trainer kit.

2) Here the selection lines of the two IC can be shorted then it can be form the S0 and S1.
3) Connect the first pin of the two Ic’s then it can be form a clear then it connect
to the logic switch.
4) Short the pin number 11 of the both the ic’s then it forms a common clock
line then it is connected to the 1Hz clock generator or the pulsar switch.
5) Now connect the parallel data inputs of the first ic and the
second ic to the logic switches.
6) Connect the QA, QB, QC and QD of the first ic to the led’s shown in the circuit.
7) Connect the QA, QB, QC and QD of the second ic to the led’s shown
in the circuit assume it as QE, QF, QG and QH.
8) Connect the 2pin of the first ic to the 12pin of the second ic.
9) Connect the serial input of the second IC (pin7) to the logic switch put in logic ‘0’.
10) Connect the 2pin of the second ic to the 12pin of the first ic.
11) Connect the 7pin of the second ic to the 15pin of the first ic.
12) Connect the parallel inputs (ABCD) first ic to the logic switches similarly
connect the Parallel inputs (ABCD) of the second ic to the logic switches
and assume it as EFGH.
13) Now put the selection lines both are high that is S0=’1’ and S1=’1’
now apply the input Data. Whatever you given it will be indicated on
the led’s.
Ex:A=1,B=0,C=0,D=0,A=0,B=1,C=0,D=0=1000 0100
14) After applying the parallel data put the S0=’0’ and S1=’1’ then the
data is shifted right side.
15) The input data serially exited at the QA you will observe that
using the pulsar switch giving a single pulse at a time.
16) Observe the truth table
RESULT: - Hence the 8 bit parallel load and serial out using two 4 bit shift Register constructed and verified.

VIVA:
1. What is meant by shift register?
2. What are the types of shift registers?
3. What is the use of shift register?
4. What is meant by universal shift register?
5. What are the applications of shift registers?
EXPERIMENT NO.8 DATE:
DESIGN AND REALIZATION OF ASYNCHRONOUS COUNTER USING FLIFLOPS
AIM:

To study and realize the asynchronous decade counter using flip flop

APPARATUS REQUIRED:
1. Digital Trainer Kit
2. Patch cord
3. Power supply,
4. IC74LS 10
5. IC74LS73

THEORY:

Asynchronous counters are those whose output is free from the clock signal. Because the flip flops in
asynchronous counters are supplied with different clock signals, there may be delay in producing output.
The required number of logic gates to design asynchronous counters is very less. So they are simple in design.
Another name for Asynchronous counters is “Ripple counters”.
If we take the modulo-16 asynchronous counter and modified it with additional logic gates it can be made
to give a decade (divide-by-10) counter output for use in standard decimal counting and arithmetic circuits.
Such counters are generally referred to as Decade Counters. A decade counter requires resetting to zero when the
output count reaches the decimal value of 10, ie. when DCBA = 1010 and to do this we need to feed this condition
back to the reset input. A counter with a count sequence from binary “0000” (BCD = “0”) through to “1001”
(BCD = “9”) is generally referred to as a BCD binary-coded-decimal counter because its ten state sequence is that
of a BCD code but binary decade counters are more common.
This type of asynchronous counter counts upwards on each trailing edge of the input clock signal starting
from 0000 until it reaches an output 1001 (decimal 9). Both outputs QA and QD are now equal to logic “1”. On
the application of the next clock pulse, the output from the 74LS10 NAND gate changes state from logic “1” to a
logic “0” level.
As the output of the NAND gate is connected to the CLEAR ( CLR ) inputs of all the 74LS73 J-K Flip-
flops, this signal causes all of the Q outputs to be reset back to binary 0000 on the count of 10. As
outputs QA and QD are now both equal to logic “0” as the flip-flop’s have just been reset, the output of
the NAND gate returns back to a logic level “1” and the counter restarts again from 0000.
LOGIC DIAGRAM OF ASYNCHRONOUS DECADE COUNTER USING FLIPFLOP:
TRUTH TABLE:

Output bit Pattern

Clock Decimal
Count Value
QD QC QB QA

1 0 0 0 0 0

2 0 0 0 1 1

3 0 0 1 0 2

4 0 0 1 1 3

5 0 1 0 0 4

6 0 1 0 1 5

7 0 1 1 0 6

8 0 1 1 1 7

9 1 0 0 0 8

10 1 0 0 1 9

11 Counter Resets its Outputs back to Zero

PROCEDURE:
1. Connect the circuit as per the logic diagram.
2. Switch ON the kit
3. Give the input and verify the output with truth table.

RESULT:
Hence an asynchronous counter is realized with flip flop.

VIVA:
1. What is asynchronous counter?
2. What are the advantages of Asynchronous counter?
3. What are the limitations of asynchronous counter?
4. What are the applications of asynchronous counter?
5. What is clock ripple?
 DESIGN AND REALIZATION OF SYNCHRONOUS COUNTER USING FLIFLOPS
AIM:
To study and realize the synchronous up counter and down counter using flip flop

APPARATUS REQUIRED:
1. Digital Trainer Kit
2. Patch cord
3. Power supply
4. IC74LS 10
5. IC74LS73

THEORY:
Asynchronous counter suffers from what is known as “Propagation Delay” in which the timing signal is
delayed a fraction through each flip-flop. However, with the Synchronous Counter, the external clock signal is
connected to the clock input of every individual flip-flop within the counter so that all of the flip-flops are clocked
together simultaneously (in parallel) at the same time giving a fixed time relationship.

In Synchronous Up Counter, the external clock pulses (pulses to be counted) are fed directly to each of the J-
K flip-flops in the counter chain and that both the J and K inputs are all tied together in toggle mode, but only in
the first flip-flop, flip-flop FFA (LSB) are they connected HIGH, logic “1” allowing the flip-flop to toggle on
every clock pulse. Then the synchronous counter follows a predetermined sequence of states in response to the
common clock signal, advancing one state for each pulse.

The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-flop FFA, but
the J and K inputs of flip-flops FFC and FFD are driven from separate AND gates which are also supplied with
signals from the input and output of the previous stage. These additional AND gates generate the required logic for
the JK inputs of the next stage.

If we enable each JK flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q) are
“HIGH” we can obtain the same counting sequence as with the asynchronous circuit but without the ripple effect,
since each flip-flop in this circuit will be clocked at exactly the same time. Because this 4-bit synchronous counter
counts sequentially on every clock pulse the resulting outputs count upwards from 0 ( 0000 ) to 15 ( 1111 ).
Therefore, this type of counter is also known as a 4-bit Synchronous Up Counter.
LOGIC DIAGRAM OF 4-BIT SYNCHRONOUS UP COUNTER USING FLIPFLOP:

TRUTH TABLE:
Clock QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0
LOGIC DIAGRAM OF 4-BIT SYNCHRONOUS DOWN COUNTER USING FLIPFLOP:

TRUTH TABLE:
Clock QD QC QB QA
0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 0 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0

However, we can easily construct a 4-bit Synchronous Down Counter by connecting the AND gates to
the Q output of the flip-flops as shown to produce a waveform timing diagram the reverse of the above. Here the
counter starts with all of its outputs HIGH ( 1111 ) and it counts down on the application of each clock pulse to
zero, ( 0000 ) before repeating again.
PROCEDURE:

1. Connect the circuit as per the logic diagram

2. Ensure the connection is proper before ON the trainer kit

3. Give the clock pulse and observe the output.

RESULT:

Hence synchronous counter is realized with Flip-flops

VIVA:
1. What is meant by synchronous counter?
2. Differentiate synchronous and asynchronous counter.
3. What are the advantages of synchronous counter?
4. What are the applications of synchronous counter?
5. What is the relation between number flip-flops used and number of states in the counter?
EXPERIMENT NO.9 DATE:
DESIGN AND REALIZATION OF 8X1 MUX USING 2X1 MUX
AIM:
To design and implement 8x1 MUX using 2x1MUX.

APPARATUS REQUIRED:-
1. IC74157
2. Bread board/CDTkit.
3. Connecting wires.
4. Power supply.

THEORY:-

The multiplexer or MUX is a digital switch, also called as data selector. It is a combinational circuit with
more than one input line, one output line and more than one select line. It allows the binary information from
several input lines or sources and depending on the set of select lines , particular input line , is routed onto a single
output line.
The basic idea of multiplexing is in which data from several sources are routed to the single output line
when the enable switch is ON. That is how the multiplexers are also called as ‘many to one’ combinational
circuits.

DESIGN:
No. of required input for 8X1 MUX is n1=8
No. of required input for 2X1 MUX is n2=2
In first level no. of 2X1 MUX required M1 =n1/n2=8/2=4
In second level no. of 2X1 MUX required M2=M1/n2=4/2
In third level no. of 2X1 MUX required M3=M2/n2=2/2=1
So total no. of MUX required=4+2+1=7
BLOCK DIAGRAM OF 2X1 MUX:
LOGIC DIAGRAM OF 2X1 MUX:

TRUTH TABLE OF 2X1 MUX:

S D0 D1 Y
0 0 0 0
0 0 1 1
1 1 0 1
1 1 1 1
PIN DIAGRAM OF IC74157:
PROCEDURE:-

1. Connect the circuit as for circuit diagram.

2. Vary the inputs lines (Datalines) and selection lines and observe the output.
3. Verify the truth table for 8x1 mux.
4.

CONNECTION DIAGRAM OF 8X1 MUX USING 2X1 MUX:

TRUTH TABLE:

RESULT:
Hence the verified the truth table of 8x1 MUX using 2x1 MUX.

VIVA:
1. What is Multiplexer?
2. What are the applications of MUX?
3. What is the MUX Size do you need to implement N variable function?
4. Why MUX is called universal Logic circuit?
5. What is DEMUX?
EXPERIMENT NO.10 DATE:
DESIGN AND REALIZATION OF 4 BIT COMPARATOR
AIM:
To study and realize the operation of 4 bit Comparator.

APPARATUS REQUIRED:
1. IC74LS11
2. IC74HC4075 / IC7432
3. IC74LS266
4. IC7485
5. Digital Trainer Kit
6. Connecting Wire
7. Power supply

THEORY:

A magnitude digital comparator is a combinational circuit that compares two digital or binary numbers
(consider A and B) and determines their relative magnitudes in order to find out whether one number is equal, less
than or greater than the other digital number.
Three binary variables are used to indicate the outcome of the comparison as A>B, A<B, or A=B. The
below figure shows the block diagram of a n-bit comparator which compares the two numbers of n-bit length and
generates their relation between themselves.
DESIGN:
It can be used to compare two four-bit words. The two 4-bit numbers are A = A3 A2 A1 A0 and B3 B2 B1
B0 where A3 and B3 are the most significant bits.
It compares each of these bits in one number with bits in that of other number and produces one of the
following outputs as A = B, A < B and A>B. The output logic statements of this converter are

 If A3 = 1 and B3 = 0, then A is greater than B (A>B). Or

 If A3 and B3 are equal, and if A2 = 1 and B2 = 0, then A > B. Or
 If A3 and B3 are equal & A2 and B2 are equal, and if A1 = 1, and B1 = 0, then A>B. Or
 If A3 and B3 are equal, A2 and B2 are equal and A1 and B1 are equal, and if A0 = 1 and B0 = 0, then A >
B.
BLOCK DIAGRAM OF 4 BIT MAGNITUDE COMPARATOR:

LOGIC DIAGRAM:
LOGIC DIAGRAM OF 4 BIT MAGNITUDE COMPARATOR:
 From the above statements, the output A > B logic expression can be written as

The equal output is produced when all the individual bits of one number are exactly coincides with corresponding
bits of another number. Then the logical expression for A=B output can be written as
E = (A3 Ex-NOR B3) (A2 Ex-NOR B2) (A1 Ex-NOR B1) (A0 Ex-NOR B0)
From the above output Boolean expressions, the logic circuit for this comparator can be implemented by using
logic gates as given below. In this the four outputs from Ex-NOR gates are applied to AND gate to give the binary
variable E or A = B. The other two outputs are also use Ex-NOR outputs to generate the Boolean functions as
shown figure.

PROCEDURE:

1. Connect Inputs ( A0,A1,A2,A3,B0,B1,B2,B3) to Input Switches.

2. Connect Cascade Inputs (A<B,A>B,A=B) to Input Switches.
3. Connect Outputs (A<B,A>B,A=B) to Output Switches.
4. Observe the Truth Table.
TRUTH TABLE:

COMPARING CASCADING OUTPUTS

INPUTS INPUTS

A3,B3 A2,B2 A1,B1 A0,B0 A>B A<B A=B A>B A<B A=B
A3>B3 X X X X X X H L L
A3<B3 X X X X X X L H L
A3=B3 A2>B2 X X X X X H L L
A3=B3 A2<B2 X X X X X L H L
A3=B3 A2=B2 A1>B1 X X X X H L L
A3=B3 A2=B2 A1<B1 X X X X L H L
A3=B3 A2=B2 A1=B1 A0>B0 X X X H L L
A3=B3 A2=B2 A1=B1 A0<B0 X X X L H L
A3=B3 A2=B2 A1=B1 A0=B0 H L L H L L
A3=B3 A2=B2 A1=B1 A0=B0 L H L L H L
A3=B3 A2=B2 A1=B1 A0=B0 L L H L L H
A3=B3 A2=B2 A1=B1 A0=B0 X X H L L H

RESULT:

Hence the operation of 4 bit Comparator is verified.

VIVA:
1. What is meant by digital comparator?
2. Differentiate Identity Comparator and Magnitude Comparator?
3. List the applications of Comparator
4. Write the truth table for 2 bit comparator.
5. What is meant by MSB?
EXPERIMENT NO.11 DATE:
VERIFICATION OF TRUTH TABLES AND EXCITATION TABLES

AIM: Truth Table verification of

1) JK Master Slave
2)D-Type
3) T-Type

COMPONENTS REQUIRED:

IC 7408, IC 7404, IC 7402, IC 7400, Patch Cords & IC Trainer Kit. THEORY:
Logic circuits that incorporate memory cells are called sequential logic circuits; their output
depends not only upon the present value of the input but also upon the previous values.
Sequential logic circuits often require a timing generator (a clock) for their operation.
The latch (flip-flop) is a basic bi-stable memory element widely used in sequential logic circuits.
Usually there are two outputs, Q and its complementary value.

Circuit Diagram: - (Master Slave JK Flip-Flop)

D Flip-Flop:-

T Flip-Flop:-

Procedure: -
1. Connections are made as per circuit diagram.
2. The truth table is verified for various combinations of inputs.

Truth Table:- (Master Slave JK Flip-Flop)

Prese Clea J K Cloc Qn+ Qn 1

t r k 1
0 1 X X X 1 0 Set
1 0 X X X 0 1 Reset
1 1 0 0 Qn No
Qn Change
1 1 0 1 0 1 Reset
1 1 1 0 1 0 Set
1 1 1 1 Qn Toggle
Qn
 D Flip-Flop:-
Prese Clea D Cloc Qn+ Qn 1
t r k 1
1 1 0 0 1
1 1 1 1 0

T Flip-Flop:-
Prese Clea T Cloc Qn+ Qn 1
t r k 1
1 1 0 Qn
Qn
1 1 1 Qn
Qn

PROCEDURE:

1.Check all the components for their working.

2.Insert the appropriate IC into the IC base.

3.Make connections as shown in the circuit diagram.

Verify the Truth Table and observe the outputs.

VIVA:

1. What is the difference between Flip-Flop & latch?

2. Give examples for synchronous & asynchronous inputs?

3. What are the applications of different Flip-Flops?

4. What is the advantage of Edge triggering over level triggering?

5. What are the differences between Combinational Circuits and Sequential Circuits?
 Experiment No. : 12
REALIZATION OF LOGIC GATES USING DTL, TTL

AIM:
Design and realize logic gates using DTL, TTL and verify the truth table of
the digital gates using the logic families.

Apparatus -:
S.No. Name of the Component Range Quantity

1 Transistor BC107 2

Resistor 1kΩ 2
2
4.7KΩ 1

3 Diodes IN4007 1

4 Digital Trainer Kit - 1

5 Patch cords - As required

THEORY:

Diode-Transistor Logic (DTL)

DTL Inverter:

The DTL inverter uses a transistor and a collector load resistor as shown in the
 circuit diagram. The input is connected through a pair of diodes in series with the base
of the transistor. The diode connected directly to the transistor base serves to raise the
input voltage required to turn the transistor on to about 1.3 to 1.4 volts. Any input
voltage below this threshold will hold the transistor off. The base resistor is also
connected which should be sufficient to turn the transistor on and off quickly thus
enabling higher switching speeds.

DTL NOR gate:

The emitter-collector junctions of the transistor connect in parallel to the light
emitting diode (LED). When the transistor conducts (ON), it bypasses the current
because almost all the current passes through the emitter-collector junctions, and
therefore the LED goes OFF.
The transistor will conduct when either one or both of the inputs receive a logic 1
signal. When both inputs are logic 0, the transistor stops conducting (OFF) and all the
current passes through the LED instead, hence the LED lights up.

Circuit Diagram of NOT gate:

 Analog and Digital Electronics Lab

Circuit Diagram of NOR gate:

Procedure:
1. Assemble the circuit on your breadboard for NOT/NAND/NOR operation. First,
start with the inverter circuit. Keep this circuit in tact after finishing the inverter
experiment. The rest two circuits can be constructed by just adding extra
components to the inverter circuit.
2. Turn on power to your experimental circuit.
3. Apply all four possible combinations of inputs at A and B from the power supply
using dip switch.
4. For each input combination, note the logic state of the output, Q, as indicated by
the LED (ON = 1; OFF = 0), and record that result in the table.
5. Compare your results with the truth table of a logic NOT/NAND/NOR operation.
6. When you have completed your observations, turn off the power supply.

Department of ECE 71
 Analog and Digital Electronics Lab

Truth Tables:
DTL “NOT” gate Truth Table:

0 1

1 0
INPUT OUTPUT

Department of ECE 72
 Analog and Digital Electronics Lab

DTL NOR gate Truth Table:

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

Transistor-Transistor Logic (TTL)

Transistor-transistor logic uses bipolar transistors in the input and output stages.
TTL is commonly found in relatively low speed applications. Thus before
using commercial ICs that uses TTL, let’s first understand the circuit in
discrete form.

TTL Inverter Circuit

Looking at the DTL inverter circuit, one can note that the two diodes are
opposed to each other in direction. That is, their P-type anodes are connected together
and to the pull-up resistor, while one cathode is the signal input and the other is
connected to the transistor's base. Thus, one can replace these two diodes with a single
NPN transistor as shown in the circuit diagram. This makes lot of sense owing to the
fact that the amount of space required by a transistor in an IC is essentially the same as
the space required by a diode and by eliminating the space required by one diode at the
same time.

Circuit Diagram:

Department of ECE 73
 Analog and Digital Electronics Lab

Procedure:

1. Assemble the circuit on your breadboard for TTL NOT/NOR operation. First,
start with the inverter circuit. Keep this circuit in tact to use it further in NOR
circuit.
2. Turn on power to your experimental circuit. Apply all four possible combinations
of inputs at A and B from the power supply using dip switch.
3. For each input combination, note the logic state of the output, Q, as indicated by
the LED (ON = 1; OFF = 0), and record that result in the table.
4. Compare your results with the truth table of a logic NOT/NOR operation.
5. When you have completed your observations, turn off the power supply.

Truth Tables of NOT gate:

Input Output

0 1

1 0

Result:
Logic gates are designed and realized using different logic families and verified the result.

Viva Questio

Department of ECE 74
Digital Electronics Lab SPEC

1. What are the logic low and High levels of TTL IC’s and CMOS IC’s?

2. Compare TTL logic family with CMOS family? A:

3. Which logic family is fastest and which has low power dissipation?
4. Realize the EX – OR gates using minimum number of NAND gates.

5. Give the truth table for EX-NOR and realize using NAND gates?

75
Digital Electronics Lab SPEC

L.

76
Digital Electronics Lab SPEC

77