IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 37, NO.

3, MARCH 1990 309

A Higher Order Topology for Interpolative

Modulators for Oversampling
A/D Converters
KIRK C.-H. CHAO, MEMBER, IEEE, SHUJAAT NADEEM, WAI L. LEE,
AND CHARLES G. SODINI, MEMBER, IEEE

Abstract -Oversampling interpolative coding has been demonstrated to Anti-alias Fs Digital

LPF I Encodina
be an effective technique for high resolution analog-to-digital (A/D)
conversion that is tolerant of process imperfections. A novel topology for
constructing stable interpolative modulators of arbitrary order is described. Analog Resolution
Processor
Analysis of this topology shows that with proper design of the modulator Input Digital

coefficients, stability is not a limitation to higher order modulators. Fur- (Deamator) output

thermore, complete control over placement of the poles and zeros of the
quantization noise response allows treatment of the modulation process as
a high-pass filter for quantization noise. Higher order modulators are
+
Analog Digital

shown to not only greatly reduce oversampling requirements for high Fig. 1. Block diagram of an oversampling ADC system
resolution conversion applications, but also to randomize the quantization
noise to avoid the need for dithering. An experimental fourth-order modu-
an anti-aliasing filter, sampled by the modulator at a rate
lator breadboard demonstrates stability and feasibility, achieving a W d B
much higher than the Nyquist rate, and converted into a
dynamic range over the 20-lrHz audio bandwidth with a sampling rate of
hgh-speed low resolution digital signal. Further digital
2.1 MHz. A generalized simulation software package has been developed
to mimic time-domain behavior for oversampling modulators. Parameter-
processing reduces the data rate down to the Nyquist rate,
ized models are used for the system elements to determine the effects of
producing the desired h g h resolution digital output.
circuit nonidealities on overall modulator performance. Circuit design
The major advantage of this system is that the modula-
specifications for integrated circuit implementation can be deduced from
analysis of simulated data. tor analog circuit complexity can be greatly reduced if the
encoding is selected such that the modulator only needs to
I. INTRODUCTION resolve a coarse quantization (frequently a single bit) [16].
Also, if oversampling rates are high, the baseband is a
T H E ADVENT of VLSI digital IC technologies has small portion of the sampling frequency. Consequently,
made it attractive to perform many signal processing constraints on the analog anti-aliasing filter can be re-
functions in the digital domain placing important empha- laxed, permitting gradual roll off and easy construction
sis on analog-to-digital (A/D) conversion [l].For h g h with passive components. The precision filtering require-
resolution, band-limited signal conversion applications, ment is now relegated to the digital domain, where a
such as digital audio [2], a number of competing ap- " brick-wall'' anti-aliasing filter is needed to decimate the
proaches have been studied, including floating-point con- digital signal down to the Nyquist rate. Additional benefits
version [3], self-calibration [4], and stochastic techniques can be gained with the digital processor which can also
[5], [6]. This paper investigates a class of oversampled provide on-chp functions such as equalization, echo can-
interpolative converters [7]-[15] that can provide high res@ cellation, etc. Thus this system can provide integrated
lution signal acquisition without precision matching of analog and digital functions and is compatible with digital
analog circuit components. VLSI MOS technologies [17].
A generalized oversampling A/D converter (ADC) sys-
tem is shown in Fig. 1. The input signal is passed through I . I . Delta -Sigma Modulators
Fig. 2 illustrates the simplest form of an oversampled
Manuscript received August 30, 1988; revised August 3, 1989. This interpolative modulator, which features an integrator, a
work was supported by Analog Devices, AT&T Bell Laboratories, DEC,
GE, and IBM. This paper was recommended by Associate Editor T. T. 1-bit ADC and digital-to-analog converter (DAC), and a
vu. summer. This topology, known as the delta-sigma modu-
K. C.-H. Chao was with the Mxrosystems Laboratory, Massachusetts
Institute of Technology, Cambridge, MA. He is now with Lotus Develop- lator [7], uses feedback to lock onto a band-limited input
ment Corporation, Cambridge, MA 02139. X ( t ) . Unless the input X ( t ) exactly equals one of the
S. Nadeem, W. L. Lee, and C. G. Sodini are with the Microsystems
Technology Laboratory, Department of Electrical Engineering and Com- discrete DAC output levels, a tracking error results. The
puter Science, Massachusetts Institute of Technology, Cambridge, MA integrator accumulates the tracking error over time and the
02139.
IEEE Log Number 8933455. in-loop ADC feeds back a value that will minimize the

0098-4094/90/0300-0309$01.00 01990 IEEE

~-
~

- ~~

~ ~~ ~

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 I,

310 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 37, NO. 3, MARCH 1990

n 1-bit

Fig. 2. Block diagram of the delta-sigma modulator.

flfS

Fig. 4. Calculated quantization noise magnitude response IffE( z ) l for

delta-sigma loop.

tions, and 3 ) highly linear converters are possible due to

the inherent linearity of the in-loop l-bit DAC.
I r----1
I DAC
~~
II
The last point above deserves further explanation. The
integral nonlinearity of the in-loop DAC often limits the
I I
harmonic distortion performance of many oversampling
I I
L - - - - l ADC's [ll]. A multibit DAC has many discrete output
Fig. 3. Discrete-time equivalent of delta-sigma loop. The quantizer is levels that must be precisely defined to prevent linearity
modeled by an additive delay-free noise source. For a l-bit quantizer, error. With only two discrete values, a l-bit DAC always
the DAC is replaced by a wire.
defines a linear transformation between the analog and
digital domains. Gain and offset error can still exist in a
accumulated tracking error. Thus the DAC output toggles l-bit DAC, but linearity error is avoided without precision
about the input X ( t ) so that the average DAC output is trimming of output levels.
approximately equal to the average of the input. However, many problems arise when implementing an
The operation of the delta-sigma modulator can be ADC using a delta-sigma modulator. Most prominent is
analyzed quantitatively by modeling the integrator with its that the quantization noise actually is signal dependent
discrete-time equivalent and the quantization process by I211 and not statistically uncorrelated as is usually as-
an additive noise source E ( z ) as illustrated in Fig. 3. E ( z ) sumed. Ths is related to the number of state variables in a
is assumed to be a white and statistically uncorrelated system. For a delta-sigma modulator, the state of the
noise source [18]-[20], which has been shown to be reason- system is determined by the integrator output value along
able under the usual conditions [21]. With t h s linearized with the input value. With only one state variable, the loop
model of the delta-sigma modulator, it can be shown that can lock itself into a mode where the output bit stream
repeats in a pattern. Consequently, the spectrum of the
output will contain substantial noise energy concentrated
Y ( 2 )= X ( z ) z - ' + E ( z ) ( l - z - ' ) . (1)
at multiples of the repetition frequency.
To counter this effect, dithering has been used with
Interpolative modulators are also called " noise-shaping"
delta-sigma modulators to randomize the input so that
coders because of their effect on the quantization noise
repeating bit patterns will not form. However, t h s is not
E ( z ) as seen at the output Y( z ) . A plot of the quantization
an attractive technique as an additional signal source is
noise response JH,(z)J= 1 1- zT1)is shown in Fig. 4. When
required and the input dynamic range is lowered.
the modulator is sampling much higher than the Nyquist
rate, the baseband is in a region where the quantization
noise will be greatly attenuated. Although only a coarse 1.2. Higher Order Loops
quantization is made by the modulator, the bulk of the Candy [22] has done substantial work on a second-order
quantization noise has been pushed to higher frequencies interpolative modulator (the double-loop) based on the
whch can be removed by the subsequent digital processing idea of embedding a delta-sigma loop withn the main
stage. Thus the final output is a high resolution digital loop (Fig. 5). With two integrators in the loop, the quanti-
representation of the input. zation noise response rises as a quadratic function of
The single-bit encoding scheme used by the delta-sigma frequency as compared to the linear relationshp of the
modulator and similar interpolative modulators has a first-order topology. The higher order causes quantization
number of additional advantages: 1) the format is compat- noise to be further suppressed in the low frequency base-
ible for serial data transmission and storage systems, band and to rise more sharply in the higher frequencies.
2) subsequent digital processing can be simplified because The net effect is that the total power of the quantization
multiplications and additions reduce to simple logic opera- noise in baseband is further reduced, and therefore, a

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 CHAO et a[.: TOPOLOGY FOR INTERPOLATIVE MODULATORS 311

n n
+ A I ( I

1-bit
DAC *

higher effective resolution can be achieved for the same

oversampling ratio. The double-loop has been successfully
demonstrated in a number of implementations [22], [23].
Also, due to the two integrators in the loop, repeating bit
patterns are less likely to occur and, as a result, the
quantization noise tends to be less signal dependent. Thus
the double-loop increases the SNR possible for a given Digital Output
oversampling ratio while randomizing the output bit pat- Fig. 6 . Proposed Nth-order loop topology with feedforward and feed-
tern so that noise spikes in the output spectra appear less back coefficients. The A , coefficients implement the poles of the
quantization noise response, and the B, coefficients produce the zeros.
frequently. A z-' delay is associated with the in-loop ADC.
Extending the idea of multiple integration loops, hgher
order loops have proven quite difficult to stabilize [24], but also allows optimizing the quantization noise shape to
[25]. When more than one integrator is in the loop, it is improve performance.
possible for the system to be excited in a mode where a
large amplitude, low frequency oscillation persists in the 2.1. System Function
integrators. Approaches to stabilize the loops have fallen The system function for the topology of Fig. 6 is derived
into two categories: 1) increasing the size (number of bits) by replacing the integrators with their discrete-time equiva-
of the in-loop ADC-DAC to allow a greater dynamic lents and by modeling the in-loop ADC as an additive
range of signals in the loop [26], and 2) cascading multiple noise source E ( z ) [22]. A linear model is used to facilitate
stages of first-order delta-sigma modulators [25], [27]. design of the loop coefficients, whch will be subsequently
In the first case nonlinearities in the inloop multibit described. The DAC is assumed to be ideal and delayless,
ADC-DAC become the limiting factor for overall resolu- but a z - l delay is associated with the ADC. The resulting
tion while component mismatches in multistage modula- system function can be expressed as a combined response
tors determine the resolution for the second case. to the input X ( z ) and the quantization noise E ( z ) ;
y ( z )= H X ( Z ) X ( Z ) + E l , ( z ) E ( z ) (2)
11. ANALYSIS
OF NTH-ORDER
TOPOLOGY
where
The Nth-order interpolative modulator to be described
is shown in Fig. 6. It is important to note that linear 1HA4
analysis is used only to determine a starting point for
- C L O A l ( Z- 1 y
modulator design. Further design refinements and verifica- -
tion is accomplished through software simulations and a z [ ( z - 1) - E:;N=,B,( z - 1)N - z ] + C:,N_,A,( z - 1)
breadboard circuit implementation.
While this paper concentrates on the results of a fourth- (3)
order implementation, the analysis and design techniques HEW
discussed here apply equally well to other order topologies.
The salient features of this topology are the feedforward - ( z - 1) -C;N_,B, ( z - 1)
structure with loop coefficients A,; . -,A , and a feedback [
z ( z - 1) -Z:;N=p1(z - 1) , - I ] +C,N_,A,(z - 1 y - I .
structure with coefficients Bo, * , B,. The in-loop quan-
tizer' is reduced to a single bit for previously cited reasons. (4)
As will be demonstrated, the large number of loop coeffi- To gain an intuitive understanding of the system function,
cients not only allows one to stabilize loops of any order, it is helpful to consider the case where the feedback
coefficients B , , . . B , are set to zero. With this assump-
e ,

tion, (2) can be simplified for the case of low frequency

'The term quantizer refers to a cascaded ADC-DAC combination. The baseband signals by noting that ( z - 1) = js2 and Ijs2 I << 1
input and output are both analog signals which differ by the error due to where s2 = 277(f/f,); f, is the sampling frequency and f is
the quantization process.

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 312 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 3 7 , NO. 3, MARCH 1990

l . , . . . , . . . I , . . ,I , , ,
in baseband. However, suppressing quantization noise in
- the low frequency baseband produces the adverse effect of
0 0
O O O
increasing the quantization noise level at higher frequen-
Q O O - cies. Also, the quantization noise response must not be
0 0
allowed to approach 2 at h g h frequencies, otherwise the
0
0.4
0
- stability of the loop will be jeopardized.
E
a 0 0 Many methodologies can be used to determine the z-
0.2 - domain pole-zero values for H E ( z ) . Once the pole-zero
locations are known, it is a simple matter to determine the
OC ” m
_ e.
Ll loop coefficients. We have chosen to use a Butterworth
t.1
1.2
. . . I
1.4
. ~ .
1.6
I . . .
1 .a
I , . .
2
I . 1
filter design because of its flat characteristics and its
relative insensitivity to coefficient errors.
Maximum IHe(z)[
2.3.1. A , Coefficients: Again, it is useful to consider the
Fig. 7. Simulated dc input range of a fourth-order loop for various
values of IHE(z)l. With zero input, the loop becomes unstable when case where the B, coefficients are set to zero and to first
IHE(z)l > 2. The vertical axis is normalized to quantizer step-size. concentrate on the A , coefficients. The process involves
computing the s-domain poles, then translating them into
the z-domain with a bilinear transform. Once the desired
the frequency of interest. The system response reduces to values of the z-domain poles are known, values for
A,; . . , A , can be determined as follows. Let H,( z ) be
the desired N th-order response defined as
(5)

which shows that when N is sufficiently greater than 1 and

the oversampling ratio is large, i.e., ljQl << 1, the quantiza-
tion noise E ( z ) is greatly attenuated. T h s demonstrates where pl, p 2 ; . ., p , are the z-domain poles. Equation (6)
the accurate tracking aspect of the modulator for low can be related to H E ( z )by the simple relationship
frequency signals.
H,(Z) =zH,(z). (7)
2.2. Stability Expansion of the denominator terms gives
For a sampled-data system, stability requirements dic-
tate that the poles be placed within the unit circle. Since K(z-l), - Z(Z-l),
-
the loop coefficients can be designed to have arbitrary z + zNP1C,_, + . . . + CO zN+l + z N D N+ . . . + Do
values, the poles can be placed anywhere on the z-plane. (8)
The absolute control over the location of the poles will
allow not only the design of stable loops but also the where C, and D, are coefficients resulting from the expan-
optimization of the loop response for maximum effective sion. Equating similar denominator terms produces a set of
resolution. In most cases, requirements on the precision of linear equations which determine the A , coefficients. For
the coefficients to obtain an optimized quantization noise the case N = 4, K = 1, and s-domain poles at - 1.8074 k
response exceeds the requirements for a stable system. 0.7486j, - 0.7486 1.8074j rad, the resulting A , coeffi-
Another mechanism for instability is due to the limited cients are
input range of the quantizer [15] which places further A, = 0.8653
constraints on the design of the loop filter [28]. A signal at
the input of the quantizer which exceeds the quantizer A , = 1.1920
limits is reflected by an increase in the amount of quanti- A, = 0.3906
zation noise I E ( z) I. This excess noise is circulated through
the loop and can cause an even larger signal to appear at A , = 0.06926
the quantizer input, eventually causing instability. For a A, = 0.005395.
fourth-order loop, it has been determined through simula-
tions that IHE(z)l < 2 for IzI =1 at h g h frequencies is a 2.3.2. B, Coej”ficients: In the section above, all the zeros
necessary condition for stable operation with zero input. of the quantization noise response H E ( z ) reside at dc
Applying an input to the system raises signal levels in the (z = 1). As a consequence, the noise response rises mono-
loop [28], [29], hence, IHE(z)l must actually be less than 2 tonically out of baseband as an N-th order function. One
for the modulator to remain stable (Fig. 7). finds that a small portion of the noise spectrum at the
upper edge of baseband will dominate the total in-band
2.3. Design of Loop Coefficients noise energy. It is apparent that further shaping of the
Treating the loop as a quantization noise filter allows quantization noise will improve performance and this can
linear filter design techniques to be used. The primary be accomplished by using the B, coefficients to move the
design criteria is to minimize the quantization noise energy zeros away from dc.

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 CHAO et U [ . ; TOPOLOGY FOR INTERPOLATIVE MODULATORS 313

20
0
, , , ,
2.5E5
, I , ,
5E5
I I 7 I
7.5E5
I I I ',
1E6

20
Sampling Ratio (fslfb)

100
140
0

-20 120

40 100

-60
80

-80
60
-100
1 E4 2E4 3E4 4E4
40
Frequency (Hz) 0.4 2 10

Fig. 8. Calculated quantization noise spectrum for a fourth-order loop. Sampling Freq. (MHz),fb=20 kHz
The loop coefficients implement a Butterworth high-pass response with
Chebyshev rippling in the baseband region. Top axis is from 0 to 1 Fig. 9. Calculated effective resolution as a function of oversampling
MHz: bottom axis shows details from 0 to 40 kHz. ratio and modulator order for various order loops.

The methodology developed here is to use the equal- in baseband, which is given by
ripple characteristics of the Chebyshev polynomials. These
polynomials are defined by
T,(x) =1
T I (x ) =x

TN( x ) = 2xTN_1 ( x ) - T N - 2 ( x ) .

What makes them special is that \TN(x)l<1 for 1 x 1 ~ 1 ,

and IT,(x)l > 1 for 1x1 > 1. T h s property of the Cheby- (11)
shev polynomials can be used to define a desired baseband
response through proper scaling. For the case of large It has been shown that for delta-sigma modulators E(f)
oversampling rates, i.e., f,, f,, where f h is the baseband can be modeled as an additive white noise source of
frequency and f, is the sampling frequency, the desired magnitude [18]-[ZO]:
z-domain zeros z , are located at
z, = eJznx~fh/fr (9)
where X , are the roots of T N .The B, coefficients can then
be determined using the method outlined above for deter- where eo is the average quantization noise and is related to
mining the A , coefficients. For f, = 2.1 MHz and f,, = 20 the quantizer step size D by
kHz, the resulting B, coefficients are U

B,= -3.540X10-3 eo= J12

B, = - 3.542 X Equation (10) has been evaluated and is graphically pre-
B , = -3.134X10-6 sented in Fig. 9. As the modulator order increases, the
lines become steeper, implying a greater payoff from over-
B4= -1.567X10-6. sampling. For 96-dB resolution across the 20-kHz audio
A plot of the quantization noise response for a N = 4 loop range, Fig. 9 shows that a second-order loop requires a
implementing the above coefficients is shown in Fig. 8. sampling rate of 5 MHz, whereas a fourth-order modulator
From above and from (4), it is apparent that the zeros requires only 2 MHz. In this case, the additional analog
only depend on the B, coefficients. The zeros will usually circuit complexity of two integrators can reduce the sam-
be located near z = 1 because of high oversampling ratios, pling rate by a factor of 2.5.
ensuring that the B coefficient values will be small. The
effect of B coefficients in determining the A coefficients is RESULTS
111. SIMULATION
then negligible. Thus for large oversampling ratios, the B Linear analysis is a useful tool for gaining intuitive
coefficients determine the zeros and the A coefficients understanding of modulator operation and for designing
determine the poles of the quantization noise response. the loop coefficients. However, for nonlinear circuit ef-
fects, linear analysis is inappropriate. To tackle this prob-
2.4. Quantization Noise lem, a generalized software simulator has been developed
The effective resolution of the modulator can be calcu- to study nonlinear circuit effects. The simulator mimics
lated by evaluating P 2 , the total quantization noise power circuit behavior in the discrete-time domain [17] with

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 I,

314 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 37, NO. 3, MARCH 1990

Inputs

Sinusold

DC

Dither

Module
Librarv

Fig. 10. Block diagram of the generalized oversampling modulator sim-

ulation system.

.3.
0
0

-50 1
c
I

I
I I

Input Signal Amplitude [Normalized to DAC)

Fig. 12. Simulated SNR versus relative input amplitude for fourth-order
loop showing effects of finite op-amp gain. Sinusoidal input dc offset
= 0.02, frequency = 6.1 kHz, clock = 2.1 MHz, and oversampling ratio
.rnE -100 = 48.

2
-150 window (von Hann). Various simulation results are pre-
sented in the following sections for the fourth-order modu-
lator previously described.
-200
100 1000 1E4 1E5 1E6
3.1. Finite Op-amp Gain
Frequency (HZ)
Finite op-amp gain causes the inverting op-amp termi-
Fig. 11. Typical simulation spectrum of an ideal fourth-order loop.
Sinusoidal input with amplitude = 0.1 (normalized to DAC output), dc nal to reflect the output voltage rather than behave as a
offset = 0.02, and frequency = 6.1 kHz. The clock/sampling frequency virtual ground. Consequently, not all of the charge on the
is 2.1 MHz. Note the rippling in the baseband noise floor due to the
optimized zeros. sampling capacitor will be transferred to the integrating
capacitor, resulting in a “leaky” integration. This effect is
still a linear process and can be incorporated into the
modules that model block-level circuit functions. Each linear S-C integrator model by the addition of leakage and
model contains associated nonidealities so that the effect integration gain coefficients. In the system function, inte-
of each nonideality can be examined. The modules can gration gain errors are manifested as errors in the loop
then be connected, via software, to simulate almost any coefficients.
topology for oversampling modulators. T h s simulator is The effect of finite op-amp gain on fourth-order modu-
especially useful for CMOS implementations of oversam- lator performance can be seen in the SNR curves of Fig.
pling modulators, in which many analog functions are 12. For op-amp gains less than 200, the performance has
performed in discrete time. degraded by about 2 dB. However, with gains of 1000 or
Fig. 10 shows the different blocks of the simulation more, the performance is nearly ideal. This is especially
system. The user defines a modulator topology composed important for MOS implementations, since amplifier gains
of modules from a library and sets parameters that control of 1000 are easily achievable.
nonideal circuit behavior. With an input signal injected
into the simulator, a long output stream from selected 3.2. Integrator Settling Time
circuit nodes is generated. This output data can be pro- Typically, oversampled modulators are operated with
cessed with a fast Fourier transform (FFT) to reveal spec- clock frequencies over 1 MHz, thus settling becomes an
tral content. Further post-processing yields performance issue in determining performance. T h s is especially true
measurements, such as SNR. for switched-capacitor implementations, where each inte-
Discrete-time simulation of a sampled-data system can grator can be expected to step to a new output level during
greatly simplify modeling of circuits, since only nodal every clock cycle. If the integrator is modeled as a single-
values at sampling points are of interest. What happens at pole system, then step responses will be exponential in
a node in-between clock edges is usually irrelevant, as long nature. The fractional error introduced by this response is
as the proper value at the sampling point is produced. This
simulator contains models for various switched-capacitor ‘actual - ‘step

integrators, quantizers, summers, gain blocks, etc. A repre-

= - exp ( - T , / - r ) , for Ktep< TS,
Ktep
sentative sampling of nonidealities include finite op-amp (14)
gain, settling time, nonlinear capacitors for integrators,
hysteresis of comparators, and nonlinear DAC’s. where T, is sampling period, T the time constant of the
A typical spectrum of the modulator’s output bit stream exponential response, and Ktep the output step size. Thus
is shown in Fig. 11. For all simulations, the FFT’s were for a given c,
c remains constant. However, if the step size
performed on over 32 000 data points using a raised-cosine is sufficiently large, then slewing occurs and the integrator

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 CHAO et ul. : TOPOLOGY FOR INTERPOLATIVE MODULATORS 315

l l o l I I I I I I , I I 1 100, , , , , ,., , , , , , , ~ , ,
loo-- :;510 v/us
90-
80
70
60
50
t \
40
30
20
10

0
-120-110-100 -90 -80 -70 -60 -50 4 0 -30 -20 -10 0 10
5E-5 1E 4 1.5E-4

Input Signal Amplitude (Normalized to DAC) Time (S)

Fig. 13. Simulated integrator settling time results for various slew rates, (a)
T = 13 ns, T, =lo0 ns, and DAC step-size = 5. The worst case ( S , =,lo
V/ps) performance is caused by slewing during the entire sampling _.___
into
period for large steps. ..... .........
~ intl
int2
I - - in13 i

will settle with a combination of slew and exponential

characteristics. The fractional error in this case is
0

t
for 7 s R < Kpp < (7 + Ts)sR (15)
where S, is the slew rate of the loaded op-amp. With this -1
SE-5 1E 4 1.5E-4
model, a set of SNR curves for various slew rates (Fig. 13)
was produced. The parameters used in this experiment Time (S)

were calculated from SPICE simulation results of an inte- (b)

grator design operating under worst-case conditions. As Fig. 14. Simulated integrator outputs for fourth-order loop. Sinusoidal
input amplitude = 0.1, dc offset = 0.02, frequency = 6.1 kHz, and clock
can be seen, settling time for a first-order step-response = 2.1 MHz. (a) Integrator gain = 1. (b) Gain = 0.2.
only affects performance for lower slew rates. The slewing
introduces nonlinear effects, yet the values of the percent-
age errors for the higher slew rates are so small as to be system. Errors from process mismatch change the coeffi-
negligible. cient values and cause performance degradation. Toler-
ances to each coefficient were determined and are listed in
3.3. Limited Op-amp Swing
Table I. As can be seen, 5 to 30-percent errors in each
The effect of limited output swing has already been coefficient can be tolerated for a 3-dB loss of dynamic
documented [17], [30]. Because the integrators contain range.
state information, clipping of output levels will cause loss
of state information, thus performance will be degraded.
For higher order loops, this is a serious problem because 3.5. DC Idle-Channel Noise
the last integrator has very large signal swings. A solution One major problem with first- and second-order loops is
is to design the discrete-time integrators with time constant that their quantization noise is highly dc-bias dependent
less than unity, thereby attenuating the signal levels at the [18], [31]. The first-order system contains only one state
integrator outputs. T h s attenuation is then compensated variable, thus it is very likely that repeating bit patterns
by multiplying the values of the A , and B, coefficients so will be produced. In a second-order system, somewhat
that the overall loop transmission remains the same. Fig. better performance is possible because the states are more
14(a) shows superimposed images of the four integrator random, hence, quantization noise is less signal dependent.
outputs without the “gain compensation,” and Fig. 14(b) Presumably, for a fourth-order system, even better ran-
shows the same outputs with the “gain compensation.” domization should be acheved. This is indeed the case and
Clearly, the last integrator now has signal levels well is reflected in the flatness and lack of noise spikes with dc
within the maximum swing bounds. Thus with proper inputs as shown in Fig. 15. Thus no dither signal is
system design, output swing is not a limitation for this necessary.
topoiogy . Thus from a system viewpoint, the fourth-order loop is
quite immune to many nonidealities and does not suffer
3.4. A , and B, Coefficient Errors from the dc bias problems associated with lower order
As mentioned in the preceding section, the A , and B, systems. These simulation results have been used to deter-
coefficients determine the pole and zero locations of the mine the design specifications for a CMOS implementa-

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 ,

316 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. VOL. 31, NO. 3, MARCH 1990

-10 - -
-20 - -
-30 ,- h 7

4oLPl
-50 r 4

'i
-100
-110

""-m1
-1 20

-140 -0.5

input Signal Amplitude (Normalized to DAC)

0.5

Fig. J5. Simulated fourth-order loop dc idle-channel noise. The lack of

noise spikes within the valid input region indicates signal-independent
noise. Fig. 16. Output spectrum of breadboard fourth-order loop showing
quantization noise around the baseband region (0-40 kHz). Clock rate
is 2.1 MHz. Input is a 10-kHz sinusoid with amplitude of - 70-dB full
TABLE I scale.
MAXIMUM ERRORTOLERANCES OF A, AND B, COEFFICIENTS
WHICH
WILLCAUSELESSTHAN 3 DB Loss OF DYNAMIC RANGE
__ Harmonic Distortion
Coefficient Butterworth Elliptic I Coefficient Butterworth Elliptic A Random Noise
I
Ao 5% 5%
Ai 10% 5% Bl 30% 30%
A2 20% 10% Bz 10% 10%
As 30% 20% B3 30% 20%
A4 20% 20% 30% 30%

tion of a fourth-order modulator for digital audio applica-

tions. O0
, l o ~ i , I , , , , I 0
-100 -80 -60 -40 -20 0
IV. EXPERIMENTAL
RESULTS Input Amplitude, dB
In order to verify the results of the theoretical analysis Fig. 17. Measured SNR of breadboard as a function of input ampli-
and demonstrate the robustness of the topology, an experi- tude. Random noise and harmonic distortion components are mea-
sured separately. Input frequency is 5 kHz.
mental fourth-order modulator has been constructed from
discrete components. The breadboard consists of continu-
ous-time integrators, summers, a comparator, and a 1-bit
current DAC. T h s breadboard operates at a clock fre-
quency of 2.1 MHz and implements the Buttenvorth- $ -60
Chebyshev loop filter already described. 5 -70

To make signal-to-noise measurements, a sinusoidal sig- 0

6 -90
nal is fed into the modulator and the output is examined. U -100
However, in order to maintain the effectiveness of a spec- U
- -110
I -5 0 5 I
trum analyzer, the square-wave output of the modulator DC Input Bias
must first be low-pass filtered to remove the high fre- Fig. 18. DC idle-channel noise of breadboard as a function of input
quency components. In addition, limited dynamic range of level (normalized to DAC output).
the spectrum analyzer necessitates use of a notch filter to
remove the signal component when making baseband noise
measurements. percent total harmonic distortion for inputs smaller than
Fig. 16 is an output spectrum of the modulator. Notice - 3 dB and less than 0.01 percent total harmonic distor-
the large amount of quantization noise, except in baseband tion for inputs smaller than -21 dB. Fig. 18 shows the
where it is greatly suppressed by the response of the loop. modulator noise characteristic as a function of dc input
A 10-kHz input signal component is also shown with no level which does not exhibit the sharp increases in output
harmonic distortion visible, revealing the extreme linearity noise at various dc input levels that are a problem for the
of the modulation process. As mentioned in the introduc- first- and second-order loops. The reason the theoretical
tion, the excellent linearity is aided by the use of a 1-bit noise limit for the fourth-order modulator was not achieved
DAC which is inherently linear because it has only two is attributable to clock jitter. Since the DAC in the contin-
discrete output levels. Measurement of the SNR as a uous-time implementation returns a current signal which is
function of input signal amplitude is shown in Fig. 17. It integrated by the loop, any jitter in the clock signal ap-
indicates a dynamic range of 90 dB with less than 0.1 pears as noise at the input.

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 I

CHAO et al.: TOPOLOGY FOR INTERPOLATIVE MODULATORS 317

Using real audio sources as an input to t h s system has with z-domain pole-zero locations at
produced very good results. For this listener’s ears, the
pi= 0.9138+0.2500j, 0.6970k0.1964j
sound quality was “excellent” with no discernible underly-
ing tones, which would occur if signal-dependent nonhar- z , = 0.9985+0.0550j, 0.9997k0.0230j.
monic noise were being generated. Stability was main- The resulting A loop coefficients are
tained, with the modulator faithfully trackmg the input
signal. A, = 0.77486

A , = 1.07610
V. CONCLUSIONS
A, = 0.36610
The analysis of a novel Nth-order interpolative modula-
tor topology has been presented. It reveals that with proper A , = 0.07398
design of feedforward loop coefficients, stability is not a A, = 0.00912
limitation to higher order modulators. The loop stability is
determined primarily by the feedforward coefficients, while and the B coefficient values are
feedback coefficients may be added to optimize quantiza- B, = - 0.003558
tion noise response in the baseband, thereby improving
B2 = - 0.003559
performance. A design methodology for a quantization
noise-shaping filter has been described. Measured results B, = - 0.00000323
of 90-dB SNR for an experimental fourth-order modulator B4 = - 0.00000161.
demonstrates the feasibility and robustness of the topol-
From simulation results, the elliptical filter implementa-
ogy.
A generalized software simulation package has been tion was more susceptible to instability for a given pertur-
developed to mimic ideal and nonideal circuit behavior. bation of A , and Bi coefficients as compared with the
With this package, system level design specifications for Butterworth-Chebyshev implementation. This fact has
various modulator components may be determined. been summarized in the results of Table I, which show a
tighter constraint on the allowable errors for the elliptical
APPENDIX case.
ELLIPTICAL
FILTERIMPLEMENTATION
ACKNOWLEDGMENT
The quantization noise response can also be designed
using elliptical filter design techniques. An elliptical filter The authors gratefully thank Prof. H.-S. Lee for his
has the “optimal” characteristics of maximum attenuation insights throughout thus project. Special thanks go to Prof.
and sharpness of transition region for a given filter order. Bruce Musicus, Prof. John Wyatt, and Lloyd Clark for
The design is easily accomplished using a common ellipti- their helpful discussions.
cal filter design program [32], which gives the pole-zero REFERENCES
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 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. VOL. 37, NO. 3, MARCH 1990

S. K. Tewksbury and R. W. Hallock, “Oversampled, linear predic- Shujaat Nadeem received the B.S. and M.S.
tive and noise-shaping coders of order N > 1,” I E E E Trans. Circuits degrees in electrical engineering from Mas-
S - V S ~vol.
. , CAS-25, pp. 436-447, July 1978. sachusetts Institute of Technology, Cambridge,
W. L. Lee and C. G. Sodini, “A topology for lugher order inter- in 1989. He is currently working towards the
polative coders,” in Proceedings 1987 Int. Synip. on Circuits and Ph.D degree in electrical engineering at Mas-
Systems, pp. 459-462, May 1987.
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for high resolution oversampling A/D converters,” Master’s thesis, interests are in the area of high performance
MIT, Cambridge, MA, 1987. analog circuits using CMOS and BICMOS tech-
J. R. Fox and G. J. Garrison, “Analog to digital conversion using nologies.
sigma-delta modulation and digital signal processing,” in Proc. Mr. Nadeem is a member of Tau Beta Pi, Eta
M I T VLSI Conf., pp. 101-112, Jan. 1982. Kappa Nu, and Sigma Xi.
M. W. Hauser and R. W. Brodersen, “Circuit and technology
considerations for MOS delta-sigma a/d converters,” in Proc. I986
Int. Symp. on Circuits und Systems, pp. 1310-1315, May 1986.
J. C. Candy, “The structure of quantization noise from sigma-delta
modulation,” I E E E Trans. Commun., vol. COM-29, pp. 1316-1323,
Sept. 1981.
W. R. Bennett, “Spectra of quantized signals,” Bell Svst. Tech. J . ,
vol. 27, pp. 446-472, July 1948.
D. J. Goodman, “Delta modulation granular quantizing noise,”
Bell Syst. Tech. J . , pp. 1197-1218, May 1969. 9
R. M. Gray, “ Oversampled sigma-delta modulation,” I E E E Trans.
Commun., vol. COM-35, pp. 481-489, May 1987.
J. C. Candy, “A use of double integration in sigma delta modula-
tion,” I E E E Trans. Commun., vol. COM-33. pp. 249-258. Mar.
1985.
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S. H. Ardalan and J. J. Paulos, “Stability analysis of hgh-order
sigma-delta modulators,’’ in Proc. 1986 Int. Svmp. on Circuits and Wai L. Lee received the B.S. and M.S. degrees from Massachusetts
Systems, pp. 715-719, May 1986. Institute of Technology in 1987.
Y. Matsuya, K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa, His interests include analog circuits, high-speed arithmetic logic, and
and T. Yoshitome, “A 16-bit oversampling A-to-D conversion computer architectures.
technology using triple integration noise shaping,” IEEE J . Solid-
State Circuits, vol. SC-22, pp. 921-929, Dec. 1987. Mr. Lee is a member of Eta Kappa Nu.
M. J. Hawksford, “N-th order recursive sigma-ADC machinery at
the analogue-digital gateway,” presented at Audio Engineering
Society Convention, May 1985.
T. Hayashi, Y. Inabe, K. Uchimura, and T. Kmura, “A multistage
delta-sigma modulator without double integration loop,” in ISSCC
Dig. Tech. Pupers. pp. 182-183, Feb. 1986.
S. H. Ardalan and J. J. PaElos, “An analysis of nonlinear behavior
in delta-sigma modulators, IEEE Trans. Circuits und S y s t e m , vol.
CAS-34, pp. 593-603, June‘J987. 9
C. Wolff and L. R. Carley, Modeling the quantizer in higher-order
delta-sigma modulators,” in Proc. 1988 Int. S.vmp. on Circuits und
Svstems, June 1988.
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sigma-delta modulator,” in ISSCC Dig. Tech. Pupers. pp. 258-259,
Feb. 1988.
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Systems, June 1988.
A. H. Gray, Jr. and J. D. Markel, “A computer program for Charles G. Sodini (S’80-M’82) received the
designing digital elliptic filters,” IEEE Trans. Acoust. Speech, B.S.E.E. degree from Purdue University,
Signul Processing, vol. ASSP-24, pp. 529-538, Dec. 1976. Lafayette. IN, in 1974, and the M.S.E.E. and
Ph.D. degrees from the University of California,
Berkeley, in 1981 and 1982, respectively.
He was a member of the technical staff at
9 Hewlett-Packard Laboratories from 1974 to 1982,
where he worked on the design of MOS memory
and later on the development of MOS devices
with very thin gate dielectrics. He joined the
Kirk C.-H. Chao (S’86-M’88) received S.B. and faculty of the Massachusetts Institute of Tech-
S.M. degrees in electrical engineering from the nology, Cambridge. MA, in 1983 where he is currently an Associate
Massachusetts Institute of Technology, Cam-
Professor in the Department of Electrical Engineering and Computer
bridge, MA, in 1986 and 1988, respectively.
Science. His research interests are focussed on IC fabrication, device
Currently, he is consulting and developing
modelling, and device level circuit design, with emphasis on analog and
software for Lotus Development Corporation. memory circuits.
Cambridge. MA. Dr. Sodini was awarded the IBM Faculty Development Award from
Mr. Chao is a member of Tau Beta Pi and Eta 1985 to 1987. He has served on a variety of IEEE Conferene Committees
Kappa Nu. including the International Electron Device Meeting where he served as
the 1989 General Chairman.

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