2012 International Conference on Optoelectronics and Microelectronics (ICOM)

16-Bit Delta-Sigma DAC with

Cascade-of-Resonators Feed-Forward Modulator
and Interpolation Filter with OCSD Code
Yongsheng Wang*, Mengye Cai, Yonglai Zhang, Mingyan Yu
Micro-electronic department
Harbin Institute of Technology
Harbin, China
[email protected]

Abstract-A 16-bit 5.6-MHz clock-rate digital to analog filter is powerless to remove the images produced in first
converter (DAC) achieves 96-dB signal-to-noise rate (SNR) in interpolation due to its inherent properties. As the reason of
the 22-KHz band. The optimal canonic signed digit (OCSD) that, a low-pass digital filter is presented in interpolator
code is proposed in a multi-stage interpolator filter to achieve filter. The classical CSD code is usually adopted in
less hardware consumption. A third-order
interpolator filter [4-6]. For saving hardware overhead
cascade-of-resonators feed-forward (CRFF) with zero
optimization Delta-Sigma modulator has been developed to further, the concept of optimal OCSD code is proposed in
convert an oversampled digital signal into 1-bit code. A this paper.
switch-capacitor (SC) analog filter is used to reconstruct the This paper explores how these blocks can be employed
analog signal. effectively in DAC to extend the resolution that can be
achieved beyond that of Nyquist-rate converters. Folded
Keywords-Delta-Sigma mudulator; interpolation
filter;reconstruction analog filter structure are used to optimize the interpolator filter. The
zero optimazation structure for noise-shaping loop is
I. INTRODUCTION employed and the realizability in hardware is considered.
The fast growth of the audio products has increased the II. DELTA-SIGMA MODULATOR WITH CRFF STRUCTURE
demand for the digital-to-analog converter(DAC) that meets
high degree of accurancy and achieves wide dynamic A. System Modeling
range[1]. Delta-Sigma DAC takes extensive use of digital Delta-sigma modulator is the most crucial part of the
signal processing, taking advantage of the fact that VLSI is whole system, because its proporties decide the scope and
better suited for providing fast digital circuits than for compexity of the digital interpolator filter and analog
providing precise analog circuits ， so the Delta-Sigma reconstruction filter.
modulator and interpolator filter are implemented in digital The main specifications of a modulator are OSR, the
area. Delta-Sigma DAC is composed of an interpolator filter, order of noise-shaping loop, feedback types and output bits
a Delta-Sigma modulator, releasing in digital techonology, of quantizer. The OSR is always chosen as integer power of
and an analog reconstrction filter. 2. To be more specific, a low OSR is not sufficient to meet
There have been several approaches to realize the system requirements. Whereas, a very high OSR makes
Delta-Sigma modulator. A feed-back structure of the fifth analog filter work in a high frequency, that generates more
order Delta-Sigma modulator is presented in [2]. Compared power consumption. Finally, 128 of the OSR is chosen in
with feed-back modulator, feed-forward topology reduces this design. On the other hand, multi-bit quantizer can
swings of internal signals because only quantized noise achieve higher SNR, but the overall modulator linearity and
existing in every integrator’s output, which is easier to keep resolution are limited by the precision of the multi-bit DAC,
Delta-Sigma modulator stable. Meanwhile, the signal as the reason of that, single-bit quantizer is inherent
transfer function (STF) of full feed-forward modulator is linearity and is adopted in this scheme.
unity under ideal circumstances and the NTF doesn’t To sum up, considering the power consumption,
contain any pole. stability, resolution and complexity, at this ratio, as fig.1
The second stage of interpolator filter is usually depicts, a third-order cascade-of-resonators feed-forward
realized by half-band filter [3]. It can achieve upsampling delta-sigma modulator introducing zero optimization has
ratio and take away the images as well. Nevertheless, as for been developed to convert an oversampled input digital
the Delta-sigma DAC system, the digital input are always signal in this paper.
quantized signals which would inevitably contain DC
components. It is can not ignored because another half-band

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 2012 International Conference on Optoelectronics and Microelectronics (ICOM)

III. INTERPOLATOR FILTER WITH OCSD CODE

A. System modeling
z −1 z −1 z −1
1 − z −1 1 − z −1 1 − z −1 In the frequency domain, FIR filter can remove the
image frequency out of baseband. In this design,
interpolation factor can be divided into several parts to
fulfill the performance and it is also used in many contexts.
In order to achieve an ideal effect, for the digital filter, the
stop band attenuation should reach at least 85dB and the
pass-band ripple is controlled below 0.006dB. The OSR
factor can be accomplished by processing the input signal
Fig.1 Delta-sigma modulator structure
with three-cascade filters. It consists of a half-band filter, a
B. Optimization and implementation low-pass filter and the cascaded integrator comb (CIC) with
The feed-back loop realizes the zero optimization that the upsampling ratio of 2、2 and 32 respectively.
could distribute zeros in NTF (Noise Transfer Function) (1) half-band filter
throughout base band, which will enhance the suppression The first stage is realized by half-band filter because it
of noise around the bandwidth frequency. The NTF of this saves half of coefficients in realizing the same frequency
modulator is as followed. response compared with other filter. It also avoids
2
(z −1)(z −2z +1−ac )
approximately half the number of multiplication. The first
H(z) = 3
(1) stage increases clock frequency to 2f and remove images
3 2
z −(3+ab
1 1
)z +(3−ac
3
+2ab
1 1
−aab
1 2 2
)z +ac
3
−ab
1 1
+aab
1 2 2
+aabc
1 3 1
−aab
1 2 3
−1 beyond signal baseband, so it has the narrowest relative
Hardware implementation should be considered before transition band which needs greater hardware consumption,
the coefficients are decided. The trade-off between peak so the pass-band ripple can be relaxed as 0.007dB and be
SNR and consumption are taken into account as well. At the enhanced in the next stage. The transition band of half-band
same time, the stablity and perfomance of Delta-Sigma filter is designed at 0.4535π∼0.5465π. The filter is realized
modulator should be verified in Matlab environment. by 86-tap providing 70dB stop-band attenuation.
Behavioral simulations show the range of input sine wave (2) low-pass filter
should be below 0.8 of the full scale in order not giving rise A low-pass filter is used in this paper, despite the
to vibrate. The Optimized Coefficients are showed in increase in non-zero tap coefficients will increase the area
table.1, the power spectral density (PSD) of the output of the digital interpolation filter, but it can set aside a larger
signal is depicted in fig.2. The SNR of inband signal noise margin and reduce the requirements of analog
reaches 109dB, the 2nd an 3th harmonic distortion are reconstruction filter.
below -120dB, the effects of zero optimazation and Signal sampling ratio is increased to 4f after the second
quantizing noise modulation are clearly observed. stage and images produced by the first and second
interpolation are removed by low-pass filter. The transition
TABLEⅠ. OPTIMIZED COEFFICIENTS band of low-pass filter is designed at 0.25π∼0.4545π. The
a1 a2 a3 c filter is realized by 36-tap providing 50dB stop-band
-0.25 -0.25 -0.25 attenuation. The pass-band ripple is designed below
b1 b2 b3 0.001dB, since the first stage FIR relax the demand of that
1 indicator.
3.25 -4.625 2.8125 512
(3) CIC filter
CIC filter is very effective in high-speed decimation
and interpolation system. It can complete more than two
times of interpolation and provide sufficient noise
suppression without using any multiplier unit and only cost
little memory. Compared with half-band filter or low-pass
filter, CIC is much more efficient. The structure of CIC
filter is also very simple, consisting of only integrators and
differentiators circuits, and the arithmetic is strictly
additions and subtractions.
To increase the stop band attenuation, a five-stage
CIC filter is used in this design. To maximize the amount of
Fig.2 Output PSD by behavioral simulation
low sample rate processing and minimize power
consumption in high-speed hardware applications, the
upsampler is allocated in the middle of integrator and
differentiator sections. It also makes the amount of the

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 2012 International Conference on Optoelectronics and Microelectronics (ICOM)

delay cells used in the differentiators reduced to 1/32. The transistors compared with a full-adder. Considering the
upsampling is accomplished just through the 32-times delta-sigma DAC system usually contain 16-48bits in
higher frequency clock sampling the lower clock rate data digital signal processing, the classical CSD method will
and does not need any special hardware. The sampling cost much more MOS transistors, which would significantly
frequency of digital signal becomes 128f at the output of increase circuits complexity and power consumption.
CIC. The CSD coding given in the following will produce
a CSD coding with the minimum number of nonzero terms,
B. Optimization and implementation
but also with the minimum number of subtractions.
(1) Folded structure First of all, Substitute all 1 sequences larger than two
For FIR filter’s coefficients being symmetrical about −

the quarter of sample rate, the polyphase structure is applied with 1 0 ...0 1 from LSB. Also replace 1011 with 1101.
−
in half-band and low-pass filter to reduce the number of Then, starting with the MSB, substitute 1 0 1 with 011.
multiplications by means of the folded structure, as fig.3 The optimal CSD code saves extra hardware cost in an
and fig.4 depict. efficient way.
C. Results
Table.2 shows the specifications of interpolator filter
and the overall of frequency response is depicted in fig.5
after realizing with Verilog code. Test results is illustrated in
Fig.6 that stop-band attenuation is -92dB lower than signal
and the bottom of noise power is -140dB compared with
input signal.

TABLEⅡ SPECIFICATIONS OF INTERPOLATOR FILTER

Parameter Performance Unit

Pass-band 0.4535 π
Fig.3 Folded structure of half-band filter Stop-band 0.5465 π
Pass-band ripple 0.001 dB
Stop-band attenuation -92 dB

Fig.4 Folded structure of lowpass filter

(2) Optimal CSD code
The classical CSD code starts with the LSB and Fig.5 Interpolator filter frequency response
substitutes all 1 sequences equal or larger than two
−
with 1 0 ...0 1 . This method clearly reduces the number of 1
which decreases shifting and adding times and save
hardware cost simultaneously. Whereas, classical CSD
coding does not always produce the optimal CSD coding in
terms of hardware complexity, because additions are also
substituted by subtractions, when there should be no such
substitution.
−
For instance 011 are coded as 1 0 1 in CSD, and if
this coding is used to produce a constant multiplier the
subtraction will need a full-adder instead of a half-adder for
the LSB. We can take a simple single digit adder as an
example; the half-adder usually saves more than ten MOS
Fig.6 Interpolator filter SNR analysis

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 2012 International Conference on Optoelectronics and Microelectronics (ICOM)

IV. ANALOG RECONSTRUCTION FILTER WITH

SWITCHED-CAPACITOR TECHNOLOGY 1 2

N1 P1 N2 P2

A. System modeling COM+

COM-

Considering the relationship between the order of P3

3
N3 P4

4
N4

delta-sigma modulator and analog reconstruction filter [7],

a four-order switched-capacitor Bessel reconstruction filter
is employed in this paper. Switched-capacitor technology Fig.8 Analog reconstruction filter
can realize big resistance precisely by MOS switch and
capacitor. Meanwhile, a Bessel filter is adopted in this paper.
To be more specific, Bessel structure has a flat magnitude
and phase response of pass-band. It can provide the same
amount of delay for all frequencies which is crucial for
audio products.
The liner model is described in fig.7 and STF can be
expressed as:
aa a3a4
H(z) = 1 2
* (4)
2 2
(z −1) + a2 (z −1) + aa
1 2
(z −1) + a3 (z −1) + a3a4

Fig.9 Results of post-simulation

V. CONCLUSION
Fig.7 Analog reconstruction filter liner model A third-order cascade-of-resonators feed-forward
The gain coefficients of every integrator is designed Delta-Sigma Modulator introducing zero optimization has
in Matlab and make sure the frequency of -3dB located at been employed. Meanwhile, an area-efficient three-stage
around 22 KHz. The coefficients of analog reconstruction interpolator filter is introduced to realize 128 OSR by
filter are listed in table 3. means of OCSD code and folded structure. A four-stage
switch-capacitor Bessel analog filter is used to reconstruct
TABLE3 COEDDICIENTS OF ANALOG RECONSTRUCTION FILTER
the analog signal. The 16-bit 5.6-MHz clock-rate DAC is
A1 A2 A3 A4 implemented in 0.18-μm CMOS and achieves 96dB-SNR
1/45 1/15 1/25 1/25 for a 22 KHz signal bandwidth
B. Implementation and results References
Non-inverting switched capacitor integrator that is
insensitive to parasitic capacitors is used in every stage of [1] Jae-Wan Kim, Byung-Moo Min,Jang-Sik Yoo, "An Area-Efficient
Sigma-Delta DAC with a Current-mode Semidigital IFIR
analog filter. The value of sampling capacitor is determined Reconstuction Filter," ASIC Lab, Korea University,IEEE 1998.
by following equation and at least 1pf capacitor should be [2] Sun-Hong Kim, Byoung-Wook Kim, Seok-Woo Choi, "Design of
chosen in order to realize 96dB SNR. Oversampling Sigma-Delta DAC for ADSL Applications," Division
v c2m of Information and Communcation Engineering, Woosuk University,
2
(5) IEEE, 2002.
SN R = [3] Noura Ben Ameur, Mourad Loulou, "Design of Efficient Digital
KT
Interpolation Filters and Sigma-Delta Modulator for Audio DAC,"
C * O SR
L 2008 International Conference on Design & Technology of
In this paper, a suitable topology for the Integrated Systems in Nanoscale Era, 2008.
switched-capacitor reconstruction filter in a Delta-Sigma [4] P. Samadi, M.Ahmadi, “Performance Analysis of Genetic Algorithm
DAC is inverted follow the leader feedback configuration. for the Design of Linear Phase Digital Filter Banks with CSD
Coefficients,”ICNC 2007, vol.3, pp. 145 –154, 2007.
The output referred noise from the amplifiers and switched
[5] Binming Luo, Yuanfu Zhao, Zongmin Wang, "An Area-efficient
capacitors is dominated by the first stage components which Interpolator Applied in Audio Σ-△DAC," Third International IEEE
mean the size of the other amplifiers and capacitors can be Conference on Signal-Image Technologies and Internet-Based
reduced. As the reason of that, the sampling capacitor from System, 2008.
2nd to 4th stage could be reduced to 0.5pf if taken chip area [6] Kei-Yong Khoo, Alan Kwentus, Alan N. Willson, Jr, “A
into account. The schematic of analog reconstruction filter Programmable FIR Digital Filter Using CSD Coefficients,” IEEE
Journal of Solid-State Circuits, Vol, 31, NO.6, June 1996.
is shown in fig.8. Results of post-simulation are shown in
[7] Steven R.Norsworthy, Richard Schreier, Gabor C.Temes.
fig.9. The tested signal is -9dB and the in-band noise are "Delta-Sigma Data Converters," New York, IEEE Circuits&Systems
suppressed below -100dB. Society, 1997, pp.309-444, 1997.

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