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15EC4DCHDL

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11 views2 pages

15EC4DCHDL

Uploaded by

rohit adhikary
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Question Paper

Exam Date & Time: 16-Oct-2020 (09:30 AM - 01:00 PM)

BMS COLLEGE OF ENGINEERING

Autonomous Institute Affiliated to VTU, Supplementary Semester End Examinations October 2020
Verilog HDL Programming [15EC4DCHDL]
Marks: 100 Duration: 210 mins.

ELECTRONICS AND COMMUNICATION ENGG-IV Sem


Answer all the questions.
Instructions: 1. Answer FIVE full questions using the given internal choice
2. Missing data, if any, may be suitably assumed.

1) Explain a typical design flow for designing VLSI IC circuit using the block diagram. (10)

a)
b) Explain the Components of a Verilog Module (6)
c) Explain Rise, Fall, and Turn-off Delays. How they are specified in Verilog. (4)
[OR] Write the gate level description for 4 bit full adder with carry look ahead. (8)
2)
a)
b) Define implicit continuous assignment delay and net declaration delay with an example. (4)
c) Explain the following operators used in Verilog with an example. (i) Logical (ii) Replication (iii) Shift (8)
(iv) Conditional
3) Explain sequential and parallel blocks with examples. (8)

a)
b) Explain different loop statements in Verilog. (8)
c) Write a Verilog behavioral description 4 to 1 Multiplexer program using CASE statement. (4)
[OR] Explain the differences between Tasks and Functions. (4)
4)
a)
b) Explain Automatic (Recursive) Functions with an example. (8)
c) Write the syntax for Task Declaration and Invocation. (8)
5) Explain Synthesis Design Flow with a neat block diagram. (8)

a)
b) Explain the mapping the case statement. (4)
c) Explain Horizontal partitioning and Vertical Partitioning. (8)
6) Briefly explain the generic architecture of FPGA. (8)

a)
b) Explain the following: i) FPGA based system design ii) Spartan-III (12)
7) Design serial adder using Moore machine. Write state diagram, state table & expressions for the (10)
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same.
a)
b) Write Verilog code for shift register. (6)
c) Explain One-Hot encoding in FSM designing. (4)

-----End-----

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