Chapter 4

Sequential Circuits

Introduction

◼ A sequential circuit contains

◼ Storage elements
◼ Latches or Flip-Flops
◼ Combinational Logic
◼ Implements a multiple-output switching function
◼ Inputs are signals from the outside.
◼ Outputs are signals to the outside.
◼ Other inputs, State or Present State, are signals
from storage elements.
◼ The remaining outputs, Next State are inputs to
storage elements

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 Introduction

◼ Block diagram
◼ Outputs are function of inputs and present
state of the storage elements
◼ Feedback system
◼ Storage elements are either latches or flip-flops
◼ Usually flip-flops
◼ Abbreviation: “FF”

Types of Sequential Circuits

◼ Synchronous and Asynchronous

◼ Complex sequential circuits require
synchronous
◼ Synchronous
◼ Behavior defined from knowledge of its
signals at discrete instances of time
◼ Storage elements observe inputs and can
change state only in relation to a timing signal
(clock pulses from a clock)
◼ Clock timing forces these circuits to have
built-in fixed time intervals in which the states
and outputs are known 4

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 Types of Sequential Circuits

◼ Asynchronous
◼ Behavior defined from knowledge of inputs at
any instant of time and the order in
continuous time in which inputs change
◼ Lack of clock timing allows these circuits to
change states at any time based on input
changes and current state changes
◼ If clock just regarded as another input, all
circuits are asynchronous

Clocked Sequential Circuit

◼ Block diagram

Next State

Present State

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 Gate Propagation Delay

◼ Affects system response time and when

states can change
◼ Sequential circuits require delay because
of the feedback connections
◼ Cumulative gate delays are always present
and are variable and
◼ Can cause problems
◼ Synchronous systems eliminate most of
the cumulative gate delay issues
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Gate Delay Models

◼ Suppose gates with delay n ns are

represented for n = 0.2 ns, n = 0.4 ns,
n = 0.5 ns, respectively:

0.2 0.4 0.5

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 Circuit Delay Models
◼ Consider a 2-input multiplexer
◼ Function:
◼ Y = A for S = 1
◼ Y = B for S = 0

Circuit Delay Models

◼ Timing diagram shows signal changes with

time
◼ Inverter delay causes inputs to top AND
gate to arrive at different times
◼ Result is a “glitch”
◼ Narrow pulse – almost always undesired

Glitch 10

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 Latches

◼ Storage element can maintain a binary

state (1 or 0) indefinitely as long as power
to circuit
◼ Latches and flip-flops
◼ Latches are simplest

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S-R Latch – NOR Gates

◼ Cross-coupled NOR gates

◼ Inputs labeled R for “reset” and S for “set”
◼ The “1 1” input state is undefined
◼ Output could be either set or reset state
◼ Designer needs to make sure this input combination does not occur

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 NOR S-R Latch Timing
Simulation
◼ Input signal levels are changed to cover
all the possibilities
◼ Input waveform generators take the place of
manual switches
◼ Q_b is “Q bar” – often written as /Q

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/S - /R Latch With NAND Gates

◼ Cross-coupled NAND gates

◼ Opposite input polarity vs. NOR version
◼ Output polarity for Q and /Q are the same
◼ The “0 0” input state is undefined
◼ Output could be either set or reset state
◼ Designer needs to make sure this input combination does not
occur

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 /S - /R Latch With Control Input

◼ Control input “enables” the /S and /R inputs

◼ /S and /R inputs won’t get through if C is low

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D-Latch

◼ Eliminates the undefined input situation

◼ Replace S and R inputs with single D
◼ D input often called “data input”
◼ D value will pass through to output only when
C is high

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 Flip-Flops (FFs)

◼ Having latch outputs able to change when

a C input is high is undesirable in
sequential circuits
◼ Feedback allows the combinational block to
change states and therefore, inputs to latches
would change
◼ Prefer a “latch” where output only
changes on a control input transition
◼ Cascading two latches will do this
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Negative-Edge-Triggered D FF

◼ Cascade a D latch followed by a S-R latch

◼ Left latch samples D input and changes output when
clock C is high
◼ The right latch sees the D latch’s values but does not
react until C goes low
◼ Output latch changes state on negative clock edge
◼ Input latch cannot change when C is low

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 Positive-Edge-Triggered D FF

◼ Switch C input polarity

◼ Left latch samples D input and changes output when
clock C is low
◼ The right latch sees the D latch’s values but does not
react until C goes high
◼ Output latch changes state on positive clock edge
◼ Input latch cannot change when C is high

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More on Edge-Triggered D FFs

◼ A slight delay between input latch

changing state and output latch clock
input is important
◼ The input latch’s outputs must be stable
before the clock changes the output
latch’s state

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 Standard FF Graphics Symbols

Pulse triggered (not edge)

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Interpreting FF Graphics Symbols

◼ For all shown, inputs are on left, outputs

on right
◼ Bubble on output means it’s value is
complement of the “normal” output
◼ For latches
◼ Bubble on inputs means that set-reset occurs
with 0 logic signals
◼ “C” without bubble means triggering on 1
level
◼ “C” with bubble means triggering on 0 level
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 Interpreting FF Graphics Symbols

◼ For pulse-triggered FFs

◼ Triggering pulse polarity is positive without
bubble and is negative with bubble
◼ The “  ” symbol indicates the output changes
at the end of the pulse
◼ For edge-triggered FFs
◼ Triangular arrowhead symbol indicates edge
triggered
◼ Negative edge triggered has a bubble on C input

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Direct Inputs

◼ Direct inputs set or reset a FF without

using the control or clock input trigger
◼ Used to put all FFs in a known state when the
system powers up
◼ This is essential
◼ Also adds flexibility to FF function

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 Direct Inputs

◼ D FF with direct set/reset

◼ It has edge-triggered clock function and
simple /S-/R function

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Sequential Circuit Analysis

◼ Behavior of sequential circuit is

determined by
◼ Inputs
◼ Outputs
◼ Present state
◼ Synchronous sequential circuit has FFs
driven by clock inputs with direct inputs
unused

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 Sequential Circuit Analysis

◼ Synchronous sequential circuit example

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Input Equations

◼ Boolean logic circuits create FF inputs

◼ Boolean equations are the FF input equations
◼ FF outputs are denoted in equations by the FF
input symbol with subscript denoting the FF
output variable name
◼ Example: DA
◼ Example circuit Boolean equations
DA = AX + BX
For FF inputs
DB = AX
Y = ( A + B) X 28

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 State Table

◼ Describes relationships between inputs, outputs,

and FF states
◼ Note that for each possible input combination,
Present state row is repeated because the next state
could be different
◼ Present state is for time t and next state is for one
clock period later t+1
◼ Output is for time t

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State Table

◼ One-dimensional state table for example

circuit

Like typical truth table rows 30

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 State Table

◼ Deriving state table

◼ List all possible binary combinations of present state
and inputs
◼ The example has 8 combinations (23)
◼ Next state values determined by logic diagram or FF
input equations
◼ For a D FF, A(t+1)=DA(t)
◼ So for the A FF , B FF and Y

A(t + 1) = DA = AX + BX
B (t + 1) = DB = AX
Y = ( A + B ) X = AX + BX 31

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State Table

◼ Two-dimensional truth table

◼ Present state combinations determine how many
rows
◼ Input combinations listed across top with the next
state and output, creating more columns

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 State Table

◼ Mealy and Moore sequential circuit models

◼ Named after inventors
◼ Mealy model circuit
◼ Outputs depend on the inputs as well as the
present states
◼ Example circuit is a Mealy model because the
output Y depends on input X as well as
present state
◼ Moore model circuit
◼ Outputs depend only on the states 33

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State Table

◼ Moore model example

◼ Output Z only depends on the state A

DA = X  Y  A FF input equation
Output equation
Z=A
(no input involved) 34

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 State Diagram

◼ Graphical version of state table

◼ Circles are the states with the binary value
inside
◼ Arrows connect states (next state) depending
on input values while at that present state

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State Diagram
◼ State diagram for first example circuit (Mealy circuit)
At present state Input/output values as X/Y during present state.
00 with input Output shown next to input since this circuit’s output
X=0, stay at state depends directly on input – a Mealy output
00 on next clock
At present state 00 with
input X=1, move to state 01
With input X=0 at
on next clock
present state 00
output is Y=0
With input X=1 at present
state 00, output is Y=0
Denoted “0/0”
Denoted “1/0”

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 State Diagram
◼ State diagram for first example circuit (Mealy circuit)

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State Diagram
◼ State diagram for second example circuit (Moore circuit)
State and output value shown as “state/output” inside circle
since output depends only on present state – a Moore output

Input combinations as XY
At present state 0
with input XY=00
or XY=11, stay at
state 0 on next
clock
At present state 0 with input XY=01 or
Output is 0 while XY=10, move to state 1 on next clock
at this state
Output is 0 while at this state
Denoted “0/0”
inside circle Denoted “0/0” inside circle
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 State Diagram Recap

◼ State diagram is graphical version of state

table
◼ Sequential circuit (aka “sequential machine”
or “finite state machine”) has two basic
models
◼ Mealy model or Moore model
◼ Can be a combination of both

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State Diagram Recap

◼ Mealy model
◼ Output depends on inputs and present state
◼ Output values shown on state transition
arrows following a “/”
◼ Moore model
◼ Outputs depend only on that present state
◼ Output values shown in the circles for the
states following a “/”
◼ Pure Moore model will not have output value
shown on a transition arrow
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 State Diagram Recap

◼ Other example state diagrams where x is

the input and y is the output
◼ Mealy or Moore? x=1/y=0
x=0/y=0
x=0 0 1

0/0 x=0/y=0 x=1/y=1

x=0

x=1 x=1
x=0

1/0 2/1
x=1
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State Table Recap

◼ Mealy model state table maps input and present

state to outputs Present Next State Output
◼ Input is “x” State x=0 x=1 x=0 x=1
0 0 1 0 0
1 0 1 0 1

◼ Moore model state table maps present state to

Present Next State Output
output State x=0 x=1
◼ Input is “x” 0 0 1 0
1 0 2 0
2 0 2 1
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 Sequential Circuit Simulation

◼ Input patterns are applied in sequence

along with clock pulses
◼ Simulation begins with a circuit reset to
set the initial state
◼ Gate and FF propagation delays are
accounted for
◼ Timing diagram is the result

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Sequential Circuit Simulation

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 Sequential Circuit Design
Procedure
1. Specification for circuit
2. Formulation with state table or state
diagram
3. State assignment
◼ Create a state table if only have a state
diagram
◼ Assign binary codes to states in the table

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Sequential Circuit Design

Procedure
4. Write flip-flop input equations
◼ Select FF types you want
◼ Derive input equations from next-state entries
in encoded state table
5. Write circuit output equations from
output entries in state table
6. Optimize FF input equations and circuit
output equations

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 Sequential Circuit Design
Procedure
7. Technology mapping
◼ Start with a logic diagram for the equations
that works
◼ Modify to fit the available gates and FFs
8. Verify design

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Finding State Diagrams and

Tables
◼ Understand that a state is used to
remember something about the history of
input combinations and applied during
clock transitions
◼ Think through what conditions are
necessary to remain in a current state or
move to another one
◼ May need to write this out in words or a flow
chart
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 Finding State Diagrams and
Tables
◼ Look for opportunities to reduce the
number of states
◼ Establish an initial state for the system at
power on using a global reset signal

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Ex.: Find State Diagram for

Sequence Recognizer
◼ Specification:
◼ Circuit must recognize the sequence of bits
1101 arriving at the input
◼ Order is from left to right: 1 first, 1 second …
◼ Output Z will go high when the last arriving
correct bit (a 1 in this cas) arrives
◼ Otherwise Z = 0
◼ Circuit needs to remember previous 3 bits

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 Ex.: Find State Diagram for
Sequence Recognizer
◼ Which model? Moore? Mealy?
◼ Output Z will go high when last correct bit arrives
at input, so output depends on states and input
◼ System needs to be reset initially

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Ex.: Find State Diagram for

Sequence Recognizer
◼ Start state diagram
◼ Identify initial reset state as “A”
◼ State B: If a 1 occurs at input, it is first
“correct” sequence bit and must be
remembered so create next state B that
occurs when input is 1
◼ Output remains at 0

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 Ex.: Find State Diagram for
Sequence Recognizer
◼ State B: If a 1 occurs at input, it is first
“correct” sequence bit and must be
remembered so create next state B that
occurs when input is 1
◼ Output remains at 0
◼ State C: If another 1 arrives while at stat B,
then move to state C because this is the next
correct bit
◼ Output Z is still 0

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Ex.: Find State Diagram for

Sequence Recognizer
◼ State D: If a 0 comes in while in state C, that
is the next correct bit, then move to state D
◼ While in state D, if a 1 arrives, the complete
correct sequence has occurred
◼ Set Z = 1

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 Ex.: Find State Diagram for
Sequence Recognizer
◼ So far, only the exact correct outcome has
been handled, what if a wrong bit arrives?
Where do we go after a correct sequence?
◼ This is the tricky part as an incorrect bit in one
position of the sequence does not mean you have
to start all over again

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Ex.: Find State Diagram for

Sequence Recognizer
◼ Need to handle transitions (or not) due to any
possible input bit, not just correct one
◼ For example, the 1 that arrived while in state D
can be the first 1 in the next correct sequence
◼ So from state D when it outputs Z = 1 for correct
sequence, return to state B as this last input 1 is the first
1 of the next correct sequence
◼ While in state D, if a 0 comes in, we would have
received 1100 as the last 4 bits
◼ This time we need to return all the way back to the
beginning because two 0s in a row do not fit the correct
1101 pattern at any time

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 Ex.: Find State Diagram for
Sequence Recognizer
◼ State C represents the first 2 bits “11” correct
◼ If a 0 comes in at C, we move to D as already
determined because we just received “110”
◼ If a 1 comes in at C, it’s 3 1’s in a row “111”, which isn’t
correct, but the last 2 are still part of a correct sequence,
◼ So remain at C if a 1 comes in

◼ State B represents the first bit of the correct

sequence is 1
◼ If a 1 comes in, we move to C as already determined
◼ If a 0 comes in, “10” is not a correct start to the
sequence and we need to return to state A

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Ex.: Find State Diagram for

Sequence Recognizer
◼ State A is the starting point
◼ If a 1 comes in, we move to B as already determined
◼ If a 0 comes in, “0” is not a correct start of the
sequence, so remain at A

◼ Final state diagram

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 Ex.: Find State Table for
Sequence Recognizer
◼ The state table for the diagram is

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State Assignment for Sequence

Recognizer
◼ States are maintained as flip-flop outputs
◼ Need to assign the four states A, B, C, D
to binary numbers

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 State Assignment for Sequence
Recognizer
◼ Two methods
1. Use a binary “counting” sequence
◼ There are 4 states, so binary numbers 00, 01, 10, and 11
are appropriate
◼ Choosing Gray code sequence 00, 01, 11, 10 instead
makes it easier to use with K-maps
2. Have only one flip-flop output active for each
state
◼ Each state represented by a single 1
◼ This would mean 4 flip-flops needed
◼ Also known as “one-hot” code
◼ Acts like a “token passing” where the token is the 1 and
it moves from state to state
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State Assignment for Sequence

Recognizer – Gray Code
◼ State table based on Gray code using 2
FFs

Original
Scheme
A
B
C
D

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 State Assignment for Sequence
Recognizer – One Hot
◼ State table based on one-hot using 4 FFs

Original
Scheme
A
B
C
D

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Ex. Sequence Recognizer Gray

Code Design
◼ State diagram, state table, and state
assignment already done
◼ From state table use the two variables A and
B and input X for Boolean equations
◼ Redraw state table to show A, B, X on left
◼ Choose D FF

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 Ex. Sequence Recognizer Gray
Code Design
◼ Revised state table showing next state as DA and DB

Present State Input Next State Output Z

A B X A (DA) B (DB) 0
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 1 0
1 1 0 1 0 0
1 1 1 1 1 0
1 0 0 0 0 0
1 0 1 0 1 1 65

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Ex. Sequence Recognizer Gray

Code Design
◼ Create D FF input equations with
◼ Present state values and input (A, B, X) as
“inputs” and next state values as “outputs”

A(t + 1) = DA =  m ( 3, 6, 7 )
B (t + 1) = DB =  m (1,3,5, 7 )

◼ Create Z output equation from present

state values and input (A, B, X) as “inputs”
Z =  m ( 5 ) = ABX
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 Ex. Sequence Recognizer Gray
Code Design
◼ Reduce A(t+1) and B(t+1) equations using
K-maps X X
AB 0 1 AB 0 1
0 1 0 1
00 00 1
2 3 2 3
01 1 01 1
6 7 6 7
11 1 1 11 1
4 5 4 5
10 10 1

DA = AB + BX DB = X
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Ex. Sequence Recognizer Gray

Code Design
◼ Logic diagram

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 Ex. Sequence Recognizer Gray
Code Design
◼ Map technology to NANDs and inverters

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Flip-Flop Timing

◼ Setup time – ts
◼ Minimum time that S, R, or D inputs must be
fixed level before the clock transition causing
FF to change state
◼ Hold time: th
◼ Minimum time that S, R, or D inputs must
remain at fixed level after clock transition
causing FF to change state
◼ Clock pulse width: tw
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 Flip-Flop Timing

◼ Propagation delays
◼ Interval between triggering clock edge and
stabilization of output to a new value
◼ High-to-low prop delay: tPHL
◼ Low-to-high prop delay: tPLH
◼ Prop delay (general): tp−
◼ Where min or max follows the “−”

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Flip-Flop Timing Diagram

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 Sequential Circuit Timing

◼ The maximum input-to-output delay

including combinational logic and FF
propagation delays limits the maximum
clock frequency, fmax

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Sequential Circuit Timing

◼ Minimum allowable clock period tp = 1/fmax

◼ Slack time tslack is extra margin time in
clock period
◼ Timing paths

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 Sequential Circuit Timing

◼ Require

(
t p  max t pd , FF + tCOMB + ts )

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Ex.: Sequential Circuit Timing

◼ For FF timing parameters ts = 0.1 ns,

tpd = 0.2 ns
◼ Let maximum delay of combinational logic
be tpdCOMB = 1.3 ns
◼ Find tp and fmax
t p = t pd , FF + tCOMB + ts = 0.2 + 0.1 + 1.3 = 1.6 ns
1
f max = = 625 MHz
1.6 10−9
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 Ex.: Sequential Circuit Timing

◼ Note that this clock frequency is

unrealistic as some slack time must be
added to the clock period to account for
delay variations

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Asynchronous Interactions

◼ Synchronous/asynchronous interaction
◼ Sequential systems often have asynchronous
inputs

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 Synchronization

◼ Asynchronous inputs can cause problems

in synchronous systems
◼ Can cause FF setup time violations
◼ Can lead to metastability – FF output neither 0 nor
1 but in between
◼ Eventually the output will settle to 0 or 1, but not
before other gates are affected
◼ Results can be unpredictable
◼ Need to synchronize the asynchronous
inputs using clocked FFs
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Synchronization

◼ Synchronous system with asynchronous

input

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 Synchronization

◼ Synchronous system with synchronized

asynchronous input

Synchronizing FF

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