Chapter 3

Combinational Logic Design

Hierarchical Design

◼ Create low-level logic “building blocks”

that perform basic functions
◼ Combine them as needed to create more
complex functions

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 Hierarchical Design

◼ Steps in hierarchical design

1. Specify desired behavior
2. Formulate relationship between inputs and
outputs with truth table, Boolean expression,
etc.
3. Optimize the design with Boolean algebra
reduction or K-maps
4. Map optimized logic to available technology
◼ May require changing logic gates from
original design
5. Verify the design
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Ex.: 4-Bit Equality Comparator

Design
◼ Specification
◼ Compare two binary vectors to determine if
they are equal or not
◼ Inputs: A(3:0) and B(3:0)
◼ A bits are A(3), A(2), A(1), A(0)
◼ B bits are B(3), B(2), B(1), B(0)
◼ Output is single bit E = 1 if arrays equal, E =
0 if unequal

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 Ex.: 4-Bit Equality Comparator
Design
◼ Formulation (without truth table this time)
◼ Each corresponding bit of A and B array must
be equal
◼ Test each corresponding bit
◼ All tests must show that bits are equal for
output E = 1
◼ Use 4 comparison circuits MX
◼ Use 1 circuit ME combining MX outputs

Ex.: 4-Bit Equality Comparator

Design
◼ Block diagram

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 Ex.: 4-Bit Equality Comparator
Design
◼ Optimization
◼ Choose output of MX to be 0 for Ai and Bi are
equal and 1 if unequal
Ni = Ai Bi + Ai Bi

Recognize the function?

◼ Use 4 copies of the MX circuit (lowest level in

hierarchy)
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Ex.: 4-Bit Equality Comparator

Design
◼ The ME function generates output 1 when all
Ni values are 0 and output 0 otherwise
◼ An OR gate would produce a 1 if any ME output is 1
and we want the opposite (complement), so NOR

E = N 0 + N1 + N 2 + N3

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 Ex.: 4-Bit Equality Comparator
Design
◼ A hierarchical representation
◼ Uses primitives – simple gates – at lowest levels as
“leaves” in the tree
◼ Branches are the MX and ME blocks with the root
being the overall function
◼ MX blocks are reusable in the design
◼ They must be implemented separately as instances in the
actual circuit

Ex.: 4-Bit Equality Comparator

Design

Simplified representation
showing reusable blocks
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 Technology Mapping

◼ Demonstrate by using NAND and NOR

gates as the available technology
◼ Logic circuit must map to these gates
◼ NAND and NOR gates can be faster than AND
and OR, so good motivation to use them

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Technology Mapping

◼ Let the NAND technology have available

cells with 1, 2, 3, and 4 inputs
◼ Call them Inverter, 2NAND, 3NAND, 4NAND
◼ Let the NOR technology have available
cells with 2, 3, and 4 inputs
◼ Call them 2NOR, 3NOR, 4NOR

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 Technology Mapping

◼ Convert from AND and OR gates in a SOP

or POS expression (or truth table) to
NAND and NOR as follows
1. Replace each AND and OR gate with NAND
(NOR) gate and inverter equivalent circuits
◼ Mapping to NAND

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Technology Mapping
◼ Notice the last conversion uses DeMOrgan’s theorem on
the OR gate (which creates an inversion of OR) and then
a last inversion with the bubble at the AND output
(NAND)

F = A + B + C  F = A + B + C = ABC
DeMorgan’s

F = F = ABC

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 Technology Mapping
◼ Mapping to NOR

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Technology Mapping
◼ Notice the first conversion uses DeMorgan’s theorem on
the AND gate (which creates an inversion of AND) and
then a last inversion with the bubble at the AND output
(NAND)

F = ABC  F = ABC = A + B + C
DeMorgan’s

F = F = A+ B +C

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 Technology Mapping

2. Cancel all inverter pairs

3. Repeat the following pairs of actions until
there is at most one inverter between
a. A circuit input or driving NAND gate output and
b. The attached NAND gate inputs

Dot

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Ex.: NAND Gate Implementation

◼ Implement the following with NAND gates

F = AB + ( AB)C + ( AB) D + E
1. Replace ANDs with NANDs followed by
inverters
Replace OR by NAND with inverters on each
input

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 Ex.: NAND Gate Implementation

2. Cancel inverter pairs 1, 2 and 3,4

3. Push inverter 5 through the dot
◼ Then cancel inverters 5 with 6 and 5 with 7

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Ex.: NAND Gate Implementation

◼ Result

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 Ex.: NOR Gate Implementation

◼ Implement the following with NAND gates

F = AB + ( AB)C + ( AB) D + E
1. Replace ANDs with NORs with inverted inputs
Replace OR by NOR with inverter on output

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Ex.: NAND Gate Implementation

2. Cancel inverter pair on D input line

3. Push inverter 1 through the dot
◼ Then cancel inverters 1 with 2 and 1 with 3
◼ Result

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 Important Observation for NOR
and NAND Implementations
◼ Product of sums (POS) form works better
for NAND implementation
◼ Sum of products (SOP) form works better
for NOR implementation

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Rudimentary Logic Functions

◼ Value fixing, transferring, inverting

◼ Input = X, output = F

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 Rudimentary Logic Functions

◼ Value fixing, transferring, inverting

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Rudimentary Logic Functions

◼ Multi-bit function
◼ Need to represent bit combinations into parallel
“busses” and splitting up busses into bits
Which Extracted
Slash with number wires are functions
indicates how many extracted
bits in the bus

Order (position) of
a function’s wire in
the bus 26

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 Enabling

◼ An “enable” is a signal bit used to allow

another signal through a gate
◼ For an OR gate, if the enable is 0, then the
other signal is allowed through
◼ For an AND gate, if the enable is 1, then the
other signal is allowed through

EN

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Decoding

◼ Maps (converts) n-bit binary input code to

m-bit binary output code where
n  m  2n
◼ Mappings are unique
◼ Input bit combinations do not have to have a
corresponding output
◼ Called n-to-m line decoders

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 1-to-2 Line Decoder

◼ Truth table and circuit

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2-to-4 Line Decoder

◼ Truth table and circuit

◼ Produces output 1 on a line selected by the 2-bit
input code
◼ Each line represents the minterm for that binary value

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 3-to-8 Line Decoder

◼ Start with a 2-to-4 line decoder feeding 8 output

AND gates
◼ Use the 2 LSBs as inputs (A0, A1)
◼ This would produce 2 outputs for each input
combination
◼ Enable only 1 group of 4 AND gates at a time by
using a 1-to-2 line decoder
◼ Ensures only one output
◼ One output feeds 4 AND gates and
◼ The other output feeds the remaining 4 AND gates

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3-to-8 Line Decoder

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 Other Decoder Combinations

◼ The general procedure starts from the

output (on the right) and works toward the
input (on the left)
◼ The largest decoders are closest to the
output
◼ At each level moving toward the input,
smaller decoders are created that drive the
larger one(s) on their right
◼ The procedure ends when you only have 1-
to-2 line decoders connected to the inputs 33
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Other Decoder Combinations

◼ Procedure
1. Let k = n
2. If k is even, divide k by 2
Use 2k 2-input AND gates driven by 2
decoders of output size 2k /2
If k is odd, find (k +1)/2 and (k −1)/2
Use 2k 2-input AND gates driven by one
decoder of output size 2(k +1)/2 and a decoder
of output size 2(k −1)/2

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 Other Decoder Combinations

3. For each decoder from step 2, repeat step 2

with k equal to the values from step 2 until
k=1
For k = 1, use a 1-to-2 decoder

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Ex.: 6-to-64 Line Decoder

First cycle
1. Start with k = n = 6
2. k is even so use 26 = 64 2-input AND gates
fed by two decoders of output size 2k/2 = 23 =
8
◼ These are two 3-to-8 decoders

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 Ex.: 6-to-64 Line Decoder

Second cycle
1. Now k = 3
2. k is odd, so use 23 = 8 2-input AND gates
driven by
◼ One decoder of output size 2(k+1)/2 = 22 = 4
(a 2-to-4 decoder) and
◼ One decoder of output size 2(k−1)/2 = 21 = 2
(a 1-to-2 decoder)

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Ex.: 6-to-64 Line Decoder

Third cycle
◼ From second cycle,
◼ One decoder was a 1-to-2 line, so it is not
reduced further
◼ The other was a 2-to-4 line, so it is reduced
again
1. Now k = 2
2. k is even, so use 24 = 4 2-input AND gates
driven by
◼ One decoder of output size 2k/2 = 21 = 2 (a
1-to-2 decoder) 38

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 Ex.: 6-to-64 Line Decoder

Finish
◼ All decoder expansions (size reductions) are
complete

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Ex.: 6-to-64 Line Decoder

Note
◼ Final output has 64 2-input AND gates in
groups of 8
◼ The top 3-to-8 line decoder has 8 outputs
◼ Each output feeds one of the AND gates in each
group
◼ The lower 3-to-8 line decoder has 8 outputs
◼ Each output feeds all 8 AND gates in one
group
◼ These outputs are “enabling” one group at a time
◼ Just like inside a 3-to-8 line decoder 40

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 Enabling Decoder Outputs

◼ Enabling or disabling an entire functional

block is very useful
◼ Adding an additional AND output stage to a 2-
to-4 decoder allows the EN signal to do this

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Enabling Decoder Outputs

◼ This could have been done by taking the

original 2-to-4 decoder’s AND gates and
converted to them to 3 inputs
◼ But this means we can’t use a basic 2-to-4 line
decoder block

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 1-Bit, 3-Input Binary Adder Using
3-to-8 Line Decoder
◼ A 1-bit binary adder has
the following truth table
◼ Inputs X and Y are the
bits being added and Z is
an incoming carry from
the right
◼ There are 2 independent
outputs even though you
may think they are
dependent

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1-Bit, 3-Input Binary Adder Using

3-to-8 Line Decoder
◼ The decoder produces the minterm values for
its 3-input bit combination
◼ The SOP function realization just requires ORing
the appropriate outputs from the decoder
◼ Function equations:

S =  m (1, 2, 4, 7 )
C =  m ( 3,5, 6, 7 )

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 1-Bit, 3-Input Binary Adder Using
3-to-8 Line Decoder
◼ Implementation
S =  m (1, 2, 4, 7 )
C =  m ( 3,5, 6, 7 )

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Encoding

◼ Encoding - the opposite of decoding –

◼ Converts an m-bit input code to a n-bit output
code where
n  m  2n
◼ Mappings are unique
◼ Circuits that perform encoding are called
encoders

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 Encoders

◼ Have 2n (or fewer) input lines and n

output lines
◼ Generate the binary code corresponding to
the input values
◼ Typical encoder converts a code
containing exactly one bit that selects a
binary code corresponding to the position
in which the 1 appears

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Ex.: Octal-to-Binary Converter

◼ 8-to-3 line encoder

◼ Truth table

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 Ex.: Octal-to-Binary Converter

◼ Each output is given by

A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7

◼ Requires 3 OR gates to implement

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Ex.: Octal-to-Binary Converter

◼ Problem:
◼ If 2 or more inputs are active, output will be
invalid
◼ Solution – use a priority encoder

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 Priority Encoder

◼ Prioritizes inputs so that only one

dominates
◼ For the octal-to-binary converter,
prioritizing the higher subscript (higher
octal number) of simultaneously active
inputs is a good choice

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Ex. 4-Input Priority Encoder

◼ Highest priority is the most significant 1

present
◼ Less significant 1s are unimportant and are
don’t cares X

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 Ex. 4-Input Priority Encoder
◼ The V input means “valid” and is 1
whenever one of the inputs is 1
◼ Truth table is condensed
◼ Row 3 replaces rows
0010
0011
With 0 0 1 X

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Ex. 4-Input Priority Encoder

◼ Row 4 replaces rows
0100
0101
0110
0111
With 0 1 X X
◼ Row 5 replaces 8 rows with 1 X X X

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 Ex. 4-Input Priority Encoder
◼ Each row’s input can be written as a
minterm where an “X” simply doesn’t
appear
A0 = D3 D2 D1 + D3
A1 = D3 D2 + D3
V = D0 + D1 + D2 + D3

◼ Can simplify A0 and A1 equations but not V

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Ex. 4-Input Priority Encoder

◼ K-map for A0
D1D0
D3D2 00 01 11 10
0 1 3 2
00 X 1 1
A0 = D3 + D1D2 01
4 5 7 6

12 13 15 14
11 1 1 1 1
8 9 11 10
10 1 1 1 1

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 Ex. 4-Input Priority Encoder
◼ K-map for A1
D1D0
D3D2 00 01 11 10
0 1 3 2
00 X
A1 = D2 + D3 4 5 7 6
01 1 1 1 1
12 13 15 14
11 1 1 1 1
8 9 11 10
10 1 1 1 1

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Ex. 4-Input Priority Encoder

◼ Logic diagram

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 Selecting

◼ Selecting data or information is a critical

function
◼ Circuits that perform selecting have:
◼ A set of information inputs from which the
selection is made
◼ A single output
◼ A set of control lines for making the selection

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Selecting

◼ Logic circuits that perform selecting are

called multiplexers
◼ Selecting can also be done by three-state
logic or transmission gates

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 Multiplexer (MUX)

◼ A multiplexer selects information from an

input line and directs the information to an
output line
◼ A typical multiplexer has
◼ n selection inputs ( Sn −1 , , S0 )
◼ 2n information inputs ( I 2 n−1 , , I 0 )
◼ One output Y

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Ex. 2-to-1 Line Multiplexer

◼ n = 1, one select bit S

◼ Information bits I1 and I0
◼ S = 0 selects I0
◼ S = 1 selects I1

Y = SI 0 + SI1

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 Ex. 2-to-1 Line Multiplexer

◼ Simplified truth table

S Y
0 I0
1 I1

◼ Circuit and symbol

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Ex. 4-to-1 Line Multiplexer

◼ Simplified truth table S1 S0 Y

0 0 I0
0 1 I1
1 0 I2
1 1 I3
◼ Equation
Y = S1S0 I 0 + S1S0 I1 + S1S0 I 2 + S1S0 I3
◼ Direct implementation requires four 3-input
AND gates, one 4-input OR and two inverters

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 Ex. 4-to-1 Line Multiplexer

◼ Alternate implementation uses a 2-to-4

line decoder with its four 2-input AND
gates feeding another set of AND gates
Y = ( S1S0 ) I 0 + ( S1S0 ) I1 + ( S1S0 ) I 2 + ( S1S0 ) I 3

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Ex. 4-to-1 Line Multiplexer

◼ Circuit

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 Multiplexer Design Summary

◼ Use an appropriate size decoder

◼ Follow the decoder with 2-input AND
gates having
◼ One input is a data input In
◼ The other is a decoder output line acting as
the enable
◼ OR all the AND gate outputs

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Implement 4-Input Function

with 8-to-1 Line MUX
◼ The truth table inputs A, B, C are the
select inputs
◼ The data inputs are D, /D, 0, or 1

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 Implement 4-Input Function
with 8-to-1 Line MUX

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Ex. 1-Bit Binary Adder With

Using MUX
◼ Use a dual 8-to-1 line MUX
◼ One MUX handles the sum output S
◼ The other handles the carry output C
◼ Each MUX produces the minterms selected
by the inputs
◼ The input bits X and Y are the two bits to be
added and Z is the incoming carry bit
◼ All possible combinations appear

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 Ex. 1-Bit Binary Adder With
Using MUX
S output
◼ First subscript is value: MUX 1
minterm number
determined by X, Y
◼ Second is the carry
bit value Z

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BCD-to-Seven Segment Display

Decoder
◼ Activating appropriate segments of a 7-
segment display will show decimal
numbers

◼ 4-input, 7-output circuit

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 BCD-to-Seven Segment Display
Decoder
◼ Truth table

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BCD-to-Seven Segment Display

Decoder
◼ “a” segment equation
a ( A, B, C , D) =  m(0, 2,3,5, 6, 7,8,9)

◼ Others are listed in text

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 BCD-to-Seven Segment Display
Decoder
◼ Using seven 8-to-1 line MUX
◼ Each MUX handles one display segment
◼ Select inputs would be A = S2, B = S1, C = S0
◼ Data inputs I would be as in table below
◼ Inputs would either be D, /D, 1, or 0

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BCD-to-Seven Segment Display

Decoder
◼ Truth table for 7 MUX implementatoin

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 Adders

◼ Binary addition used frequently

◼ Adders are combinational circuits
◼ Versions:
◼ Half-Adder (HA), a 2-input bit-wise addition
functional block,
◼ Full-Adder (FA), a 3-input bit-wise addition
functional block,
◼ Ripple Carry Adder, an iterative array to
perform binary addition, and
◼ Carry-Look-Ahead Adder (CLA), a hierarchical
structure to improve performance. 77

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Half-Adder

◼ Adds two bits

◼ Produces sum and carry outputs
◼ Doesn’t handle carry input
◼ Truth table and circuit
S = XY + XY = X  Y
C = XY

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 Full-Adder

◼ Adds two bits and incoming carry bit

◼ Produces sum and carry outputs
◼ Truth table

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Full-Adder

◼ K-map simplification

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 Full-Adder

◼ Implementation
◼ Two half-adders and OR gate

◼ Notice that S output has 2 gate delays and C output has 3

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Ripple Carry Adder

◼ Modular
◼ Made up of full-adder stages
◼ Each sum bit is produced in parallel
◼ Carry “ripples” through the stages in series
◼ Output delay is longer than sum bits

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 Binary Subtraction – Unsigned
Numbers
◼ Unsigned binary numbers do not use the
MSB as a sign bit (positive or negative sign)
◼ Implement using 2’s complement with
addition
◼ Taking a 2’s complement
◼ Complement each bit individually (bit-wise)
◼ Add 1 to result
◼ Be sure to carry through to higher bits if necessary

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Binary Subtraction – Unsigned

Numbers
◼ Algorithm
◼ Write down minuend (number you are
subtracting from)
◼ Take 2’s complement of subtrahend (number
you are subtracting)
◼ Add it to minuend
◼ Look at the resulting difference
◼ If there is a carry out of MSB, throw it away and
keep the rest (result is positive)
◼ If there is no carry out of MSB, take 2’s complement
of the result and put a “−” sign in front 84

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 Ex. 3-20: Unsigned Number
Subtraction
◼ Let X = 1010100 and Y = 1000011
◼ Perform X – Y, then Y – X

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Ex. 3-20: Unsigned Number

Subtraction
◼ For X – Y first find 2’s complement of Y
1. Bitwise inversion
1000011 → 0111100
2. Add 1 to get 2’s complement: 0111101
◼ Now add 2’s complement of Y to X
Minuend 1010100
2’s Complement of Y + 0111101
Discard carry out
Sum 1 0010001
Answer X – Y 0010001 86

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 Ex. 3-20: Unsigned Number
Subtraction
◼ For Y – X first find 2’s complement of X
1. Bitwise inversion 1010100 → 0101011
2. Add 1 to get 2’s complement: 0101100

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Ex. 3-20: Unsigned Number

Subtraction
◼ Now add 2’s complement of X to Y
Minuend 1000011
2’s Complement of Y + 0101100
No carry out
Sum 1101111

Take 2’s complement of sum: 0010001

Then put “–” in front

Answer X – Y − 00100001 88

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 Binary Adder-Subtractor

◼ Binary subtraction using 2’s complement

followed by addition is implemented below

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Binary Adder-Subtractor

◼ How it works
◼ S bit is 0 for addition, 1 for subtraction
◼ When S = 0 for addition, XOR gates allow B
bits through unaltered
◼ S = 0 bit is the input carry C0 to the LSB full adder
so does nothing
◼ When S = 1 for subtraction, XOR gates invert
B bits
◼ S = 1 bit is input carry C0 so essentially forms 2’s
complement of B

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 Binary Adder-Subtractor

◼ Recall XOR truth table

XOR
B S BS
0 0 0
0 1 1
1 0 1
1 1 0

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Signed-Magnitude Binary
Numbers
◼ Signed-magnitude is convenient
◼ The MSB is the sign bit
◼ Remaining bits are the magnitude
◼ MSB = 0 means positive number
◼ MSB = 1 means negative number
◼ We won’t go over the arithmetic

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 Signed-Magnitude Binary
Numbers
◼ Table for 3-bit
magnitudes
◼ Notice “0” can be
represented two ways

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